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Gabor <gabor@alacron.com> writes: > I thought the only SPI "core" is the one for Microblaze which would > be in the EDK rather than ISE. There's an SPI example for a Xilinx CPLD available somewhere on Xilinx's website. I just remember it was mentioned in this group once. Come to think of it, Altera has an SPI master available too, also in their CPLD pages.Article: 149351
On Oct 17, 3:55=A0pm, rickman <gnu...@gmail.com> wrote: > On Oct 16, 10:55 am, Vips <thevipulsi...@gmail.com> wrote: > > > > > On Oct 15, 11:48 pm, steve ravet <steve.ra...@gmail.com> wrote: > > > > Vipul, this is a pretty standard and common problem in FPGAs. =A0You > > > can't independently synchronize a bunch of control signals when > > > crossing clock domains. =A0They'll all cross individually OK, but > > > there's no guarantee that they'll all end up in the same clock phase > > > on the other side, especially if the destination domain is faster tha= n > > > the source domain. =A0You need to have a send/receive handshake that > > > consists of a single signal, synchronized in both directions. > > > > The control signals that need to cross are flopped directly in the > > > receiving domain without any synchronizers. =A0The handshake signal i= s > > > double flop synchronized and used as an enable on the flops that > > > receive the control signals. =A0By the time the double flopped sync > > > signals make it through to the flop enable, the other control signals > > > are stable and can be safely latched. > > > > An async FIFO is another possibility. > > > > Do a search on clock domain crossing and you'll come up with plenty o= f > > > answers. > > > > --steve > > > > On Oct 13, 1:48 am, jas <thejaspr...@gmail.com> wrote: > > > > > Hi Everyone, > > > > > I am designing a system where I am interfacing a Motorolla processo= r > > > > in my system for read and write data. This processor is on the boar= d > > > > where my fpga will interact with it. The processor is the master mo= de > > > > always and the salave is my interface design and the fpga. > > > > > The motoroll Processor will have LBC Local bus controller signals > > > > will > > > > be comunicating to my interface inside the FPGA. > > > > > The processor can run at configurable clock of 33 MHz to 133 MHz. T= he > > > > address bus is 24 Bits and tye data bus is 32 bits. > > > > > I have to design an interface where the control signals from the > > > > processor to my interface will be > > > > > 1. LALE Used for latching address and making is two distict phases = as > > > > data and address phase. The LALE when HIgh is an Address phase and > > > > when Address is low it is Data phase. =A0(From processor =A0to Desi= gn ) > > > > 2. LWE it is a read and write signal single bit active low. (From > > > > processor =A0to Design ) > > > > 3. LOE Output enable active low =A0(From processor =A0to Design ) > > > > 4. LCS is active low signal from processor to my interface. It is > > > > used > > > > for selecting the chip/slave chip select > > > > 5. LA address 24 bits ( From processor =A0to Design ) > > > > 6. LAD data 32 bits =A0(Bidirectional) > > > > > I am thinking about runing my design at 300 Mhx 3X then the process= or > > > > LBC clock . The LBC clock is not coming from the processor to my > > > > interface in fpga . So in my Interface i dont have the reference > > > > clock > > > > from the processor and all the above mentioned signals are from > > > > Processor to my design except LAD which is bidirectional . > > > > > I am using 2 flop synchronisers for the control signals and MUX-Lat= ch > > > > model for data latching and synchronization across the cock domain = . > > > > > My Confusion is that when we have multiple control signal passing t= he > > > > clock =A0domain . Can we synchronize with 2 flops all the control > > > > signals. > > > > > Shall we use some glue logic to make sure we pass and synchronise > > > > only > > > > one control signal across the domain and later use this synchronous > > > > signal value to select the mux-latch of other control signals that > > > > are > > > > input to a latch and sampled when we get the synchronized signal. > > > > > In the scenario like this has anyone used multiple control signals = to > > > > pass the clock domain throgh individual 2 flop synchronizers for ea= ch > > > > control lines. > > > > > I am using 3X clock in the destination clock domain and has ample > > > > time > > > > to sample the signal in the interface block. > > > > > Any suggestion ideas will be highly appreciated > > > > > Thanks > > > > > Vipul > > > Hi Rick /Steve > > > Thanks for your reply. The processor might send continuous data and i > > don't have the control for the processor. In handshake mechanism the > > processor might have to see my response then send the next data. Rick > > you are right that we can use LOE for read case to latch data in the > > LAD bus. All signals are mutually exclusive and it is typically like a > > async memory interface. > > > I have googled but did dot get any good relevant text on this that > > talk about async memory interface . All talk about CDC issues and > > control and data bus synchronization. I am looking for some thing on > > async memory interface or something that is async and have to be > > synchronized at the interface to be used by other logic in the design. > > I will look into it the way you both have advised. > > > Thanks > > > Vipul > > I doubt that you will find much on how to design your circuit. =A0This > is very basic and you just need to understand the timing and function > of the control signals. =A0Just keep in mind that many signals won't > need to be registered at all if they are stable at the time they are > needed and only control signals need to be double registered for > metastability. =A0If you need any real help, drop me an email and send > me details of your bus and FPGA interface. > > Rick One other reason to register all of the data pins as well as the control lines is to get a delay pipeline. Then you can do things like find the trailing edge of the strobe signal and latch the data from three clock cycles ago. Regards, GaborArticle: 149352
Can you send ur e-mail id, i will send the block diagram, so that you can able to understand easily.Article: 149353
Hi, i'm new with FPGA,so excuse me for my question... Any FPGA is composed by banks, each with its Vdd: IO pins of that bank can be used with each logic with high state and low state between 0- vdd? For example, if Vdd is 3V, i can use IO pins for LVDS signals (1.8V +-200mV)?And for TTL signal 0-5V? ThanksArticle: 149354
Another option would be an XMOS device: http://www.xmos.com They can replace FPGAs in many applications, and are much easier to use.Article: 149355
On Oct 16, 9:55=A0am, Vips <thevipulsi...@gmail.com> wrote: > On Oct 15, 11:48=A0pm, steve ravet <steve.ra...@gmail.com> wrote: > > > > > > > Vipul, this is a pretty standard and common problem in FPGAs. =A0You > > can't independently synchronize a bunch of control signals when > > crossing clock domains. =A0They'll all cross individually OK, but > > there's no guarantee that they'll all end up in the same clock phase > > on the other side, especially if the destination domain is faster than > > the source domain. =A0You need to have a send/receive handshake that > > consists of a single signal, synchronized in both directions. > > > The control signals that need to cross are flopped directly in the > > receiving domain without any synchronizers. =A0The handshake signal is > > double flop synchronized and used as an enable on the flops that > > receive the control signals. =A0By the time the double flopped sync > > signals make it through to the flop enable, the other control signals > > are stable and can be safely latched. > > > An async FIFO is another possibility. > > > Do a search on clock domain crossing and you'll come up with plenty of > > answers. > > > --steve > > > On Oct 13, 1:48=A0am, jas <thejaspr...@gmail.com> wrote: > > > > Hi Everyone, > > > > I am designing a system where I am interfacing a Motorolla processor > > > in my system for read and write data. This processor is on the board > > > where my fpga will interact with it. The processor is the master mode > > > always and the salave is my interface design and the fpga. > > > > The motoroll Processor will have LBC Local bus controller signals > > > will > > > be comunicating to my interface inside the FPGA. > > > > The processor can run at configurable clock of 33 MHz to 133 MHz. The > > > address bus is 24 Bits and tye data bus is 32 bits. > > > > I have to design an interface where the control signals from the > > > processor to my interface will be > > > > 1. LALE Used for latching address and making is two distict phases as > > > data and address phase. The LALE when HIgh is an Address phase and > > > when Address is low it is Data phase. =A0(From processor =A0to Design= ) > > > 2. LWE it is a read and write signal single bit active low. (From > > > processor =A0to Design ) > > > 3. LOE Output enable active low =A0(From processor =A0to Design ) > > > 4. LCS is active low signal from processor to my interface. It is > > > used > > > for selecting the chip/slave chip select > > > 5. LA address 24 bits ( From processor =A0to Design ) > > > 6. LAD data 32 bits =A0(Bidirectional) > > > > I am thinking about runing my design at 300 Mhx 3X then the processor > > > LBC clock . The LBC clock is not coming from the processor to my > > > interface in fpga . So in my Interface i dont have the reference > > > clock > > > from the processor and all the above mentioned signals are from > > > Processor to my design except LAD which is bidirectional . > > > > I am using 2 flop synchronisers for the control signals and MUX-Latch > > > model for data latching and synchronization across the cock domain . > > > > My Confusion is that when we have multiple control signal passing the > > > clock =A0domain . Can we synchronize with 2 flops all the control > > > signals. > > > > Shall we use some glue logic to make sure we pass and synchronise > > > only > > > one control signal across the domain and later use this synchronous > > > signal value to select the mux-latch of other control signals that > > > are > > > input to a latch and sampled when we get the synchronized signal. > > > > In the scenario like this has anyone used multiple control signals to > > > pass the clock domain throgh individual 2 flop synchronizers for each > > > control lines. > > > > I am using 3X clock in the destination clock domain and has ample > > > time > > > to sample the signal in the interface block. > > > > Any suggestion ideas will be highly appreciated > > > > Thanks > > > > Vipul > > Hi Rick /Steve > > Thanks for your reply. The processor might send continuous data and i > don't have the control for the processor. In handshake mechanism the > processor might have to see my response then send the next data. Rick > you are right that we can use LOE for read case to latch data in the > LAD bus. All signals are mutually exclusive and it is typically like a > async memory interface. > > I have googled but did dot get any good relevant text on this that > talk about async memory interface . All talk about CDC issues and > control and data bus synchronization. I am looking for some thing on > async memory interface or something that is async and have to be > synchronized at the interface to be used by other logic in the design. > I will look into it the way you both have advised. > > Thanks > > Vipul Hi Vipul, I'm not familiar with that interface but if it has a valid/ ready type of handshake with the slave then those are the signals that will be double flopped. Valid from the master is double flopped before it gets to the slave, and ready is double flopped from the slave back to the master. That way all of the control or data has crossed safely to the slave before the master is allowed to proceed. If there's no handshake, and the master sends data without waiting for a response from the slave then you may have to go with an async fifo, which has one port in the receiving domain and one port in the sending domain. If you're using relatively recent FPGAs then the block RAMs may incorporate the logic needed for an async FIFO, which gets rid of any CDC considerations from your design. Then the only concern is that the receiving end be able to keep up with the sending end, since the slave has no way of holding off the master. I think you said your slave runs 3x faster than your master so you may already have that problem solved.Article: 149356
You can do all sorts of tricks with synchronizing, but it really boils down to one of two cases: - Synchronous: You should have the bus clock coming from the CPU run into your FPGA, then do everything synchronously on a bus clock domain in the FPGA. To interface to the main logic, you can use an internal FIFO to your main clock domain (or any number of other methods - google "clock domain crossing"). This is the "right" (and possibly only) way to do it if you want to utilize the full bandwidth to the bus. - Asynchronous: Most (possibly all?) Motorolla/Freescale processors have programmable bus timing on their external parallel bus. You can set the timing to give you tons of setup/hold time to allow you to take a snapshot of the data/address lines after the skew has worked itself out. The idea is that you design your FPGA logic to capture the LCS signal through a dual flip flop synchronizer, wait i.e. 10 FPGA clock cycles, then capture the address/data (by which time the data would be stable). The idea is that only one signal is ever dealt with asynchronously (LCS). ChrisArticle: 149357
>Hi, >i'm new with FPGA,so excuse me for my question... >Any FPGA is composed by banks, each with its Vdd: IO pins of that bank >can be used with each logic with high state and low state between 0- >vdd? >For example, if Vdd is 3V, i can use IO pins for LVDS signals (1.8V >+-200mV)?And for TTL signal 0-5V? >Thanks > The user guide will tell you what bank voltage you need for the IO standard you are going to use. I'm not really sure what you are trying to say regarding the LVDS standard. You cant just connect any old voltage onto the bank. Jon --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149358
On Oct 18, 7:13=A0am, Anssi Saari <a...@sci.fi> wrote: > Oliver Mattos <omat...@gmail.com> writes: > > Does any company sell a microprocessor what has a few thousand logic > > elements of FPGA "on the side", which can interface fast with the > > microprocessor, for example through shared memory. =A0Ideally this woul= d > > be cheap (ie. tens of dollars rather than hundreds of dollars), and > > easy to use (I don't want to have to be defining my own DMA controller > > or something...) > > Yes, Actel Smartfusion. It's a hard ARM Cortex M3 with hard basic > peripherals and some programmable logic around that. Also, single 3.3V > power supply. SW tools are free from Actel or you can buy from IAR or > Keil. Eval kit is $99. > > I had a visit from Actel recently, SmartFusion seems very interesting, > but I've never designed anything with their FPGAs. > > It's also interesting to note that Xilinx is going to do the same > thing in their 7 series, hard ARM with hard peripherals ready to go, > programmable logic around it. He is looking for something inexpensive and the SmartFusion devices are not that. Although the OP has only said he doesn't want to pay hundreds of dollars, which does leave the field pretty wide open. As a CPU with FPGA, I see the SmartFusion as an interesting device. But combined with the analog I see it as much more limited. The analog converters are not all that fast and don't have much resolution. The A<>D conversion world covers a very wide range speed/ resolution and a lot of apps won't be suitable to the limitations of SmartFusion capabilities. RickArticle: 149359
On 10/18/2010 04:13 AM, Anssi Saari wrote: > Oliver Mattos<omattos@gmail.com> writes: > >> Does any company sell a microprocessor what has a few thousand logic >> elements of FPGA "on the side", which can interface fast with the >> microprocessor, for example through shared memory. Ideally this would >> be cheap (ie. tens of dollars rather than hundreds of dollars), and >> easy to use (I don't want to have to be defining my own DMA controller >> or something...) > > Yes, Actel Smartfusion. It's a hard ARM Cortex M3 with hard basic > peripherals and some programmable logic around that. Also, single 3.3V > power supply. SW tools are free from Actel or you can buy from IAR or > Keil. Eval kit is $99. > > I had a visit from Actel recently, SmartFusion seems very interesting, > but I've never designed anything with their FPGAs. > > It's also interesting to note that Xilinx is going to do the same > thing in their 7 series, hard ARM with hard peripherals ready to go, > programmable logic around it. I remember a point ten years or so ago when we considered the Atmel FPSLIC (too small, too Atmel), the Altera Cyclone (too Altera), and the Xilinx part with the embedded PowerPC (too PowerPC). We ended up with a plain old Xilinx chip talking to the same little DSP that we were putting in a bunch of other boards at the same time, with a nice fast memory-mapped interface. So, don't overlook a plain old FPGA (or CPLD even) attached to a plain old processor with the high-speed interconnect of your choice. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" was written for you. See details at http://www.wescottdesign.com/actfes/actfes.htmlArticle: 149360
On Oct 18, 9:23=A0am, forks dude <forksd...@gmail.com> wrote: > Can you send ur e-mail id, i will send the block diagram, so that you > can able to understand easily. Looking forward for your reply.Article: 149361
"Tim Wescott" <tim@seemywebsite.com> wrote in message news:8cSdnWRZLOGECCHRnZ2dnUVZ_rWdnZ2d@web-ster.com... > On 10/18/2010 04:13 AM, Anssi Saari wrote: >> Oliver Mattos<omattos@gmail.com> writes: >> >>> Does any company sell a microprocessor what has a few thousand logic >>> elements of FPGA "on the side", which can interface fast with the >>> microprocessor, for example through shared memory. Ideally this would >>> be cheap (ie. tens of dollars rather than hundreds of dollars), and >>> easy to use (I don't want to have to be defining my own DMA controller >>> or something...) >> >> Yes, Actel Smartfusion. It's a hard ARM Cortex M3 with hard basic >> peripherals and some programmable logic around that. Also, single 3.3V >> power supply. SW tools are free from Actel or you can buy from IAR or >> Keil. Eval kit is $99. >> >> I had a visit from Actel recently, SmartFusion seems very interesting, >> but I've never designed anything with their FPGAs. >> >> It's also interesting to note that Xilinx is going to do the same >> thing in their 7 series, hard ARM with hard peripherals ready to go, >> programmable logic around it. > > I remember a point ten years or so ago when we considered the Atmel FPSLIC > (too small, too Atmel), the Altera Cyclone (too Altera), and the Xilinx > part with the embedded PowerPC (too PowerPC). > > We ended up with a plain old Xilinx chip talking to the same little DSP > that we were putting in a bunch of other boards at the same time, with a > nice fast memory-mapped interface. > > So, don't overlook a plain old FPGA (or CPLD even) attached to a plain old > processor with the high-speed interconnect of your choice. > I agree. It can be cost effective, but the best part is that the FPGA code syntheses and fitting is so much faster than a design incorporating a MicroBlaze or equivalent. Sometimes the FPGA code can also be stored in the CPU memory saving a FPGA Flash memory device.Article: 149362
Oliver Mattos <omattos@gmail.com> wrote: > >> "fast" probably isn't an issue, provided I can... > >By "fast" I mean memory mapped IO or DMA or something rather than an >SPI link between an FPGA and a microcontroller... Recent micros will do SPI at >50MHz and have a DMA controller to transfer the data internally. If you want memory mapped I/O then you are moving towards a system-on-chip. -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------Article: 149363
Thanks for your answer, but i have a question... from user guide i saw that LVDS_2.5 requires Vcc=2.5V....i can implement LVDS_2.5 with Vcc=3.3V?Article: 149364
> Thanks for your answer, but i have a question... >from user guide i saw that LVDS_2.5 requires Vcc=2.5V....i can >implement LVDS_2.5 with Vcc=3.3V? > > No, if it says 2.5V then that is the voltage on the bank you need. I believe that some FPGAs like Spartan 6 have a 3.3V LVDS. Jon --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149365
On 18 Okt., 17:04, fasf <silusilus...@gmail.com> wrote: > i'm new with FPGA,so excuse me for my question... > Any FPGA is composed by banks, each with its Vdd: IO pins of that bank Wrong. Some FPGAs have several banks, maybe most, but not every. Please do yourself a favor and start giving detailed information about the device. E.g. write wthat the databook says about this topics. That would really help us giving answers. There is no asnwer to your question that is valid for all Fpgas bye ThomasArticle: 149366
All differential pins can be used as single-ended pins. See the following from Xilinx Spartan-6 UG381: Each IOB contains both input, output, and 3-state SelectIO drivers. These drivers can be configured to various I/O standards. Differential I/O uses the two IOBs grouped together in one tile. =95 Single-ended I/O standards (LVCMOS, LVTTL, HSTL, SSTL, PCI) =95 Differential I/O standards (LVDS, RSDS, TMDS, Differential HSTL and SSTL) =95 Differential and VREF dependent inputs are powered by VCCAUX Each Spartan-6 FPGA I/O tile contains two IOBs, and also two ILOGIC blocks and two OLOGIC blocks BryanArticle: 149367
Hi all, I'm not sure that I asked the best question. Here it is : If I implement any design with ISE, then I use netgen to generate a new verilog netlist (lets call it newNet.v), can I take "newNet.v" and start a new project with it or not? I do not want to run simulation but I want to implement "newNet.v" and synthesize it with XST. The problem now is that "newNet.v" uses SIMPRIM files and "glbl.v" when I use these options with netgen : netgen -w -ecn conformal -ne -mhf clockbuf I looked in the code provided by xilinx, and i found that it is instantiated as follows : tri0 GSR = glbl.GSR; // in X_FF.v for example And the errors are like this : ERROR:HDLCompilers:244 - "../../work/xilinx/opt1/ISE_DS/ISE/verilog/src/simprims/X_FF.v" line 42 Name 'glbl.GSR' could not be resolved ERROR:HDLCompilers:185 - "../../work/xilinx/opt1/ISE_DS/ISE/verilog/src/simprims/X_FF.v" line 42 Illegal right hand side of continuous assign I read in xilinx forum that glbl is only used for simulation !!! That why I want tu use another library for synthesis. Any ideas? Thx again for your help. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149368
On 19 Ott, 13:23, Thomas Stanka <usenet_nospam_va...@stanka-web.de> wrote: > Please do yourself a favor and start giving detailed information about > the device..... You're right...I have a Spartan6 and i want to use its LVDS input...i want to connect LVDS traces to differential I/O pins located in a bank powered by 3.3V. In an earlier version of the board, the same traces are connected to differential I/O pins located in a bank powered by 2.5V. connect LVDS to a bank powered by 3.3V could be a problem?Article: 149369
Dear ALL I am facing this error time to time due to external IP Place:1240 - Placement has failed for the IP core generated by MIG because non-related components have been locked to slice locations required for the MIG core. Please change or remove the location constraints for these non-related components so that they don't conflict with MIG placement. Below is a list of the slice locations, and the component that is currently locked to this location: Slice Location Currently Locked Component ---------------- ----------------------------------- SLICE_X0Y42 mig_33_0/mig_33_0/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[5].u_io b_dq/stg2a_out_fall In my ucf I did not lock this variable some time edk + ise generates bit file but if i do some modification in rapper used to collect data from IP it start giving errors Kindly guide me how to remove those errors (I am not using gen_dq bit in my wrapper) Is there a way to reLOCK this pin or bypass this error Waiting for reply Regards --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149370
Hi Is this syntax is ok to keep a bit open in Xilinx EDK design Net fpga_0_xyz<0> OPEN; In my design I do not want to use few bit and I do not want to edit hdl part. Tell how do I remain it unused at top level --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149371
On Oct 15, 2:13=A0pm, "MM" <mb...@yahoo.com> wrote: > > Where else can Xilinx store pad location constraints? > > Thanks, > /Mikhail There are constraint files created by the Memory Interface Generator. RKArticle: 149372
On Oct 19, 12:48=A0pm, d_s_klein <d_s_kl...@yahoo.com> wrote: > On Oct 15, 2:13=A0pm, "MM" <mb...@yahoo.com> wrote: > > > > > Where else can Xilinx store pad location constraints? > > > Thanks, > > /Mikhail > > There are constraint files created by the Memory Interface Generator. > > RK There are too possibilities that come to mind: 1) The LOC constraint is embedded in the NGC file from synthesis 2) The LOC is inferred from the connectivity and placement of the other elements Ed McGettigan -- Xilinx Inc.Article: 149373
Well, it turned out ISE was picking up either system.ncf or system.ucf created originally by the EDK wizard I believe. They were not explicitly included in the project as far as I could tell. /Mikhail "Ed McGettigan" <ed.mcgettigan@xilinx.com> wrote in message news:e11fa579-3812-4793-899d-d8c9e9390361@w38g2000pri.googlegroups.com... On Oct 19, 12:48 pm, d_s_klein <d_s_kl...@yahoo.com> wrote: > On Oct 15, 2:13 pm, "MM" <mb...@yahoo.com> wrote: > > > > > Where else can Xilinx store pad location constraints? > > > Thanks, > > /Mikhail > > There are constraint files created by the Memory Interface Generator. > > RK There are too possibilities that come to mind: 1) The LOC constraint is embedded in the NGC file from synthesis 2) The LOC is inferred from the connectivity and placement of the other elements Ed McGettigan -- Xilinx Inc.Article: 149374
Please go and read the Spartan 6 DC data sheet and the Select IO guide and I am sure that all your questions will be answered. You are asking questions that you could find out quite easily by yourself. I am not saying I dont want to give you the answer, but in the long term I think it would be better that you did it. Jon --------------------------------------- Posted through http://www.FPGARelated.com
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