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On Sun, 28 Dec 2008 11:12:05 +0200, RealInfo wrote: > Hi all > > I have a litle dream to turn a FPGA based design into a real ASIC so I > can sell this ASIC in the market . > This is an audio processing design aimed at the guitar effects market. > > My question is how much can this venture cost in general . > > A general estimate will be very good . > > Is it realistic to search for an investor ? > > Thanks in advance > EC There are two reasons to build an ASIC, either your volumes are huge (in the millions) or an FPGA can't come close to handling the problem because of speed, size or power consumption. Building a state of the art ASIC (40nm, 65nm) costs millions of dollars, using a non-state of the art process is cheaper but your gains vis-a-vis an FPGA are less. The FPGA companies are the process drivers for their foundries so their current offerings are the first devices (with the exception of Intel which has a 12 month lead over the rest of the industry) that come out in any process. The Altera Stratix 4 is a 40nm part for example. While random logic is inefficient in an FPGA other important features, like RAM and multipliers are as good or better than you are going to get in any ASIC. If you have a significant amount of RAM in your design you might find that the die size of a state of the art FPGA is smaller than the die size for an ASIC that's built in an antique process. Your best bet would be to figure out how to fit your design into the cheapest FPGA that you can.Article: 137151
On Dec 22, 5:24=A0am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote: > Synthesis cannot drive "X" on to an output - there is > no such value in hardware - so the synth tool will assume > that X means don't-care and will choose whichever combination > of 1s and 0s comes closest to meeting its optimisation goals. > In this situation, that means the output will be identical for > wb_we_i=3D=3D0 and wb_we_i=3D=3D0; that input will simply be ignored. Looking at the Xilinx docs, this seems to be true. XST also treats '-' as a don't care. But I have not found anything that says this is true for other synthesis tools. The 'X' value is not intended to indicate a don't care value while the '-' value is listed as "don't care". However none of these have a meaning of "don't care" except for what is provided by the tools. In general, neither 'X' nor '-' can be assumed to mean "don't care" to synthesis tools. In simulation some uses will operate as a "don't care" (std_match function for example) and others won't (if (A =3D "00-1"), for example). I could be mistaken about this if this has been formalized in the last few years. The comp.lang.vhdl FAQ still says that there is no formal "don't care" meaning. http://www.eda.org/comp.lang.vhdl/FAQ1.html#dont_cares RickArticle: 137152
radarman wrote: > The DE1 is a subset of the DE2, which uses almost every single I/O pin > on the FPGA. My guess is that they simply deleted portions of the > schematic and rerouted the board - which explains some of the oddities > you noticed. The upside, however; is that if you ported to the DE2, it > should be almost trivial if necessary at all. Actually, DE2 fixes some of the worst omissions (e.g. RTS/CTS on RS232), although it still doesn't hook up the sense switches on the SD card socket. The DE2 is truly a superboard, and if it was only in the pricerange of my userbase I'd use it. The lack of sense switches on the SD socket bothers me, mostly because it means that there is no way to honor the write protect tab on a card in the design. -hpaArticle: 137153
On Dec 28, 7:48=A0pm, "H. Peter Anvin" <h...@zytor.com> wrote: > radarman wrote: > > The DE1 is a subset of the DE2, which uses almost every single I/O pin > > on the FPGA. My guess is that they simply deleted portions of the > > schematic and rerouted the board - which explains some of the oddities > > you noticed. The upside, however; is that if you ported to the DE2, it > > should be almost trivial if necessary at all. > > Actually, DE2 fixes some of the worst omissions (e.g. RTS/CTS on RS232), > although it still doesn't hook up the sense switches on the SD card > socket. =A0The DE2 is truly a superboard, and if it was only in the > pricerange of my userbase I'd use it. > > The lack of sense switches on the SD socket bothers me, mostly because > it means that there is no way to honor the write protect tab on a card > in the design. Both the switches and the extra RS-232 (EIA-232) signals can be wired by the user. I have done this before on other development boards. It is nice if you have a precise drill tool for drilling out vias, but if you can cut traces instead, that works just as well. Otherwise it is just a matter of being familiar with a soldering iron, no? How much is a DE1 board? RickArticle: 137154
rickman wrote: > > Both the switches and the extra RS-232 (EIA-232) signals can be wired > by the user. I have done this before on other development boards. It > is nice if you have a precise drill tool for drilling out vias, but if > you can cut traces instead, that works just as well. Otherwise it is > just a matter of being familiar with a soldering iron, no? > > How much is a DE1 board? > $150 ($125 for students.) Again, modding the board is one of those things that is easy to do for oneself, but expecting others to do it is iffier. In this case, it's not even all that hard... the SD socket is pretty well exposed, and one can simply wire the pins up to a pair of pins on the GPIO header. -hpaArticle: 137155
Hello, I compared the performance of implementation tools in ISE10.1.03 and in ISE9.02.03. I took the same design and playing with Map options (input functions, optimization strategy) I run multiple routing (100 cost tables) for every map option set in ISE10 and ISE9. I expected ISE10 results to be at least not worse than ISE9 results. In the table below I show the number of results (out of 100 routing started) that meet the timing constraints for every map options in these two ISE versions: Map options ISE 9.2.03 ISE 10.1.03 Input func. 4 / Balanced 7 3 Input func. 5 / Balanced 9 2 Input func. 6 / Balanced 5 3 Input func. 5 / Speed 3 1 Input func. 6 / Speed 0 0 In ISE10 I only got 38% of ISE9 good results (in other words ISE9 is 2.5 times better in this experiment). I don't know what causes ISE10 to be not as good as ISE9? What changed in the mapping/routing algorithm? Maybe synthesis algorithms of XST changed as well? Do you have the same experience with ISE10? I wanted to switch from ISE9 to ISE10 but in this situation I'm not sure. Voltaire once said: Better is the enemy of good. Is it true in this case? Regards WojtekArticle: 137156
Hi all Are there DIP (Dual Inline NOT PLCC ) packed FPGAs offered by ALTERA or XILINX if other vendors then which of them ? Thanks ECArticle: 137157
RealInfo wrote: > Hi all > > Are there DIP (Dual Inline NOT PLCC ) packed FPGAs offered by ALTERA or > XILINX > if other vendors then which of them ? > No, but there are some vendors which sell CPLDs (not FPGAs) mounted on small boards that can fit in DIP sockets. For example: http://www.digilentinc.com/Products/Detail.cfm?NavTop=2&NavSub=419&Prod=CMOD http://www.retrodevices.com/ -hpaArticle: 137158
H. Peter Anvin wrote: > RealInfo wrote: >> Hi all >> >> Are there DIP (Dual Inline NOT PLCC ) packed FPGAs offered by ALTERA or >> XILINX >> if other vendors then which of them ? >> > > No, but there are some vendors which sell CPLDs (not FPGAs) mounted on > small boards that can fit in DIP sockets. > > For example: > > http://www.digilentinc.com/Products/Detail.cfm?NavTop=2&NavSub=419&Prod=CMOD > http://www.retrodevices.com/ And not to forget: http://www.fpgaarcade.com/ttl_replacement.htm -hpaArticle: 137159
RealInfo <therightinfo@yahoo.com> wrote: > I have a litle dream to turn a FPGA based design into a real ASIC so I can > sell this ASIC in the market . > This is an audio processing design aimed at the guitar effects market. > My question is how much can this venture cost in general . > A general estimate will be very good . Probably better to keep it in an FPGA. That is being done now for many that would previously go ASIC as mask costs are rising. Unless your market is in the millions, FPGA is likely a better choice. -- glenArticle: 137160
On Dec 27, 10:05=A0pm, KJ <kkjenni...@sbcglobal.net> wrote: > On Dec 27, 6:08=A0am, rajesh <rajvan...@gmail.com> wrote: > > > =A0 =A0 =A0 thanx for ur concern towards me....i could have done in sin= gle > > process but the problem is like processor is writing so many > > times.some times its writes only 1 bit data and some times 60 BYTE. so > > i can not write in single process. > > > Pleas do somthing if possible > > > -- Rajesh kumar > > Rajesh, > > Your problem description isn't very clear but for a single fifo there > can only be one process that generates the fifo read signal and the > fifo write signal. =A0The logic description that defines when the read > and write signals occur can be as simple or complicated as you like > but still there can only be one process. =A0It generally makes no > difference how many times something will be writing to it (i.e. '1 bit > data' or '60 bytes') since each individual write must be handled > separately. > > Does simply 'or-ing' together the 8 different sources do the trick? > By that I mean take your 8 fifo write signals and give them unique > names (i.e. fifo_wrt_1, fifo_wrt_2...etc.). =A0Then the fifo write > signal that you send to the fifo is simply > fifo_write <=3D fifo_wrt_1 or fifo_wrt_2 or ... > > Not sure that helps much but I'm not quite sure what the problem is > other than you've got one fifo but 8 different sources for writing to > a single fifo. > > Kevin Jennings Thanx kevin it worked whatever you hav given solution.... thanx a lot rajeshArticle: 137161
On Mon, 29 Dec 2008 10:42:08 +0200, "RealInfo" wrote: >Are there DIP (Dual Inline NOT PLCC ) packed FPGAs In addition to the suggestions you've already seen, note the very nifty boards from Enterpoint: http://www.enterpoint.co.uk/component_replacements/craignell.html [Disclaimer: I'm not connected with Enterpoint, but if I were still in university teaching I'd be biting their hands off to get those Craignell boards.] -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 137162
Ever wanted to indent a code that you got from somebody else. I created some scripts for that, which I would like to share as free stuff. Be glad to get comments.Article: 137163
On Dec 29, 1:15 am, "H. Peter Anvin" <h...@zytor.com> wrote: > rickman wrote: > > > Both the switches and the extra RS-232 (EIA-232) signals can be wired > > by the user. I have done this before on other development boards. It > > is nice if you have a precise drill tool for drilling out vias, but if > > you can cut traces instead, that works just as well. Otherwise it is > > just a matter of being familiar with a soldering iron, no? > > > How much is a DE1 board? > > $150 ($125 for students.) Again, modding the board is one of those > things that is easy to do for oneself, but expecting others to do it is > iffier. > > In this case, it's not even all that hard... the SD socket is pretty > well exposed, and one can simply wire the pins up to a pair of pins on > the GPIO header. Just a brief comment. I am sure you have looked at a number of boards and found many that are much more expensive. $150 is not really a bargain however. Is there something that is "special" about this board or is it just that it is the best combination of features you need at the lowest price point you can find? I certainly don't have anything to suggest that would be cheaper with the same features. Mostly the price of this sort of product is set by the volume. For example Avnet offers a Spartan 3A board at $40. It doesn't have all the features that the DE1 does. I am sure the low price is a result of (and a factor in) very high sales volumes relatively speaking. There may be inexpensive add-on cards that would provide the features you need. Or perhaps the add-on card could be a do-it-yourself module based on perf board? The Avnet AES-SP3A-EVAL400- G does not include RAM, but does support parallel and serial Flash. Care to list all of the features you need? RickArticle: 137164
> RealInfo <therighti...@yahoo.com> wrote: > > I have a litle dream to turn a FPGA based design into a real ASIC viasic.com is another low cost metal mask programmable ASIC vendor. Still, take the others advice if you need an FPGA based design cost reduced and shop for other programmable ways to get there first. Then concentrate on your sales methods before worrying about selling 800,000 pieces to the music makers market...hmmm... could anyone sell >800K to musicians? How many musicians are there? Less than kids that buy a guitar-hero toy, I bet. How about programmable analog and digital PSOCs from cypressmicro for guitar effects? Then sell $45 units with a $15 BOM to musicians. JohnArticle: 137165
bknpk@hotmail.com a écrit : > Ever wanted to indent a code that you got from somebody else. I > created some scripts for that, which I would like to share as free > stuff. > Be glad to get comments. emacs VHDL-mode already does that (and much more) for you NicolasArticle: 137166
john_griessen wrote:
> Then
> concentrate on
> your sales methods before worrying about selling 800,000 pieces to the
> music makers
> market...hmmm... could anyone sell >800K to musicians? How many
> musicians are there?
US Labor statistics
http://www.bls.gov/oco/ocos095.htm
says there were
196,000 professional musicians and singers in the US in 2006
Let's guess that 30,000 are guitarists
10,000 use an effects box
May not need that asic.
-- Mike Treseler
Article: 137167Hi, I am new to VHDL. Before someone out there says "just use signal1 xor signal2" I must admit that this problem is related to the signal TYPE and evidently I don't understand a lot about that just yet. Signa1 and signal2 are declared as std_logic_vector (2 downto 0) I wish to xor these signals one bit at a time in an if statement such as: if (signal1(0) xor signal2(0)) then ........ however, this gives a compiler error because xor wishes to return a Boolean and signal1 and signal2 are not of type Boolean. I did try changin the type of Signal1 and Signal2 but that did not get rid of the compiler error. I have tried using the "event" attribute in a form like: if (signal1(0)'event xor signal2(0)'event) then....and this gets rid of the compiler error. But, the function is not working as an xor. Thank you Tom From rgaddi@technologyhighland.com Mon Dec 29 16:12:45 2008 Path: nlpi059.nbdc.sbc.com!flph199.ffdc.sbc.com!prodigy.com!flph200.ffdc.sbc.com!prodigy.net!bigfeed.bellsouth.net!news.bellsouth.net!cyclone1.gnilink.net!gnilink.net!nx02.iad.newshosting.com!newshosting.com!216.196.98.140.MISMATCH!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local02.nntp.dca.giganews.com!nntp.lmi.net!news.lmi.net.POSTED!not-for-mail NNTP-Posting-Date: Mon, 29 Dec 2008 18:12:45 -0600 Date: Mon, 29 Dec 2008 16:12:45 -0800 From: Rob Gaddi <rgaddi@technologyhighland.com> Newsgroups: comp.arch.fpga Subject: Re: How do I xor two signals in VHDL? Message-Id: <20081229161245.31f5ba66.rgaddi@technologyhighland.com> References: <0ZKdnce2IqGM-8TUnZ2dnUVZ_gednZ2d@giganews.com> Organization: Highland Technology, Inc. X-Newsreader: Sylpheed 2.5.0 (GTK+ 2.10.14; i686-pc-mingw32) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Lines: 41 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 66.117.134.49 X-Trace: sv3-w8BWmU04HgdznQO5HOTypGa4IyfMHDSvfGFUhxb2XOA4/em/69g7DUhNS6+J/i6tmDBEb6QZfl1aFV1!zVsw9Wfh3DIiIXSW1aGlPyMZKx3QVzdPMJszgcRdXxOMEyttMXJYaiRkQUfxZQjuyT0+iIq+nhmB!AuEAChHWC76gukqPjPI= X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Bytes: 2479 Xref: prodigy.net comp.arch.fpga:150158 X-Received-Date: Mon, 29 Dec 2008 19:13:46 EST (nlpi059.nbdc.sbc.com) On Mon, 29 Dec 2008 16:06:40 -0800 "Teece" <tom_cip_11551_nospam@hotmail.com> wrote: > Hi, > > I am new to VHDL. Before someone out there says "just use signal1 xor > signal2" I must admit that this problem is related to the signal TYPE > and evidently I don't understand a lot about that just yet. > > Signa1 and signal2 are declared as std_logic_vector (2 downto 0) > > I wish to xor these signals one bit at a time in an if statement such > as: > > if (signal1(0) xor signal2(0)) then > ........ > > however, this gives a compiler error because xor wishes to return a > Boolean and signal1 and signal2 are not of type Boolean. I did try > changin the type of Signal1 and Signal2 but that did not get rid of > the compiler error. > > I have tried using the "event" attribute in a form like: if > (signal1(0)'event xor signal2(0)'event) then....and this gets rid of > the compiler error. But, the function is not working as an xor. > > Thank you > Tom > std_logic values are not directly compatible with boolean true/false values. If statements work only on boolean values. Therefore, what you're looking for should be one of if (signal1(0) /= signal2(0)) then if ( (signal1(0) xor signal2(0)) = '1') then -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 137168
Teece wrote: > I wish to xor these signals one bit at a time in an if statement such as: > > if (signal1(0) xor signal2(0)) then > ........ if (signal1(0) xor signal2(0)) = '1' then Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 137169
rickman wrote:
> I could be mistaken about this if this has been formalized in the last
> few years. The comp.lang.vhdl FAQ still says that there is no formal
> "don't care" meaning.
> http://www.eda.org/comp.lang.vhdl/FAQ1.html#dont_cares
I believe you are correct.
'X' and '-' are just characters as far as standard VHDL knows.
Some synthesis vendors support the K-map fans
but I leave minimization to synthesis.
I prefer identifying the exact input slice
needed in an expression rather than marking the benched players.
My "don't care" output bit is '0' because this is easier to test.
-- Mike Treseler
Article: 137170
wojtek2u@wp.pl wrote:
> Map options ISE 9.2.03 ISE 10.1.03
> Input func. 4 / Balanced 7 3
> Input func. 5 / Balanced 9 2
> Input func. 6 / Balanced 5 3
> Input func. 5 / Speed 3 1
> Input func. 6 / Speed 0 0
>
>
> In ISE10 I only got 38% of ISE9 good results (in other words ISE9 is
> 2.5 times better in this experiment).
Why is constraining input functions on the scoreboard?
Let's see the stats with only Fmax constrained.
-- Mike Treseler
Article: 137171On 28 Dez., 19:28, General Schvantzkoph <schvantzk...@yahoo.com> wrote: > > There are two reasons to build an ASIC, either your volumes are huge (in > the millions) or an FPGA can't come close to handling the problem because > of speed, size or power consumption. Building a state of the art There are other good reasons to use an ASIC. Fpgas tend to force you on several constraints. You can't expect to get an Fpga in very small package (e.gt) less than 100 pins) and lots of resources, because you could get either small package or high performance. You might have an design with small logic and lots of ram which forces you to the high- end fpga, but the design itself could be done on an small and cheap asic, etc. As long as your design is mainstream, you are right with the reasons to change to ASIC. But some designs have constraints that are badly supported from fpga vendors. bye ThomasArticle: 137172
Xilinx QUIZ 2008 system setup * Xilinx Virtex FPGA - DDR2 memory - SFP sockets on MGTs - Gigabit TEMAC with SG DMA 1G fiber module in the SFP, fiber to D-Link media adapter cable to D-link GB switch cable to PC GB ethernet port PC is running only 1 custom application FPGA is sending UDB packets to PC PC sends very little amount of small UDP packets that are responded by FPGA Problem: UDP commands are no longed processed or responded by the FPGA after say 15 minutes after communication start. the time is dependant off the PC and the application running, there it may be sometimes several hours before the communication stops. Yesterday I did think I solved the problem: the RX buffers were not aligned properly so I assumed that could have caused the problem for the SG DMA. But after fixing this, the problem persisted. The PPC is not running wild, neither is there spurios reset coming, the main loop is still working, and the interrupts as well. But the DMA registers after the failure are written with either 0, random or wrong values. I am troubleshooting this system for some time already, had many great ideas what all could have been the cause for the problem, but non of them made any change. Hum... adding single UART char debug symbols made it NOT TO FAIL (or maybe i did not wait long enough) so i removed those debug printouts, to make the problem visible so it can be better seen. I have mini uart debug routine built in so i can type commands to read memory and DCR bus whenever i want while the system is running. So I see the DMA regs being corrupted but that doesnt give much hints how or why? It looks like TX BD address value has been written to RX LEN register, other regs are either 0, or completly random. Any body dare to propose a solution? Yesterday i belived the answer to be: ALIGN but i was wrong. AnttiArticle: 137173
Antti wrote: > Xilinx QUIZ 2008 > > system setup > > * Xilinx Virtex FPGA > - DDR2 memory > - SFP sockets on MGTs > - Gigabit TEMAC with SG DMA > Ok, what I can remember from running in Virtex-4FX issues (information from about one year ago, so maybe that has changed meanwhile) with ethernet: SG-DMA used to be buggy. HardTemac-Version used to be Silicon-Revision dependend (and was not selected properly automatically) Maybe that helps a little. Regards, LorenzArticle: 137174
On Dec 30, 2:11=A0pm, Lorenz Kolb <lorenz.k...@uni-ulm.de> wrote: > Antti wrote: > > Xilinx QUIZ 2008 > > > system setup > > > * Xilinx Virtex FPGA > > - DDR2 memory > > - SFP sockets on MGTs > > - Gigabit TEMAC with SG DMA > > Ok, what I can remember from running in Virtex-4FX issues (information > from about one year ago, so maybe that has changed meanwhile) with ethern= et: > > SG-DMA used to be buggy. > > HardTemac-Version used to be Silicon-Revision dependend (and was not > selected properly automatically) > > Maybe that helps a little. > > Regards, > > Lorenz Thank you, well it not very encouraging :( the system uses LL_TEMAC_SGMII_V1_00a (user modified!) and MPMC2 #define GUI_VERSION 1.9 #define PCORE_VERSION _v2_10_a #define pcorename mpmc2_ddr2_pnncc_200mhz_x16_mt47h16m16_3 I know this is rather old and so on, but currently i have no options to upgrade the complete system to MPMC2 4.x anything you recall about the buggy? what did the buggy behavior cause? I think the hw revision is not an issues as the MGT seems to work ok under all circumstances, just the DMA engine DCR registers get wrong values, and then it all stops Antti
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