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Messages from 136675

Article: 136675
Subject: Re: How to evaluate program efficiency/functionality
From: Mike Treseler <mtreseler@gmail.com>
Date: Sun, 30 Nov 2008 11:03:03 -0800
Links: << >>  << T >>  << A >>
> cid <nihonshuu@gmail.com> wrote 
> 
>> I am fairly new to working with FPGAs, have created only a few
>> projects, and want to know how to determine whether or not your design
>> is any good.
>> Simulation works, on-board program works.

Congratulations.

If you have a synchronous design
with just one clock, and pass Fmax
in static timing, you are done.
If you have more than one clock,
or other asynchronous elements,
you are just getting started.
See Allan's Posting.

>> Besides normal functionality, what should I be focusing on when
>> designing FPGAs?

Updating your own design rules so
that "normal functionality" happens sooner next time

>> 1. Come up with project idea
Consider projects that can be cascaded into larger projects.

>> 2. Work out general functionality
I would make this a plain-english text description
as a comment at the top of the top entity/module.
This describes the device input requirements and
the top output registers.

>> 3. Draw Block Diagram
I sketch these in my notebook.
The computer can draw the final version
from my code.

>> 4. Rework general functionality
I like to start each process with a plain-english
text description that names *all*
the internal registers and explains
how they are updated.

>> 5. Write out Flow Charts for each module
      Clean code *is* the flowchart.

>> 6. Start coding
      ... by checking a header into rcs or svn
      Continue coding until some output of some
      module is complete and
       vcom my_testbench.vhd or
       vlog my_testbench.v
      is error free.

    Simulate7: while (incomplete or bugs) loop
       vsim my_testbench
       If it works better than before, check in the changes.
       Enter any new simulation bugs as temporary comments
       Write code to fix a bug or add an output.
    end loop Simulate7;

>> 8. Program target device
   I would make that, "Run synthesis and check static timing"
   It is not efficient or necessary to test the board every time.

>> 9. Test/Error checking
   I would call this system testing.
   Functional testing is completed in the simulation loop.
   System test on the board covers synthesis constraints
   like pin assignments, and unexpected external requirements.
   Any error found here is translated into a new design rule,

         -- Mike Treseler

Article: 136676
Subject: Re: How to evaluate program efficiency/functionality
From: hal-usenet@ip-64-139-1-69.sjc.megapath.net (Hal Murray)
Date: Sun, 30 Nov 2008 16:29:10 -0600
Links: << >>  << T >>  << A >>

>1. Come up with project idea
>2. Work out general functionality

Somewhere about here you have to figure out how you are going
to decide if it works.  It often helps to keep that in mind
when going through the rest of the steps.

>3. Draw Block Diagram (identify clock domain crossings)
>4. Rework general functionality (identify entities/modules)
>5. Write out Flow Charts for each module
>6. Start coding individual modules
>7. Simulate individual modules
>8. Code "top-level" module
>9. Simulate "top-level" module
>10. Program target device
>11. Test/Error checking (on-board)


-- 
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 136677
Subject: Re: FMC/VITA 57
From: palvarez <pabloalvarezsanchez@gmail.com>
Date: Sun, 30 Nov 2008 15:19:03 -0800 (PST)
Links: << >>  << T >>  << A >>
On Nov 28, 7:57=A0pm, Mike Monett <N...@here.adr> wrote:
> =A0 palvarez <pabloalvarezsanc...@gmail.com> wrote:
>
> =A0 > Hi,
>
> =A0 > In =A0 =A0 =A0 principle =A0 =A0 on =A0 =A0 can =A0 =A0 get =A0 =A0=
 the =A0 =A0 specs =A0 from
> =A0 >http://www.vita.com/fmc.html. I =A0have =A0also tried to =A0get =A0i=
t this
> =A0 > week but there is an unusual delay.
>
> =A0 > Cheers
>
> =A0 > pablo
>
> =A0 pablo,
>
> =A0 I searched =A0the =A0site =A0but couldn't find =A0anywhere =A0to =A0d=
ownload the
> =A0 specs. Do you have to join to get their open standard?

Hi,

Have you tried here?
https://www.vita.com/online-store.html

pablo


Article: 136678
Subject: Re: make phone calls from fpga. is it possible?
From: Karl <karl.polytech@googlemail.com>
Date: Sun, 30 Nov 2008 16:54:05 -0800 (PST)
Links: << >>  << T >>  << A >>
On 30 Nov, 15:36, "tim....." <tims_new_h...@yahoo.co.uk> wrote:
> "Karl" <karl.polyt...@googlemail.com> wrote in message
>
> news:f8493c3f-0629-472a-8ff4-1e7551887a7b@f20g2000yqg.googlegroups.com...
>
> > Hi,
> > Is it possible to build a unit on fpga where alerting pre-recorded
> > messages: sms, voice messages can be sent =A0using possibly the ambiant
> > wireless network? if yes, how? i am not looking for the hardware
> > architecture, i can work this on my own. i am rather looking for the
> > means to achieve this: what kind of theory =A0in the context of
> > communication and broadcating in general i should read about to
> > achieve this goal and how to be able to use the ambiant wireless
> > ( landline?) network to send these messages. any papers/books titles
> > will be greatly appreciated
>
> Do you mean "will someone supply me with the design for a GSM modem in a
> form that I can load into an FPGA".
>
> Noting that if they did, this item would allow the purchasor to reverse
> engineer the design into an ASIC, I very much doubt it.
>
> tim

I mentioned FPGA because the rest of my architectures will have to be
implemented on FPGA. From what i understand, i have to associate an
asic to my fpga. could you please suggest any available chip


Article: 136679
Subject: Re: make phone calls from fpga. is it possible?
From: Karl <karl.polytech@googlemail.com>
Date: Sun, 30 Nov 2008 16:56:20 -0800 (PST)
Links: << >>  << T >>  << A >>
On 30 Nov, 15:36, "tim....." <tims_new_h...@yahoo.co.uk> wrote:
> "Karl" <karl.polyt...@googlemail.com> wrote in message
>
> news:f8493c3f-0629-472a-8ff4-1e7551887a7b@f20g2000yqg.googlegroups.com...
>
> > Hi,
> > Is it possible to build a unit on fpga where alerting pre-recorded
> > messages: sms, voice messages can be sent =A0using possibly the ambiant
> > wireless network? if yes, how? i am not looking for the hardware
> > architecture, i can work this on my own. i am rather looking for the
> > means to achieve this: what kind of theory =A0in the context of
> > communication and broadcating in general i should read about to
> > achieve this goal and how to be able to use the ambiant wireless
> > ( landline?) network to send these messages. any papers/books titles
> > will be greatly appreciated
>
> Do you mean "will someone supply me with the design for a GSM modem in a
> form that I can load into an FPGA".
>
> Noting that if they did, this item would allow the purchasor to reverse
> engineer the design into an ASIC, I very much doubt it.
>
> tim


I mentioned FPGA because the rest of my architecture has to be
implemented on FPGA. i gather from my message i need to use an
exisiting asic chip. could you please suggest one which allows me to
set the prerecorded message and the callee phone number. cheers

Article: 136680
Subject: Re: make phone calls from fpga. is it possible?
From: "H. Peter Anvin" <hpa@zytor.com>
Date: Sun, 30 Nov 2008 17:21:23 -0800
Links: << >>  << T >>  << A >>
Karl wrote:
> I mentioned FPGA because the rest of my architecture has to be
> implemented on FPGA. i gather from my message i need to use an
> exisiting asic chip. could you please suggest one which allows me to
> set the prerecorded message and the callee phone number. cheers

I suggest you Google for "GSM module".

	-hpa

Article: 136681
Subject: Re: DDR2 SDRAM RELEATED PROBLEM IN SPARTAN 3A DSP 1800 + EDK 9.2i
From: bish <bisheshkh@gmail.com>
Date: Sun, 30 Nov 2008 19:33:27 -0800 (PST)
Links: << >>  << T >>  << A >>
On Nov 30, 11:28=A0pm, SUMAN <suman...@gmail.com> wrote:
> Hi,
> =A0I am student using spartan 3a dsp 1800 board with EDK/ise 9.2i . In
> EDK I had used BSB to create new project using default configuration
> for the following peripherals:-
> 1) microblaze (with bram 64KB) ,clock
> 2)RST32_UART
> 3)LED ,PUSH, DIP.
> 4)DDR2 SDRAM using MPMC peripheral
>
> I had used all default settings to the end of bsb.
>
> When i downloaded bitseam in the board , i got MEMORY TEST FAILURE
> (for 32 ,16 and 8 bit) message in hyperterminal .
>
I doubt that xilinx and avnet people ever tested the spartan 3a dsp
1800a board with edk 9.2i. As they provide the edk 9.2i with this
board they shoud have tested the board building reference systems WITH
EDK 9.2i. It seems they didn't do that and people like us get a lot of
trouble and lot of time wasted unnecessarily!!

> But other peripherals are working fine.
> I can't understand what the problem is. Does any body has solution?


Article: 136682
Subject: simulation results is correct but synthesis result is not correct
From: "J.Ram" <jrgodara@gmail.com>
Date: Sun, 30 Nov 2008 20:45:04 -0800 (PST)
Links: << >>  << T >>  << A >>
Hello,
I have a problem in peice of code.
for simulation i used modelsim , and for synthesis synplify pro was
used.
when i do simulation with this code my functionality is achieved, but
during synthesis
one port (clk) is unconnected , when i saw result in RTL view.

code is shown below
entity pn_clk is
port(
clk: in std_logic;
ref_clk : in std_logic;
reset : in std_log;
out_clk : in std_logic)

architecture behav of pn_clk is
signal sig_count : natural range 0 to 8 := 0;
 begin
u1: process(clk, reset, ref_clk)
variable count : natural range 0 to 8 := 0;
begin
if reset = '1' or ref_clk = '1' then
count := 0;
end if;
if reset = '1' then
count := 0;
elsif rising_edge(clk) then
if count = 8 then
count := 0;
else
count := count + 1;
end if;
end if;
sig_count <= count;
end process u1;
u2: process(sig_count)
variable clk_var : std_logic := '0';
begin
if sig_count >= 4 or sig_count >5 then
clk_var := 0;
else
clk_var := 1:
end if;
clk_out <= clk_var;
end process u2;
end behav;

Article: 136683
Subject: Re: Deserializing Camerlink on Spartan XC3s400
From: reganireland@gmail.com
Date: Sun, 30 Nov 2008 21:48:51 -0800 (PST)
Links: << >>  << T >>  << A >>
I got the Xilinx XAPP485 and it seemed very thorough, made the entire
task truly trivial, even took into account PCB jitter and worked out
exact clock rates. Haven't had chance to try it on hardware but will
post when I do. Geez some of those built-in Xilinx designs and IPs are
impressive!

Cheers guys,
Gints

Article: 136684
Subject: Re: Problem with post-route simulation / timing simulation
From: "ikki" <jasperng10@gmail.com>
Date: Sun, 30 Nov 2008 23:49:56 -0600
Links: << >>  << T >>  << A >>
>On 2008-11-27, ikki <jasperng10@gmail.com> wrote:
>> Hi there, I tried to run my design using modelsim through Xilinx ISE,
>> However it seems i keep encountering this problem. Can anyone know
what
>> isthe problem and how to fix this ? ... It seems to be missing a
library
>> named simprim. But I have no idea how to get the library and implement
it ?
>> ..
>
>You will need to compile the Xilinx simulation libraries. You can
compile
>this library using the compxlib command. (You can also click somewhere
in
>ISE to compile it but I don't remember exactly where right now, I
usually
>don't use the GUI any longer.)
>
>/Andreas
>

where do i type in the compxlib command?



Article: 136685
Subject: Re: Problem with post-route simulation / timing simulation
From: "ikki" <jasperng10@gmail.com>
Date: Sun, 30 Nov 2008 23:51:57 -0600
Links: << >>  << T >>  << A >>
>ikki wrote:
>> # ** Error: C:/FPGAdv71LSPS/Modeltech/win32/vcom failed.
>
>
>Click up a shell, bash or cmd.exe
>
>mkdir play
>cd play
>vcom
>
>If this doesn't give you the vcom usage,
>type "exit" to close the shell,
>find vcom, and add it's location
>to your path and try again.
>
>        -- Mike Treseler
>

what do you mean by shell,bash or cmd.exe ? ... where do i get those ? 
how do i type in command ? in MOdelsim ?

Article: 136686
Subject: what is the difference between post-synthesis simulation and timing simulation?
From: "ikki" <jasperng10@gmail.com>
Date: Mon, 01 Dec 2008 00:02:10 -0600
Links: << >>  << T >>  << A >>

As the title shown, 

what isthe difference between post-synthesis simulation and timing
simulation ? and what are the method to be used for each of the simulation
? 

Does post-synthesis simulation requires SDF file as timing simulation
needs ?

Thanks


Article: 136687
Subject: Re: what is the difference between post-synthesis simulation and
From: Thomas Stanka <usenet_nospam_valid@stanka-web.de>
Date: Sun, 30 Nov 2008 22:50:04 -0800 (PST)
Links: << >>  << T >>  << A >>
On 1 Dez., 07:02, "ikki" <jaspern...@gmail.com> wrote:
> what isthe difference between post-synthesis simulation and timing
> simulation ? and what are the method to be used for each of the simulation
> ?

Post-synthesis is the simulation performed after synthesis.

Timing simualtion is a simulation using timing information.
This can be done in rtl using after clause for example or in
behavioral using wait statements. The term timing simulation is in
99.9% used for the simulation of the netlist using sdf-files.

> Does post-synthesis simulation requires SDF file as timing simulation
> needs ?

No, it is possible (and especially for large designs reasonable) to
perfom a simulation of the netlist without sdf or other timing
information.

When you do an ASIC, you have no good timing information between
synthesis and layout step. Therefor it is acceptable to verify the
outcome of the synthesis by simulations without sdf for some designs
(and designflows, you should know the technology and tools a bit).

After layout you can still simulate without timing if you trust your
STA. This will speed up your simulation.
I prefer doing netlist without sdf as a first step and with sdf as
second step.

bye Thomas


Article: 136688
Subject: Re: How to write driver for xilinx spartan iie xc2s50e
From: berte <b3hzat@gmail.com>
Date: Sun, 30 Nov 2008 23:07:46 -0800 (PST)
Links: << >>  << T >>  << A >>
Hello Mike,

This chipset using by dvb-s pci digital tv card.

I investigated this case in linuxtv mail list but I do not get any
solution.

Thanks for reply.

Regards.


On 29 Kas=FDm, 21:10, Mike Treseler <mtrese...@gmail.com> wrote:
> berte wrote:
> > I am a newbie for fpga devices so I want to write driver for xilinx
> > spartan iie xc2s50e chipset.
>
> This is not possible because the xc2s50e is a blank slate.
> There are no registers for an OS to talk to until
> somebody defines the operation and writes, tests and
> compiles some hdl code to implement it.
>
> > How to start for this case ?
>
> Think about what this driver would do
> if it were already working.
>
> =A0 =A0 =A0-- Mike Treseler


Article: 136689
Subject: Re: simulation results is correct but synthesis result is not correct
From: Thomas Stanka <usenet_nospam_valid@stanka-web.de>
Date: Sun, 30 Nov 2008 23:15:02 -0800 (PST)
Links: << >>  << T >>  << A >>
On 1 Dez., 05:45, "J.Ram" <jrgod...@gmail.com> wrote:
> Hello,
> I have a problem in peice of code.

I see that you have a problem, but is more than just a piece.
Simulation accepts software, synthesis expects hardware description.
in vhdl you use for registered data transfer always a template in the
form

process (clk)
  if rising_edge(Clk) then
      <synchron change regs>
  end if

or for asynchronous reset:

process(clk,reset)
  if reset = active then
    <reset regs asynchronous>
  elsif rising_edge(Clk) then
    <synchron update regs>
  end if

Your first process does something you propably wouldn't expect, when
having a rising edge on clk, while reset=0 and ref_clk=1 This behavior
is not synthesisable for most tools and need to be rewritten if
needed.

Three questions:
1. Why do you name a process, if you don't like to name it properly?
   (eg. change u1 to registered_counter)
2. Why do you write redundant code?
       a) if reset = 1 or..then...end if; if reset = 1 then...
       b) if sig_count >= 4 or sig_count >5 then
3. Is there a reason to use the variables? Variables are good practice
for most code but I see no reason in this particular code.

bye Thomas

Article: 136690
Subject: Re: simulation results is correct but synthesis result is not correct
From: KJ <kkjennings@sbcglobal.net>
Date: Mon, 1 Dec 2008 05:31:16 -0800 (PST)
Links: << >>  << T >>  << A >>
On Nov 30, 11:45=A0pm, "J.Ram" <jrgod...@gmail.com> wrote:
> Hello,
> I have a problem in peice of code.
> for simulation i used modelsim , and for synthesis synplify pro was
> used.
> when i do simulation with this code my functionality is achieved, but
> during synthesis
> one port (clk) is unconnected , when i saw result in RTL view.
>

Your posted code is riddled with typos and errors, it never made it
through a successful compile with Modelsim or Synplify let alone
actually simulating correctly.  Clean up the code first, then run it
through and Modelsim and Synplify and then peruse any warnings that
Synplify might have and fix any issues that it may have and then come
back here and try again.  Below are just some of the errors:

> reset : in std_log;
std_log...when std_logic won't work, I guess std_log will

> out_clk : in std_logic)

Will get back to 'out_clk' again later, but also note the lack of a
semicolon and the required 'end pn_clk;' statement to end the entity.

Given this declaration for clk_var...
> variable clk_var : std_logic :=3D '0';

Spot the errors in the following two assignments...
> clk_var :=3D 0;
> clk_var :=3D 1:

I guess you think 'clk_out' and 'out_clk' are the same thing or
something....no compiler will though.
> clk_out <=3D clk_var;

Kevin Jennings

Article: 136691
Subject: using memory of spartan 3sd1800a dsp fpga
From: denish <dinesh.twanabasu@gmail.com>
Date: Mon, 1 Dec 2008 07:34:28 -0800 (PST)
Links: << >>  << T >>  << A >>
we are using spartan 3sd1800a dsp fpga, and we need to store 0.1 mega
byte of image data to memory so that further processing can be done.
what are the options to store the image data and how we can access the
part of sd ram from custom designed modules.

Article: 136692
Subject: Re: DDR2 SDRAM RELEATED PROBLEM IN SPARTAN 3A DSP 1800 + EDK 9.2i
From: Bryan <bryan.fletcher@avnet.com>
Date: Mon, 1 Dec 2008 09:07:22 -0800 (PST)
Links: << >>  << T >>  << A >>
The 1800A board's DDR2 was tested extensively by both Avnet and Xilinx
in ISE/EDK 9.2.

Xilinx is running Linux from the DDR2 in example design
http://www.xilinx.com/support/documentation/boards_and_kits/ug486.pdf.
This design is currently at 10.1, but I believe it was originally
posted for ISE/EDK 9.2.

You can also go to the Avnet Design Resource Center for some extra
designs for this board:  www.em.avnet.com/spartan3a-dsp.  Click on
Support Files & Downloads.  Both MIG and MicroBlaze designs that use
the DDR2 are posted for ISE/EDK 9.2.  For MicroBlaze, the S3A1800DSP
BPI Flash Configuration and Bootloading design specifically has a DDR2
memory test.

Regarding your issues, SUMAN, have you installed the service packs for
both ISE and EDK?

Bryan


On Nov 30, 8:33=A0pm, bish <bishes...@gmail.com> wrote:
> On Nov 30, 11:28=A0pm, SUMAN <suman...@gmail.com> wrote:> Hi,
> > =A0I am student using spartan 3a dsp 1800 board with EDK/ise 9.2i . In
> > EDK I had used BSB to create new project using default configuration
> > for the following peripherals:-
> > 1) microblaze (with bram 64KB) ,clock
> > 2)RST32_UART
> > 3)LED ,PUSH, DIP.
> > 4)DDR2 SDRAM using MPMC peripheral
>
> > I had used all default settings to the end of bsb.
>
> > When i downloaded bitseam in the board , i got MEMORY TEST FAILURE
> > (for 32 ,16 and 8 bit) message in hyperterminal .
>
> I doubt that xilinx and avnet people ever tested the spartan 3a dsp
> 1800a board with edk 9.2i. As they provide the edk 9.2i with this
> board they shoud have tested the board building reference systems WITH
> EDK 9.2i. It seems they didn't do that and people like us get a lot of
> trouble and lot of time wasted unnecessarily!!
>
>
>
> > But other peripherals are working fine.
> > I can't understand what the problem is. Does any body has solution?- Hi=
de quoted text -
>
> - Show quoted text -


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From: Rob Gaddi <rgaddi@technologyhighland.com>
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Subject: Re: Infer Dual Port Block ROM for Xilinx FPGA
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On Wed, 26 Nov 2008 17:47:20 -0800 (PST)
Sudhir.Singh@email.com wrote:

> Hi Guys,
> I am trying to figure out a way to infer dual port ROM using BRAM on
> Xilinx FPGAs. Documentation shows how to infer single port ROMs but
> couldn't find any info on dual port.
> Any info on this will be greatly appreciaied.
> 
> Cheers
> Sudhir

While you can certainly infer DP RAMs (several other posters have given
good documentation links on it), my experience has been that for the
most part XST forces you to tie your code into such knots in order for
it to recognize and infer a dual-port that you're better off just
calling it out directly.

-- 
Rob Gaddi, Highland Technology
Email address is currently out of order

Article: 136693
Subject: Re: DDR2 SDRAM RELEATED PROBLEM IN SPARTAN 3A DSP 1800 + EDK 9.2i
From: SUMAN <sumansrb@gmail.com>
Date: Mon, 1 Dec 2008 09:56:49 -0800 (PST)
Links: << >>  << T >>  << A >>

No , I have not. I am planning to install them.






Article: 136694
Subject: Re: Terasic DE1 board commentary
From: Tommy Thorn <tommy.thorn@gmail.com>
Date: Mon, 1 Dec 2008 11:43:04 -0800 (PST)
Links: << >>  << T >>  << A >>
Try writing directly to TeraSic (either sales or support). I have
gotten good responses from them.

My perpetual request:

4. More Memory Please. You can never have too much, too fast, or too
wide memory.

Tommy




On Nov 30, 2:18=A0am, "H. Peter Anvin" <h...@zytor.com> wrote:
> Hello,
>
> I am in the process of porting a project of mine from the Cyclone Nios
> Development Kit to the Terasic DE1 board. =A0The main reason for this is
> to be able to run on less expensive hardware and thus make the project
> available to more people (hence "get a better board" is not really an
> easy answer.) =A0My interest is mostly in computing projects, so my views
> are certainly biased in that direction.
>
> Unfortunately, I have run into a few issues with the DE1 board. =A0I
> thought I'd post them here (and please let me know if there is a better
> place to send this) in the hope that a future board (Cyclone III-based,
> maybe?) might address these. =A0Please don't get me wrong - this is a
> great board at a great price; I think, however, that a few things would
> make it even better.
>
> 1. The SD card slot only connects a handful of signals. =A0In particular,
> it does not connect the two switch pins on the socket (card detect and
> write protect.) =A0This makes it much harder than it needs to be to handl=
e
> card removal and insertion.
>
> 2. Similarly, the serial port doesn't connect more than the transmit and
> receive signals, even though there is a 2/2 transceiver on the board.
> Having at least DTR/DCD or RTS/CTS would have been a plus; a "real"
> serial port with 3/5 signals would of course be even better.
>
> 3. While I'm dreaming, I would *love* to see a USB-A or -AB connector
> and/or an Ethernet PHY (not a fullblown Ethernet controller) connected
> to the FPGA.
>
> That would make the DE1 a dream board in my book.
>
> =A0 =A0 =A0 =A0 -hpa


Article: 136695
Subject: Re: simulation results is correct but synthesis result is not correct
From: Nicolas Matringe <nicolas.matringe@fre.fre>
Date: Mon, 01 Dec 2008 22:00:51 +0100
Links: << >>  << T >>  << A >>
J.Ram a écrit :
> Hello,
> I have a problem in peice of code.
> for simulation i used modelsim , and for synthesis synplify pro was
> used.
> when i do simulation with this code my functionality is achieved, but
> during synthesis
> one port (clk) is unconnected , when i saw result in RTL view.
> 
> code is shown below
> entity pn_clk is
> port(
> clk: in std_logic;
> ref_clk : in std_logic;
> reset : in std_log;
> out_clk : in std_logic)

Hi
Where are your outputs ?
Any synthesizer will reduce this to... absolutely nothing.

Nicolas

Article: 136696
Subject: Use Chipscope libCseJtag.dll
From: John <isuvalov@gmail.com>
Date: Mon, 1 Dec 2008 23:23:31 -0800 (PST)
Links: << >>  << T >>  << A >>
Hello!

 I am try to use TCL with libCseJtag.dll from Xilinx chipscope. I try
set pins like TCK, TDI, TMS by script.
 Like it descibe at ug029.pdf:
   For example clock I can run in the loop:
    csejtag_target set_pin $handle $CSEJTAG_TCK 0
    csejtag_target set_pin $handle $CSEJTAG_TCK 1

 Script work, not get any error. Chaining correctly done and all good,
BUT!  TCK, TDI, TMS by this commands not set!
 Any body try to do this?

Best Regards,
Ivan

Article: 136697
Subject: reading registers
From: uraniumore238@gmail.com
Date: Tue, 2 Dec 2008 00:48:18 -0800 (PST)
Links: << >>  << T >>  << A >>
Hi guys,

I have a spartan 3 starter board from digilent. I using a 2 counter
and then subtracting the two registers and then displaying these
values on the led screen from lsb to msb (right to left). What kind of
representation (signed magnitude, two's complement, ones complement)
is my system displaying the binary value ? I am really confused on
which technique to use in order to convert it into an integer
value ...

Thanks,

Article: 136698
Subject: Re: using memory of spartan 3sd1800a dsp fpga
From: ales.gorkic@gmail.com
Date: Tue, 2 Dec 2008 01:43:19 -0800 (PST)
Links: << >>  << T >>  << A >>
On Dec 1, 4:34=A0pm, denish <dinesh.twanab...@gmail.com> wrote:
> we are using spartan 3sd1800a dsp fpga, and we need to store 0.1 mega
> byte of image data to memory so that further processing can be done.
> what are the options to store the image data and how we can access the
> part of sd ram from custom designed modules.

Use EDK and Base System Builder. The MPMC memory controller can have a
VFBC (video frame buffer) port. Use it!
The other option is ISE and MIG (Memory Interface Generator), but
harder to understand and evolve.

Cheers,

Ales

Article: 136699
Subject: Re: reading registers
From: Per <per@anon.se>
Date: Tue, 2 Dec 2008 10:22:08 +0000 (UTC)
Links: << >>  << T >>  << A >>
On 2008-12-02, Sean Durkin <news_MONTH@tuxroot.de> wrote:
> uraniumore238@gmail.com wrote:
>> Hi guys,
>> 
>> I have a spartan 3 starter board from digilent. I using a 2 counter
>> and then subtracting the two registers and then displaying these
>> values on the led screen from lsb to msb (right to left). What kind of
>> representation (signed magnitude, two's complement, ones complement)
>> is my system displaying the binary value ? I am really confused on
>> which technique to use in order to convert it into an integer
>> value ...
>
> I'm not sure I understand exactly what you're doing. Only one idea that
> might help: usually on this kind of board LEDs are connected so they
> light when the IO is set to low. So a lit LED means '0', and '1' turns
> it off. Maybe that's all there is to your problem...
>
> HTH,
> Sean
>

  Hi!  To me it seams like you are confused about how all these
  representations corresponds to numbers. A two complement number is
  just two complement because you decide it to be. From the hardware
  perspective there is no difference when adding or
  subtracting. Although subtracting usually requires you to interpret
  the numbers as two's complement numbers.

  1101 + 0110 = 0011 with carry set to 1.
  The question is how you interpret the result
  (-3) + (6)  = 3   or (this only works due to truncation of the number)
  (13)  + (6)  = 19 (with carry) or 3 (truncated to four bits, overflow) 

  Subtraction is usually done with an adder as: a-b = a+(-b)
  
  its all about how you interpret it. The FPGA just deals with bits,
  its your task to decide what the bits mean.

  I don't know if this is what you are after, it although sounds as
  you are confused about binary number representation.

  /Per



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