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Not sure what the problem is with your code. Here's an example with
one timer. It's 10.1, but there weren't any changes in the interrupt
stuff between 9.2 and 10.1 (so I'm told). This is based on a lab from
one of Avnet's Speedway trainings. I ran it on the Xilinx Spartan-3A
DSP 1800A Starter and verified that the interrupts are indeed
happening. There is a bit file in the project directory if you don't
want to rebuild the project.
Bryan
The following file has been made available for you to download from
Avnet's File Transfer web site:
http://xfer.avnet.com/uploads/Xil3S1800ADSP_Interrupt_v10.1.03.zip
Click on the hyperlink or enter this URL into your web browser to
retrieve the file.
This file will remain on the server for approximately 5 days from the
date of the upload at which time it will be deleted. Please be sure
to download it before the expiration time.
This file will expire on Dec 1, 2008.
File Size: 232357 Bytes
On Nov 26, 12:22=A0am, bish <bishes...@gmail.com> wrote:
> On Nov 26, 4:58=A0am, David <simianfe...@gmail.com> wrote:
>
>
>
>
>
> > On Nov 26, 2:37=A0am, bish <bishes...@gmail.com> wrote:
>
> > > On Nov 25, 12:25=A0pm, Matthias Alles <REMOVEallesCAPIT...@NOeit.SPAM=
uni-
>
> > > kl.de> wrote:
> > > > Hi!
>
> > > > I wonder, whether "one_second_flag" is declared as volatile? If not=
, the
> > > > compiler optimizes your if-statement in the while(1) loop away. You=
can
> > > > check this by using mb-objdump.
>
> > > I tried using the volatile for one_second_flag, still it does not
> > > work. It just prints "the value of count =3D 1" once in terminal and
> > > nothing happens then.
>
> > > > Cheers,
> > > > Matthias
>
> > > > bish schrieb:
>
> > > > > I am trying to use a timer for regular interrupt in microblaze. I=
am
> > > > > using edk 9.2i and spartan 3a dsp 1800a.
> > > > > Even following a simple lab example widely used by beginners didn=
't
> > > > > work:http://users.utcluj.ro/~baruch/ssce/labor/EDK-L5-e.pdf
>
> > > > > I have connected all the interrupt ports correctly as evident fro=
m the
> > > > > following portion of the mhs file:
> > > > > BEGIN microblaze
> > > > > =A0PARAMETER HW_VER =3D 7.00.a
> > > > > ...........
> > > > > ...........
> > > > > PORT INTERRUPT =3D interrupt
> > > > > END
>
> > > > > BEGIN xps_timer
> > > > > =A0PARAMETER INSTANCE =3D delay
> > > > > =A0PARAMETER HW_VER =3D 1.00.a
> > > > > =A0PARAMETER C_ONE_TIMER_ONLY =3D 1
> > > > > =A0PARAMETER C_BASEADDR =3D 0x8141c200
> > > > > =A0PARAMETER C_HIGHADDR =3D 0x8141c3ff
> > > > > =A0BUS_INTERFACE SPLB =3D mb_plb
> > > > > =A0PORT Interrupt =3D timer1
> > > > > =A0PORT CaptureTrig0 =3D net_gnd
> > > > > END
>
> > > > > BEGIN xps_intc
> > > > > =A0PARAMETER INSTANCE =3D xps_intc_0
> > > > > =A0PARAMETER HW_VER =3D 1.00.a
> > > > > =A0PARAMETER C_BASEADDR =3D 0x81418000
> > > > > =A0PARAMETER C_HIGHADDR =3D 0x814181ff
> > > > > =A0BUS_INTERFACE SPLB =3D mb_plb
> > > > > =A0PORT Irq =3D interrupt
> > > > > =A0PORT Intr =3D timer1
> > > > > END
>
> > > > > Now for the software settings since I am using edk 9.2i, it does =
not
> > > > > have option for registering our interrupt handler in software pla=
tform
> > > > > settings window (which is what the lab suggests), I used the
> > > > > microblaze_register_handler(...) function ( I took me 3 days to f=
igure
> > > > > out this), =A0but I still don't get how it works differently from=
the
> > > > > function XIntc_RegisterHandler.
> > > > > The portion of C file is as follows:
> > > > > void timer_int_handler(void * baseaddr_p) {
> > > > > =A0 =A0 /* Add variable declarations here */
> > > > > =A0 =A0unsigned int csr;
> > > > > =A0 =A0/* Read timer 0 CSR to see if it raised the interrupt */
> > > > > =A0 =A0csr =3D XTmrCtr_mGetControlStatusReg(XPAR_DELAY_BASEADDR,0=
);
> > > > > =A0 =A0/* If the interrupt occurred, then increment a counter */
> > > > > =A0 =A0/* and set one_second_flag to 1 */
> > > > > =A0 =A0if (csr & XTC_CSR_INT_OCCURED_MASK ) {
> > > > > =A0 =A0 =A0 =A0 =A0 =A0count ++;
> > > > > =A0 =A0 =A0 =A0 =A0 =A0one_second_flag =3D 1;
> > > > > =A0 =A0}
>
> > > > > =A0 =A0/* Display the count on the LEDs */
> > > > > =A0 =A0XGpio_mSetDataReg(XPAR_LED_HIGHADDR, LEDChan, count);
>
> > > > > =A0 =A0/* Print the count using the UART*/
> > > > > =A0 =A0xil_printf("count value is: %x\n\r", count);
> > > > > =A0 =A0/* Clear the timer interrupt */
> > > > > =A0 =A0XTmrCtr_mSetControlStatusReg(XPAR_DELAY_BASEADDR,0,csr);
> > > > > }
>
> > > > > int main() {
>
> > > > > =A0 int count_mod_3;
>
> > > > > =A0 //registering an interrupt handler
> > > > > =A0 microblaze_register_handler((XInterruptHandler) timer_int_han=
dler,
> > > > > (void *)0);
>
> > > > > =A0 /* Register the Timer interrupt handler in the vector table *=
/
> > > > > =A0 XIntc_RegisterHandler(XPAR_XPS_INTC_0_BASEADDR,
> > > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0XPAR_X=
PS_INTC_0_DELAY_INTERRUPT_INTR,
> > > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0(XInte=
rruptHandler) timer_int_handler,
> > > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0(void =
*)XPAR_DELAY_BASEADDR);
> > > > > =A0 /* Enable MicroBlaze Interrupts */
> > > > > =A0 microblaze_enable_interrupts();
>
> > > > > =A0 /* Initialize and set the direction of the GPIO connected to =
LEDs */
> > > > > =A0 XGpio_Initialize(&gpio, XPAR_LED_DEVICE_ID);
> > > > > =A0 XGpio_SetDataDirection(&gpio,LEDChan, 0);
>
> > > > > =A0 /* Start the interrupt controller */
> > > > > =A0 XIntc_mMasterEnable(XPAR_XPS_INTC_0_BASEADDR);
> > > > > =A0 XIntc_mEnableIntr(XPAR_XPS_INTC_0_BASEADDR, 0x1);
>
> > > > > =A0 /* Set the gpio as output on high 8 bits (LEDs)*/
> > > > > =A0 XGpio_mSetDataReg(XPAR_LED_DEVICE_ID,LEDChan, ~count);
> > > > > =A0 xil_printf("The value of count =3D %d\n\r", count);
>
> > > > > =A0 /* Set the number of cycles the timer counts before interrupt=
ing */
> > > > > =A0 XTmrCtr_mSetLoadReg(XPAR_DELAY_BASEADDR, 0,
> > > > > (timer_count*timer_count) * 50000000);
>
> > > > > =A0 /* Reset the timers, and clear interrupts */
> > > > > =A0 XTmrCtr_mSetControlStatusReg(XPAR_DELAY_BASEADDR, 0,
> > > > > XTC_CSR_INT_OCCURED_MASK | XTC_CSR_LOAD_MASK );
>
> > > > > =A0 /* Enable timer interrupts in the interrupt controller */
> > > > > =A0 XIntc_mEnableIntr(XPAR_DELAY_BASEADDR, XPAR_DELAY_INTERRUPT_M=
ASK);
>
> > > > > =A0 /* Start the timers */
> > > > > =A0 XTmrCtr_mSetControlStatusReg(XPAR_DELAY_BASEADDR, 0,
> > > > > XTC_CSR_ENABLE_TMR_MASK | XTC_CSR_ENABLE_INT_MASK |
> > > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK);
>
> > > > > =A0 /* Wait for interrupts to occur */
> > > > > =A0 while(1) {
> > > > > =A0 =A0if(one_second_flag){
> > > > > =A0 =A0 =A0 =A0 =A0 =A0count_mod_3 =3D count % 3;
> > > > > =A0 =A0 =A0 =A0 =A0 =A0if(count_mod_3 =3D=3D 0)
> > > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0xil_printf("Interrupt take=
n at %d seconds \n\r",count);
> > > > > =A0 =A0 =A0 =A0 =A0 =A0one_second_flag=3D0;
> > > > > =A0 =A0 =A0 =A0 =A0 =A0xil_printf(".");
> > > > > =A0 =A0 =A0 =A0 =A0 =A0}
> > > > > =A0 =A0}
> > > > > }
>
> > > > > When I run the system, the value of count does not change from 1.=
What
> > > > > could be the problem?- Hide quoted text -
>
> > > > - Show quoted text -
>
> > Hello,
>
> > Here is how I set up a timer interrupt in 9.2:
>
> > void TimerCounterHandler(void *CallBackRef)
> > {
> > =A0 =A0 =A0 =A0 print("timer interrupt ");
>
> > }
>
> > Int main (void) {
>
> > =A0 =A0 =A0 =A0 XIntc intr_ctrl;
> > =A0 =A0 =A0 =A0 XTmrCtr timr;
>
> > =A0 =A0 =A0 =A0 XIntc_Initialize(&intr_ctrl,XPAR_XPS_INTC_0_DEVICE_ID);
> > =A0 =A0 =A0 =A0 XTmrCtr_Initialize(&timr,XPAR_XPS_TIMER_1_DEVICE_ID);
>
> > =A0 =A0 =A0 =A0 XIntc_Connect(&intr_ctrl, XPAR_XPS_INTC_0_XPS_TIMER_1_I=
NTERRUPT_INTR,
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0(XInterruptHandl=
er)
> > XTmrCtr_InterruptHandler,
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0(void *)&timr);
>
> > =A0 =A0 =A0 =A0 XIntc_Start(&intr_ctrl, XIN_REAL_MODE);
>
> > =A0 =A0 =A0 =A0 XIntc_Enable(&intr_ctrl, XPAR_XPS_INTC_0_XPS_TIMER_1_IN=
TERRUPT_INTR);
>
> > =A0 =A0 =A0 =A0 XTmrCtr_SetHandler(&timr, (void *)TimerCounterHandler, =
void);
>
> This issued an error so I replaced void with NULL in the third
> argument above. Apart from that I didn't change anything, but still
> the terminal never printed "timer interrupt" so still the problem
> remains!!
>
>
>
>
>
> > =A0 =A0 =A0 =A0 XTmrCtr_SetOptions(&timr, 0,
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0XTC_INT_MODE_OPTION | XT=
C_AUTO_RELOAD_OPTION);
>
> > =A0 =A0 =A0 =A0 XTmrCtr_SetResetValue(&timr, 0, 0xF0000000);
>
> > =A0 =A0 =A0 =A0 XTmrCtr_Start(&timr,0);
>
> > =A0 =A0 =A0 =A0 microblaze_enable_interrupts();
>
> > =A0 =A0 =A0 =A0while(1){
> > =A0 =A0 =A0 //wait for interrupts
> > =A0 =A0 =A0 }
>
> > }
>
> > If you are using the Intc component, you no longer need to use the
> > microblaze_register_handler function - instead use the XIntc_Connect()
> > function.
> > The XTmrCtr driver provides its own interrupt handler
> > XTmrCtr_InterruptHandler() which you should use to service the
> > interrupt. =A0It will issue a callback to a function of your choice (se=
t
> > with XTmrCtr_SetHandler)
>
> > Hope this helps,
>
> > David- Hide quoted text -
>
> > - Show quoted text -- Hide quoted text -
>
> - Show quoted text -- Hide quoted text -
>
> - Show quoted text -
Article: 136626Hi Guys, I am trying to figure out a way to infer dual port ROM using BRAM on Xilinx FPGAs. Documentation shows how to infer single port ROMs but couldn't find any info on dual port. Any info on this will be greatly appreciaied. Cheers SudhirArticle: 136627
On 2008-11-27, ikki <jasperng10@gmail.com> wrote: > Hi there, I tried to run my design using modelsim through Xilinx ISE, > However it seems i keep encountering this problem. Can anyone know what > isthe problem and how to fix this ? ... It seems to be missing a library > named simprim. But I have no idea how to get the library and implement it ? > .. You will need to compile the Xilinx simulation libraries. You can compile this library using the compxlib command. (You can also click somewhere in ISE to compile it but I don't remember exactly where right now, I usually don't use the GUI any longer.) /AndreasArticle: 136628
Sudhir.Singh@email.com wrote:
> I am trying to figure out a way to infer dual port ROM using BRAM on
> Xilinx FPGAs.
I would infer two identical single port ROMs
like the rom example here:
http://mysite.verizon.net/miketreseler/
True dual port bram is vendor specific
and probably has to be instanced
rather than inferred.
Good luck.
-- Mike Treseler
Article: 136629Hi there, I tried to run my design using modelsim through Xilinx ISE, However it seems i keep encountering this problem. Can anyone know what isthe problem and how to fix this ? ... It seems to be missing a library named simprim. But I have no idea how to get the library and implement it ? ... Help is appreciated thanks. # -- Loading package standard # -- Loading package std_logic_1164 # ** Error: (vcom-19) Failed to access library 'simprim' at "simprim". # No such file or directory. (errno = ENOENT) # ** Error: C:/FPGAdv71LSPS/Modeltech/win32/vcom failed. # Error in macro ./tb_TopLevelRS232.tdo line 6 # C:/FPGAdv71LSPS/Modeltech/win32/vcom failed. # while executing # "vcom -explicit -93 "netgen/par/TopLevelRS232_timesim.vhd"" jasperngArticle: 136630
On 27 =D7=A0=D7=95=D7=91=D7=9E=D7=91=D7=A8, 03:47, Sudhir.Si...@email.com w= rote: > Hi Guys, > I am trying to figure out a way to infer dual port ROM using BRAM on > Xilinx FPGAs. Documentation shows how to infer single port ROMs but > couldn't find any info on dual port. > Any info on this will be greatly appreciaied. > > Cheers > Sudhir You may want to look at h--p://bknpk.no-ip.biz/cpu_8051_ver/top.html. There are two examples for RAM and ROM usage (i8051_ram_x.v and i8051_rom_x.v). There are a lot of others examples both VHDL and verilog for RAM and RAM (h--p://bknpk.no-ip.biz).Article: 136631
ikki wrote:
> # ** Error: C:/FPGAdv71LSPS/Modeltech/win32/vcom failed.
Click up a shell, bash or cmd.exe
mkdir play
cd play
vcom
If this doesn't give you the vcom usage,
type "exit" to close the shell,
find vcom, and add it's location
to your path and try again.
-- Mike Treseler
Article: 136632On 2008-11-27, Robert <Robert.Blank@gmx.at> wrote: > Hi > > I am aware of the fact, that "implementing" a cache on an FPGA is not > really compareable to a real cache. Anyway, in my architecture I wanna > have such a kind of memory hierarchy with RAM and a Cache. So I wonder > if I can realise a N-Way Set Associative cache on an FPGA? Obviously it > should use the BRAM for the memory ressources as I just have around 5000 > slices on my device. Maybe someone can point me out to an example where > someone has tried to do such a FPGA implementation! This is of course possible (assuming N is around 2-4 or so). You can look at the sourcecode of for example Mico32 to find some examples if I remember correctly. However, I have not found any good information about how to really optimize a cache for an FPGA (and I have looked around a bit). If anyone knows of a good paper about optimizing caches for FPGAs I would be quite interested in that. /AndreasArticle: 136633
Sudhir.Singh@email.com wrote: > Hi Guys, > I am trying to figure out a way to infer dual port ROM using BRAM on > Xilinx FPGAs. Documentation shows how to infer single port ROMs but > couldn't find any info on dual port. > Any info on this will be greatly appreciaied. A look in .../Xilinx/10.1/ISE/doc/usenglish/books/docs/xst/xst.pdf might also help. -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 136634
On Mon, 24 Nov 2008 09:25:50 -0800, osquillar wrote: > Hello all, does anyone any experience using the opb2wb bridge and the > can core from opencores?. > I've already installed the opb2wb bridge in xilinx edk but I would like > to know how to interface the can core with this opb2wb bridge. Once this > bridge is installed I would like how to work with this bridge. You might try asking this question on the OpenCores mailing list (cores@opencores.org). I believe the cores are originally from asics.ws, so you could always pay for some support from them... HTH, JeremyArticle: 136635
On 26 Nov., 19:05, palvarez <pabloalvarezsanc...@gmail.com> wrote: > For several reasons a need very low jitter on some of my outputs. I > was thinking of using LVDS for my I/Os and of course I do not consider > using a clock manager. Do you have an idea of the order of magnitude > of jitter one can get? What fpga would you recomend for a low cost > small design? You have quite a lot of jitter inside an FPGA. We see on the order of 300ps jitter at the output of an Spartan-3 driven by an output flip-flop with a clock driven by a BUFG driven by a DCM. Using the Virtex-5 PLL you should get less jitter. The best Jitter should have an output that uses a regional clock input routed via a BUFIO. Kolja SulimmaArticle: 136636
Hi I am aware of the fact, that "implementing" a cache on an FPGA is not really compareable to a real cache. Anyway, in my architecture I wanna have such a kind of memory hierarchy with RAM and a Cache. So I wonder if I can realise a N-Way Set Associative cache on an FPGA? Obviously it should use the BRAM for the memory ressources as I just have around 5000 slices on my device. Maybe someone can point me out to an example where someone has tried to do such a FPGA implementation! Thanks for your help in advance, RobertArticle: 136637
I am trying to set up my ethernetblaster and having some problems. When I tried the autodetect feature, it worked ok. However, I typed no password and the connection status was "authentication failure". This was expected. What was not expected is that I cannot change the password. I also cannot "remove server" because this button appears shaded! Next, I set up the ethernetblaster server on another IP address, and tried to connect providing the correct password. In the "currently selected hardware", and indication of the server appears but when I close the "Hardware setup" window, the programmer still keeps saying "No hardware" in the top line. I suspect that if I could remove the "bad" server (actually, now I have even 2 of them, with a fake one showing "connecting..." all the time) I could try again but this seems impossible. Any hints? PereArticle: 136638
> I am aware of the fact, that "implementing" a cache on an FPGA is not > really compareable to a real cache. What makes you say that? The current crop of FPGA CPUs don't have multilevel caches, but otherwise they are very similar to the caches you would find in older CPUs. Cheers, JonArticle: 136639
Hi Kolja, "Kolja Sulimma" <ksulimma@googlemail.com> wrote in message news:a48f4020-7f8a-4ce8-949a-e27397d7a370@q9g2000yqc.googlegroups.com... > > Using the Virtex-5 PLL you should get less jitter. Maybe. Maybe not. I do not believe that "PLLs always reduce the jitter inherent on a reference clock." even though Xilinx claim this rubbish in their V5 user guide. (UG190 (v4.3) pg.91). Here's a counter-example. http://www.edn.com/contents/images/6475013.pdf Whatever, the OP's question is too vague to meaningfully answer. He fails to indicate what frequency of jitter he is interested in. Jitter is generally defined from 10Hz upwards, but often 1UI of jitter at 10Hz is inconsequential, but 1UI at 10MHz probably will be a bother. FWIW, common sources of noise which will produce jitter include power supply noise, SSOs, other clocks in the design. Trying to stop these coupling into the outputs when they are all present on a single FPGA may be difficult. > The best Jitter > should have an output that uses a regional clock input routed via a > BUFIO. > I agree. I believe these resources are driven differentially and so will probably have better immunity to noise sources. For even better performance it may be necessary to retime the signals outside of the FPGA. HTH., Syms.Article: 136640
On Nov 27, 6:14=A0am, Bryan <bryan.fletc...@avnet.com> wrote:
> Not sure what the problem is with your code. =A0Here's an example with
> one timer. =A0It's 10.1, but there weren't any changes in the interrupt
> stuff between 9.2 and 10.1 (so I'm told). =A0This is based on a lab from
> one of Avnet's Speedway trainings. =A0I ran it on the Xilinx Spartan-3A
> DSP 1800A Starter and verified that the interrupts are indeed
> happening. =A0There is a bit file in the project directory if you don't
> want to rebuild the project.
>
> Bryan
>
> The following file has been made available for you to download from
> Avnet's File Transfer web site:http://xfer.avnet.com/uploads/Xil3S1800ADS=
P_Interrupt_v10.1.03.zip
I downloaded the timer_interrupt.bit file into FPGA using impact, the
timer example worked FINE.
It generated the required output and interrrupt was working. BUT
I could not use the system.xmp present in
http://xfer.avnet.com/uploads/Xil3S1800ADSP_Interrupt_v10.1.03.zip
because
I have edk 9.2i, but it was developed with later version of edk.
And here is the mysterious problem yet to be solved!!
So I developed a base system and used xps interrupt controller and
timer. The MHS file is:
#
###########################################################################=
###
# Created by Base System Builder Wizard for Xilinx EDK 9.2 Build
EDK_Jm.16
# Sun Nov 16 21:24:15 2008
# Target Board: Xilinx Spartan-3A DSP 1800A Starter Board Rev 1
# Family: spartan3adsp
# Device: xc3sd1800a
# Package: fg676
# Speed Grade: -4
# Processor: microblaze_0
# System clock frequency: 62.000000 MHz
# On Chip Memory : 8 KB
#
###########################################################################=
###
PARAMETER VERSION =3D 2.1.0
PORT fpga_0_RS232_Uart_1_RX_pin =3D fpga_0_RS232_Uart_1_RX, DIR =3D I
PORT fpga_0_RS232_Uart_1_TX_pin =3D fpga_0_RS232_Uart_1_TX, DIR =3D O
PORT sys_clk_pin =3D dcm_clk_s, DIR =3D I, SIGIS =3D CLK, CLK_FREQ =3D
125000000
PORT sys_rst_pin =3D sys_rst_s, DIR =3D I, RST_POLARITY =3D 0, SIGIS =3D R=
ST
PORT dip_GPIO_in_pin =3D dip_GPIO_in, DIR =3D I, VEC =3D [0:7]
PORT push_GPIO_in_pin =3D push_GPIO_in, DIR =3D I, VEC =3D [0:3]
PORT led_GPIO_IO_pin =3D led_GPIO_IO, DIR =3D IO, VEC =3D [0:7]
BEGIN microblaze
PARAMETER HW_VER =3D 7.00.a
PARAMETER INSTANCE =3D microblaze_0
PARAMETER C_INTERCONNECT =3D 1
PARAMETER C_DEBUG_ENABLED =3D 1
PARAMETER C_AREA_OPTIMIZED =3D 1
BUS_INTERFACE DLMB =3D dlmb
BUS_INTERFACE ILMB =3D ilmb
BUS_INTERFACE DPLB =3D mb_plb
BUS_INTERFACE IPLB =3D mb_plb
BUS_INTERFACE DEBUG =3D microblaze_0_dbg
PORT RESET =3D mb_reset
PORT INTERRUPT =3D Interrupt
END
BEGIN plb_v46
PARAMETER INSTANCE =3D mb_plb
PARAMETER HW_VER =3D 1.00.a
PORT PLB_Clk =3D sys_clk_s
PORT SYS_Rst =3D sys_bus_reset
END
BEGIN lmb_v10
PARAMETER INSTANCE =3D ilmb
PARAMETER HW_VER =3D 1.00.a
PORT LMB_Clk =3D sys_clk_s
PORT SYS_Rst =3D sys_bus_reset
END
BEGIN lmb_v10
PARAMETER INSTANCE =3D dlmb
PARAMETER HW_VER =3D 1.00.a
PORT LMB_Clk =3D sys_clk_s
PORT SYS_Rst =3D sys_bus_reset
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE =3D dlmb_cntlr
PARAMETER HW_VER =3D 2.10.a
PARAMETER C_BASEADDR =3D 0x00000000
PARAMETER C_HIGHADDR =3D 0x00003fff
BUS_INTERFACE SLMB =3D dlmb
BUS_INTERFACE BRAM_PORT =3D dlmb_port
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE =3D ilmb_cntlr
PARAMETER HW_VER =3D 2.10.a
PARAMETER C_BASEADDR =3D 0x00000000
PARAMETER C_HIGHADDR =3D 0x00003fff
BUS_INTERFACE SLMB =3D ilmb
BUS_INTERFACE BRAM_PORT =3D ilmb_port
END
BEGIN bram_block
PARAMETER INSTANCE =3D lmb_bram
PARAMETER HW_VER =3D 1.00.a
BUS_INTERFACE PORTA =3D ilmb_port
BUS_INTERFACE PORTB =3D dlmb_port
END
BEGIN xps_uartlite
PARAMETER INSTANCE =3D RS232_Uart_1
PARAMETER HW_VER =3D 1.00.a
PARAMETER C_BAUDRATE =3D 115200
PARAMETER C_ODD_PARITY =3D 0
PARAMETER C_USE_PARITY =3D 0
PARAMETER C_SPLB_CLK_FREQ_HZ =3D 62500000
PARAMETER C_BASEADDR =3D 0x84000000
PARAMETER C_HIGHADDR =3D 0x8400ffff
BUS_INTERFACE SPLB =3D mb_plb
PORT RX =3D fpga_0_RS232_Uart_1_RX
PORT TX =3D fpga_0_RS232_Uart_1_TX
END
BEGIN clock_generator
PARAMETER INSTANCE =3D clock_generator_0
PARAMETER HW_VER =3D 1.00.a
PARAMETER C_EXT_RESET_HIGH =3D 1
PARAMETER C_CLKIN_FREQ =3D 125000000
PARAMETER C_CLKOUT0_FREQ =3D 62500000
PARAMETER C_CLKOUT0_PHASE =3D 0
PARAMETER C_CLKOUT0_GROUP =3D NONE
PORT CLKOUT0 =3D sys_clk_s
PORT CLKIN =3D dcm_clk_s
PORT LOCKED =3D Dcm_all_locked
PORT RST =3D net_gnd
END
BEGIN mdm
PARAMETER INSTANCE =3D debug_module
PARAMETER HW_VER =3D 1.00.a
PARAMETER C_MB_DBG_PORTS =3D 1
PARAMETER C_USE_UART =3D 1
PARAMETER C_UART_WIDTH =3D 8
PARAMETER C_BASEADDR =3D 0x84400000
PARAMETER C_HIGHADDR =3D 0x8440ffff
BUS_INTERFACE SPLB =3D mb_plb
BUS_INTERFACE MBDEBUG_0 =3D microblaze_0_dbg
PORT Debug_SYS_Rst =3D Debug_SYS_Rst
END
BEGIN proc_sys_reset
PARAMETER INSTANCE =3D proc_sys_reset_0
PARAMETER HW_VER =3D 2.00.a
PARAMETER C_EXT_RESET_HIGH =3D 0
PORT Slowest_sync_clk =3D sys_clk_s
PORT Dcm_locked =3D Dcm_all_locked
PORT Ext_Reset_In =3D sys_rst_s
PORT MB_Reset =3D mb_reset
PORT Bus_Struct_Reset =3D sys_bus_reset
PORT MB_Debug_Sys_Rst =3D Debug_SYS_Rst
END
BEGIN xps_gpio
PARAMETER INSTANCE =3D push
PARAMETER HW_VER =3D 1.00.a
PARAMETER C_GPIO_WIDTH =3D 4
PARAMETER C_ALL_INPUTS =3D 1
PARAMETER C_IS_BIDIR =3D 0
PARAMETER C_BASEADDR =3D 0x8141c200
PARAMETER C_HIGHADDR =3D 0x8141c3ff
BUS_INTERFACE SPLB =3D mb_plb
PORT GPIO_in =3D push_GPIO_in
END
BEGIN xps_gpio
PARAMETER INSTANCE =3D dip
PARAMETER HW_VER =3D 1.00.a
PARAMETER C_GPIO_WIDTH =3D 8
PARAMETER C_ALL_INPUTS =3D 1
PARAMETER C_IS_BIDIR =3D 0
PARAMETER C_BASEADDR =3D 0x81420000
PARAMETER C_HIGHADDR =3D 0x8142ffff
BUS_INTERFACE SPLB =3D mb_plb
PORT GPIO_in =3D dip_GPIO_in
END
BEGIN xps_gpio
PARAMETER INSTANCE =3D led
PARAMETER HW_VER =3D 1.00.a
PARAMETER C_GPIO_WIDTH =3D 8
PARAMETER C_IS_BIDIR =3D 0
PARAMETER C_BASEADDR =3D 0x81400000
PARAMETER C_HIGHADDR =3D 0x8140ffff
BUS_INTERFACE SPLB =3D mb_plb
PORT GPIO_IO =3D led_GPIO_IO
END
BEGIN xps_timer
PARAMETER INSTANCE =3D xps_timer_0
PARAMETER HW_VER =3D 1.00.a
PARAMETER C_BASEADDR =3D 0x81418000
PARAMETER C_HIGHADDR =3D 0x814181ff
PARAMETER C_ONE_TIMER_ONLY =3D 1
BUS_INTERFACE SPLB =3D mb_plb
PORT Interrupt =3D xps_timer_0_Interrupt
END
BEGIN xps_intc
PARAMETER INSTANCE =3D xps_intc_0
PARAMETER HW_VER =3D 1.00.a
PARAMETER C_BASEADDR =3D 0x81414000
PARAMETER C_HIGHADDR =3D 0x814141ff
BUS_INTERFACE SPLB =3D mb_plb
PORT Irq =3D Interrupt
PORT Intr =3D xps_timer_0_Interrupt
END
In xps_intc I have connected only timer interrupt to its Intr pin and
other interrupts like
from push buttons and other are NOT CONNECTED.
Then I used "timer.c" provided in the link (I have not used external
DDR2 SDRAM), and the result:
Starting Timer example
Timer example FAILED
So, I am really confused here!!
>
> Click on the hyperlink or enter this URL into your web browser to
> retrieve the file.
> This file will remain on the server for approximately 5 days from the
> date of the upload at which time it will be deleted. =A0Please be sure
> to download it before the expiration time.
> This file will expire on Dec =A01, 2008.
>
> File Size: 232357 Bytes
>
> On Nov 26, 12:22=A0am, bish <bishes...@gmail.com> wrote:
>
>
>
> > On Nov 26, 4:58=A0am, David <simianfe...@gmail.com> wrote:
>
> > > On Nov 26, 2:37=A0am, bish <bishes...@gmail.com> wrote:
>
> > > > On Nov 25, 12:25=A0pm, Matthias Alles <REMOVEallesCAPIT...@NOeit.SP=
AMuni-
>
> > > > kl.de> wrote:
> > > > > Hi!
>
> > > > > I wonder, whether "one_second_flag" is declared as volatile? If n=
ot, the
> > > > > compiler optimizes your if-statement in the while(1) loop away. Y=
ou can
> > > > > check this by using mb-objdump.
>
> > > > I tried using the volatile for one_second_flag, still it does not
> > > > work. It just prints "the value of count =3D 1" once in terminal an=
d
> > > > nothing happens then.
>
> > > > > Cheers,
> > > > > Matthias
>
> > > > > bish schrieb:
>
> > > > > > I am trying to use a timer for regular interrupt in microblaze.=
I am
> > > > > > using edk 9.2i and spartan 3a dsp 1800a.
> > > > > > Even following a simple lab example widely used by beginners di=
dn't
> > > > > > work:http://users.utcluj.ro/~baruch/ssce/labor/EDK-L5-e.pdf
>
> > > > > > I have connected all the interrupt ports correctly as evident f=
rom the
> > > > > > following portion of the mhs file:
> > > > > > BEGIN microblaze
> > > > > > =A0PARAMETER HW_VER =3D 7.00.a
> > > > > > ...........
> > > > > > ...........
> > > > > > PORT INTERRUPT =3D interrupt
> > > > > > END
>
> > > > > > BEGIN xps_timer
> > > > > > =A0PARAMETER INSTANCE =3D delay
> > > > > > =A0PARAMETER HW_VER =3D 1.00.a
> > > > > > =A0PARAMETER C_ONE_TIMER_ONLY =3D 1
> > > > > > =A0PARAMETER C_BASEADDR =3D 0x8141c200
> > > > > > =A0PARAMETER C_HIGHADDR =3D 0x8141c3ff
> > > > > > =A0BUS_INTERFACE SPLB =3D mb_plb
> > > > > > =A0PORT Interrupt =3D timer1
> > > > > > =A0PORT CaptureTrig0 =3D net_gnd
> > > > > > END
>
> > > > > > BEGIN xps_intc
> > > > > > =A0PARAMETER INSTANCE =3D xps_intc_0
> > > > > > =A0PARAMETER HW_VER =3D 1.00.a
> > > > > > =A0PARAMETER C_BASEADDR =3D 0x81418000
> > > > > > =A0PARAMETER C_HIGHADDR =3D 0x814181ff
> > > > > > =A0BUS_INTERFACE SPLB =3D mb_plb
> > > > > > =A0PORT Irq =3D interrupt
> > > > > > =A0PORT Intr =3D timer1
> > > > > > END
>
> > > > > > Now for the software settings since I am using edk 9.2i, it doe=
s not
> > > > > > have option for registering our interrupt handler in software p=
latform
> > > > > > settings window (which is what the lab suggests), I used the
> > > > > > microblaze_register_handler(...) function ( I took me 3 days to=
figure
> > > > > > out this), =A0but I still don't get how it works differently fr=
om the
> > > > > > function XIntc_RegisterHandler.
> > > > > > The portion of C file is as follows:
> > > > > > void timer_int_handler(void * baseaddr_p) {
> > > > > > =A0 =A0 /* Add variable declarations here */
> > > > > > =A0 =A0unsigned int csr;
> > > > > > =A0 =A0/* Read timer 0 CSR to see if it raised the interrupt */
> > > > > > =A0 =A0csr =3D XTmrCtr_mGetControlStatusReg(XPAR_DELAY_BASEADDR=
,0);
> > > > > > =A0 =A0/* If the interrupt occurred, then increment a counter *=
/
> > > > > > =A0 =A0/* and set one_second_flag to 1 */
> > > > > > =A0 =A0if (csr & XTC_CSR_INT_OCCURED_MASK ) {
> > > > > > =A0 =A0 =A0 =A0 =A0 =A0count ++;
> > > > > > =A0 =A0 =A0 =A0 =A0 =A0one_second_flag =3D 1;
> > > > > > =A0 =A0}
>
> > > > > > =A0 =A0/* Display the count on the LEDs */
> > > > > > =A0 =A0XGpio_mSetDataReg(XPAR_LED_HIGHADDR, LEDChan, count);
>
> > > > > > =A0 =A0/* Print the count using the UART*/
> > > > > > =A0 =A0xil_printf("count value is: %x\n\r", count);
> > > > > > =A0 =A0/* Clear the timer interrupt */
> > > > > > =A0 =A0XTmrCtr_mSetControlStatusReg(XPAR_DELAY_BASEADDR,0,csr);
> > > > > > }
>
> > > > > > int main() {
>
> > > > > > =A0 int count_mod_3;
>
> > > > > > =A0 //registering an interrupt handler
> > > > > > =A0 microblaze_register_handler((XInterruptHandler) timer_int_h=
andler,
> > > > > > (void *)0);
>
> > > > > > =A0 /* Register the Timer interrupt handler in the vector table=
*/
> > > > > > =A0 XIntc_RegisterHandler(XPAR_XPS_INTC_0_BASEADDR,
> > > > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0XPAR=
_XPS_INTC_0_DELAY_INTERRUPT_INTR,
> > > > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0(XIn=
terruptHandler) timer_int_handler,
> > > > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0(voi=
d *)XPAR_DELAY_BASEADDR);
> > > > > > =A0 /* Enable MicroBlaze Interrupts */
> > > > > > =A0 microblaze_enable_interrupts();
>
> > > > > > =A0 /* Initialize and set the direction of the GPIO connected t=
o LEDs */
> > > > > > =A0 XGpio_Initialize(&gpio, XPAR_LED_DEVICE_ID);
> > > > > > =A0 XGpio_SetDataDirection(&gpio,LEDChan, 0);
>
> > > > > > =A0 /* Start the interrupt controller */
> > > > > > =A0 XIntc_mMasterEnable(XPAR_XPS_INTC_0_BASEADDR);
> > > > > > =A0 XIntc_mEnableIntr(XPAR_XPS_INTC_0_BASEADDR, 0x1);
>
> > > > > > =A0 /* Set the gpio as output on high 8 bits (LEDs)*/
> > > > > > =A0 XGpio_mSetDataReg(XPAR_LED_DEVICE_ID,LEDChan, ~count);
> > > > > > =A0 xil_printf("The value of count =3D %d\n\r", count);
>
> > > > > > =A0 /* Set the number of cycles the timer counts before interru=
pting */
> > > > > > =A0 XTmrCtr_mSetLoadReg(XPAR_DELAY_BASEADDR, 0,
> > > > > > (timer_count*timer_count) * 50000000);
>
> > > > > > =A0 /* Reset the timers, and clear interrupts */
> > > > > > =A0 XTmrCtr_mSetControlStatusReg(XPAR_DELAY_BASEADDR, 0,
> > > > > > XTC_CSR_INT_OCCURED_MASK | XTC_CSR_LOAD_MASK );
>
> > > > > > =A0 /* Enable timer interrupts in the interrupt controller */
> > > > > > =A0 XIntc_mEnableIntr(XPAR_DELAY_BASEADDR, XPAR_DELAY_INTERRUPT=
_MASK);
>
> > > > > > =A0 /* Start the timers */
> > > > > > =A0 XTmrCtr_mSetControlStatusReg(XPAR_DELAY_BASEADDR, 0,
> > > > > > XTC_CSR_ENABLE_TMR_MASK | XTC_CSR_ENABLE_INT_MASK |
> > > > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
=A0 =A0 =A0 =A0 =A0 =A0XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK)=
;
>
> > > > > > =A0 /* Wait for interrupts to occur */
> > > > > > =A0 while(1) {
> > > > > > =A0 =A0if(one_second_flag){
> > > > > > =A0 =A0 =A0 =A0 =A0 =A0count_mod_3 =3D count % 3;
> > > > > > =A0 =A0 =A0 =A0 =A0 =A0if(count_mod_3 =3D=3D 0)
> > > > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0xil_printf("Interrupt ta=
ken at %d seconds \n\r",count);
> > > > > > =A0 =A0 =A0 =A0 =A0 =A0one_second_flag=3D0;
> > > > > > =A0 =A0 =A0 =A0 =A0 =A0xil_printf(".");
> > > > > > =A0 =A0 =A0 =A0 =A0 =A0}
> > > > > > =A0 =A0}
> > > > > > }
>
> > > > > > When I run the system, the value of count does not change from =
1. What
> > > > > > could be the problem?- Hide quoted text -
>
> > > > > - Show quoted text -
>
> > > Hello,
>
> > > Here is how I set up a timer interrupt in 9.2:
>
> > > void TimerCounterHandler(void *CallBackRef)
> > > {
> > > =A0 =A0 =A0 =A0 print("timer interrupt ");
>
> > > }
>
> > > Int main (void) {
>
> > > =A0 =A0 =A0 =A0 XIntc intr_ctrl;
> > > =A0 =A0 =A0 =A0 XTmrCtr timr;
>
> > > =A0 =A0 =A0 =A0 XIntc_Initialize(&intr_ctrl,XPAR_XPS_INTC_0_DEVICE_ID=
);
> > > =A0 =A0 =A0 =A0 XTmrCtr_Initialize(&timr,XPAR_XPS_TIMER_1_DEVICE_ID);
>
> > > =A0 =A0 =A0 =A0 XIntc_Connect(&intr_ctrl, XPAR_XPS_INTC_0_XPS_TIMER_1=
_INTERRUPT_INTR,
> > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0(XInterruptHan=
dler)
> > > XTmrCtr_InterruptHandler,
> > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0(void *)&timr)=
;
>
> > > =A0 =A0 =A0 =A0 XIntc_Start(&intr_ctrl, XIN_REAL_MODE);
>
> > > =A0 =A0 =A0 =A0 XIntc_Enable(&intr_ctrl, XPAR_XPS_INTC_0_XPS_TIMER_1_=
INTERRUPT_INTR);
>
> > > =A0 =A0 =A0 =A0 XTmrCtr_SetHandler(&timr, (void *)TimerCounterHandler=
, void);
>
> > This issued an error so I replaced void with NULL in the third
> > argument above. Apart from that I didn't change anything, but still
> > the terminal never printed "timer interrupt" so still the problem
> > remains!!
>
> > > =A0 =A0 =A0 =A0 XTmrCtr_SetOptions(&timr, 0,
> > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0XTC_INT_MODE_OPTION | =
XTC_AUTO_RELOAD_OPTION);
>
> > > =A0 =A0 =A0 =A0 XTmrCtr_SetResetValue(&timr, 0, 0xF0000000);
>
> > > =A0 =A0 =A0 =A0 XTmrCtr_Start(&timr,0);
>
> > > =A0 =A0 =A0 =A0 microblaze_enable_interrupts();
>
> > > =A0 =A0 =A0 =A0while(1){
> > > =A0 =A0 =A0 //wait for interrupts
> > > =A0 =A0 =A0 }
>
> > > }
>
> > > If you are using the Intc component, you no longer need to use the
> > > microblaze_register_handler function - instead use the XIntc_Connect(=
)
> > > function.
> > > The XTmrCtr driver provides its own interrupt handler
> > > XTmrCtr_InterruptHandler() which you should use to service the
> > > interrupt. =A0It will issue a callback to a function of your choice (=
set
> > > with XTmrCtr_SetHandler)
>
> > > Hope this helps,
>
> > > David- Hide quoted text -
>
> > > - Show quoted text -- Hide quoted text -
>
> > - Show quoted text -- Hide quoted text -
>
> > - Show quoted text -- Hide quoted text -
>
> - Show quoted text -
Article: 136641
On Nov 27, 10:08=A0pm, bish <bishes...@gmail.com> wrote:
> On Nov 27, 6:14=A0am, Bryan <bryan.fletc...@avnet.com> wrote:
>
> > Not sure what the problem is with your code. =A0Here's an example with
> > one timer. =A0It's 10.1, but there weren't any changes in the interrupt
> > stuff between 9.2 and 10.1 (so I'm told). =A0This is based on a lab fro=
m
> > one of Avnet's Speedway trainings. =A0I ran it on the Xilinx Spartan-3A
> > DSP 1800A Starter and verified that the interrupts are indeed
> > happening. =A0There is a bit file in the project directory if you don't
> > want to rebuild the project.
>
> > Bryan
>
> > The following file has been made available for you to download from
> > Avnet's File Transfer web site:http://xfer.avnet.com/uploads/Xil3S1800A=
DSP_Interrupt_v10.1.03.zip
>
> I downloaded the timer_interrupt.bit file into FPGA using impact, the
> timer example worked FINE.
> It generated the required output and interrrupt was working. BUT
>
> I could not use the system.xmp present inhttp://xfer.avnet.com/uploads/Xi=
l3S1800ADSP_Interrupt_v10.1.03.zip
> because
> I have edk 9.2i, but it was developed with later version of edk.
>
> And here is the mysterious problem yet to be solved!!
> So I developed a base system and used xps interrupt controller and
> timer. The MHS file is:
>
> #
> #########################################################################=
##=AD###
> # Created by Base System Builder Wizard for Xilinx EDK 9.2 Build
> EDK_Jm.16
> # Sun Nov 16 21:24:15 2008
> # Target Board: =A0Xilinx Spartan-3A DSP 1800A Starter Board Rev 1
> # Family: =A0 =A0 =A0 =A0spartan3adsp
> # Device: =A0 =A0 =A0 =A0xc3sd1800a
> # Package: =A0 =A0 =A0 fg676
> # Speed Grade: =A0 -4
> # Processor: microblaze_0
> # System clock frequency: 62.000000 MHz
> # On Chip Memory : =A0 8 KB
> #
> #########################################################################=
##=AD###
> =A0PARAMETER VERSION =3D 2.1.0
>
> =A0PORT fpga_0_RS232_Uart_1_RX_pin =3D fpga_0_RS232_Uart_1_RX, DIR =3D I
> =A0PORT fpga_0_RS232_Uart_1_TX_pin =3D fpga_0_RS232_Uart_1_TX, DIR =3D O
> =A0PORT sys_clk_pin =3D dcm_clk_s, DIR =3D I, SIGIS =3D CLK, CLK_FREQ =3D
> 125000000
> =A0PORT sys_rst_pin =3D sys_rst_s, DIR =3D I, RST_POLARITY =3D 0, SIGIS =
=3D RST
> =A0PORT dip_GPIO_in_pin =3D dip_GPIO_in, DIR =3D I, VEC =3D [0:7]
> =A0PORT push_GPIO_in_pin =3D push_GPIO_in, DIR =3D I, VEC =3D [0:3]
> =A0PORT led_GPIO_IO_pin =3D led_GPIO_IO, DIR =3D IO, VEC =3D [0:7]
>
> BEGIN microblaze
> =A0PARAMETER HW_VER =3D 7.00.a
> =A0PARAMETER INSTANCE =3D microblaze_0
> =A0PARAMETER C_INTERCONNECT =3D 1
> =A0PARAMETER C_DEBUG_ENABLED =3D 1
> =A0PARAMETER C_AREA_OPTIMIZED =3D 1
> =A0BUS_INTERFACE DLMB =3D dlmb
> =A0BUS_INTERFACE ILMB =3D ilmb
> =A0BUS_INTERFACE DPLB =3D mb_plb
> =A0BUS_INTERFACE IPLB =3D mb_plb
> =A0BUS_INTERFACE DEBUG =3D microblaze_0_dbg
> =A0PORT RESET =3D mb_reset
> =A0PORT INTERRUPT =3D Interrupt
> END
>
> BEGIN plb_v46
> =A0PARAMETER INSTANCE =3D mb_plb
> =A0PARAMETER HW_VER =3D 1.00.a
> =A0PORT PLB_Clk =3D sys_clk_s
> =A0PORT SYS_Rst =3D sys_bus_reset
> END
>
> BEGIN lmb_v10
> =A0PARAMETER INSTANCE =3D ilmb
> =A0PARAMETER HW_VER =3D 1.00.a
> =A0PORT LMB_Clk =3D sys_clk_s
> =A0PORT SYS_Rst =3D sys_bus_reset
> END
>
> BEGIN lmb_v10
> =A0PARAMETER INSTANCE =3D dlmb
> =A0PARAMETER HW_VER =3D 1.00.a
> =A0PORT LMB_Clk =3D sys_clk_s
> =A0PORT SYS_Rst =3D sys_bus_reset
> END
>
> BEGIN lmb_bram_if_cntlr
> =A0PARAMETER INSTANCE =3D dlmb_cntlr
> =A0PARAMETER HW_VER =3D 2.10.a
> =A0PARAMETER C_BASEADDR =3D 0x00000000
> =A0PARAMETER C_HIGHADDR =3D 0x00003fff
> =A0BUS_INTERFACE SLMB =3D dlmb
> =A0BUS_INTERFACE BRAM_PORT =3D dlmb_port
> END
>
> BEGIN lmb_bram_if_cntlr
> =A0PARAMETER INSTANCE =3D ilmb_cntlr
> =A0PARAMETER HW_VER =3D 2.10.a
> =A0PARAMETER C_BASEADDR =3D 0x00000000
> =A0PARAMETER C_HIGHADDR =3D 0x00003fff
> =A0BUS_INTERFACE SLMB =3D ilmb
> =A0BUS_INTERFACE BRAM_PORT =3D ilmb_port
> END
>
> BEGIN bram_block
> =A0PARAMETER INSTANCE =3D lmb_bram
> =A0PARAMETER HW_VER =3D 1.00.a
> =A0BUS_INTERFACE PORTA =3D ilmb_port
> =A0BUS_INTERFACE PORTB =3D dlmb_port
> END
>
> BEGIN xps_uartlite
> =A0PARAMETER INSTANCE =3D RS232_Uart_1
> =A0PARAMETER HW_VER =3D 1.00.a
> =A0PARAMETER C_BAUDRATE =3D 115200
> =A0PARAMETER C_ODD_PARITY =3D 0
> =A0PARAMETER C_USE_PARITY =3D 0
> =A0PARAMETER C_SPLB_CLK_FREQ_HZ =3D 62500000
> =A0PARAMETER C_BASEADDR =3D 0x84000000
> =A0PARAMETER C_HIGHADDR =3D 0x8400ffff
> =A0BUS_INTERFACE SPLB =3D mb_plb
> =A0PORT RX =3D fpga_0_RS232_Uart_1_RX
> =A0PORT TX =3D fpga_0_RS232_Uart_1_TX
> END
>
> BEGIN clock_generator
> =A0PARAMETER INSTANCE =3D clock_generator_0
> =A0PARAMETER HW_VER =3D 1.00.a
> =A0PARAMETER C_EXT_RESET_HIGH =3D 1
> =A0PARAMETER C_CLKIN_FREQ =3D 125000000
> =A0PARAMETER C_CLKOUT0_FREQ =3D 62500000
> =A0PARAMETER C_CLKOUT0_PHASE =3D 0
> =A0PARAMETER C_CLKOUT0_GROUP =3D NONE
> =A0PORT CLKOUT0 =3D sys_clk_s
> =A0PORT CLKIN =3D dcm_clk_s
> =A0PORT LOCKED =3D Dcm_all_locked
> =A0PORT RST =3D net_gnd
> END
>
> BEGIN mdm
> =A0PARAMETER INSTANCE =3D debug_module
> =A0PARAMETER HW_VER =3D 1.00.a
> =A0PARAMETER C_MB_DBG_PORTS =3D 1
> =A0PARAMETER C_USE_UART =3D 1
> =A0PARAMETER C_UART_WIDTH =3D 8
> =A0PARAMETER C_BASEADDR =3D 0x84400000
> =A0PARAMETER C_HIGHADDR =3D 0x8440ffff
> =A0BUS_INTERFACE SPLB =3D mb_plb
> =A0BUS_INTERFACE MBDEBUG_0 =3D microblaze_0_dbg
> =A0PORT Debug_SYS_Rst =3D Debug_SYS_Rst
> END
>
> BEGIN proc_sys_reset
> =A0PARAMETER INSTANCE =3D proc_sys_reset_0
> =A0PARAMETER HW_VER =3D 2.00.a
> =A0PARAMETER C_EXT_RESET_HIGH =3D 0
> =A0PORT Slowest_sync_clk =3D sys_clk_s
> =A0PORT Dcm_locked =3D Dcm_all_locked
> =A0PORT Ext_Reset_In =3D sys_rst_s
> =A0PORT MB_Reset =3D mb_reset
> =A0PORT Bus_Struct_Reset =3D sys_bus_reset
> =A0PORT MB_Debug_Sys_Rst =3D Debug_SYS_Rst
> END
>
> BEGIN xps_gpio
> =A0PARAMETER INSTANCE =3D push
> =A0PARAMETER HW_VER =3D 1.00.a
> =A0PARAMETER C_GPIO_WIDTH =3D 4
> =A0PARAMETER C_ALL_INPUTS =3D 1
> =A0PARAMETER C_IS_BIDIR =3D 0
> =A0PARAMETER C_BASEADDR =3D 0x8141c200
> =A0PARAMETER C_HIGHADDR =3D 0x8141c3ff
> =A0BUS_INTERFACE SPLB =3D mb_plb
> =A0PORT GPIO_in =3D push_GPIO_in
> END
>
> BEGIN xps_gpio
> =A0PARAMETER INSTANCE =3D dip
> =A0PARAMETER HW_VER =3D 1.00.a
> =A0PARAMETER C_GPIO_WIDTH =3D 8
> =A0PARAMETER C_ALL_INPUTS =3D 1
> =A0PARAMETER C_IS_BIDIR =3D 0
> =A0PARAMETER C_BASEADDR =3D 0x81420000
> =A0PARAMETER C_HIGHADDR =3D 0x8142ffff
> =A0BUS_INTERFACE SPLB =3D mb_plb
> =A0PORT GPIO_in =3D dip_GPIO_in
> END
>
> BEGIN xps_gpio
> =A0PARAMETER INSTANCE =3D led
> =A0PARAMETER HW_VER =3D 1.00.a
> =A0PARAMETER C_GPIO_WIDTH =3D 8
> =A0PARAMETER C_IS_BIDIR =3D 0
> =A0PARAMETER C_BASEADDR =3D 0x81400000
> =A0PARAMETER C_HIGHADDR =3D 0x8140ffff
> =A0BUS_INTERFACE SPLB =3D mb_plb
> =A0PORT GPIO_IO =3D led_GPIO_IO
> END
>
> BEGIN xps_timer
> =A0PARAMETER INSTANCE =3D xps_timer_0
> =A0PARAMETER HW_VER =3D 1.00.a
> =A0PARAMETER C_BASEADDR =3D 0x81418000
> =A0PARAMETER C_HIGHADDR =3D 0x814181ff
> =A0PARAMETER C_ONE_TIMER_ONLY =3D 1
> =A0BUS_INTERFACE SPLB =3D mb_plb
> =A0PORT Interrupt =3D xps_timer_0_Interrupt
> END
>
> BEGIN xps_intc
> =A0PARAMETER INSTANCE =3D xps_intc_0
> =A0PARAMETER HW_VER =3D 1.00.a
> =A0PARAMETER C_BASEADDR =3D 0x81414000
> =A0PARAMETER C_HIGHADDR =3D 0x814141ff
> =A0BUS_INTERFACE SPLB =3D mb_plb
> =A0PORT Irq =3D Interrupt
> =A0PORT Intr =3D xps_timer_0_Interrupt
> END
>
> In xps_intc I have connected only timer interrupt to its Intr pin and
> other interrupts like
> from push buttons and other are NOT CONNECTED.
In the configure ip.. option for xps interrupt controller I could not
change the no. of interrupt inputs (by default it is 2), as it is set
to 2 and disabled.
So I used two timers and connected interrupt pins of these timers to
interrupt controller just make intr inputs 2. Then again I checked
with the "timer.c" file from the link, and still the same result:
Timer example failed !!!
This has already taken so many days and problem is becoming more
mysterious (but frustrating)!!!
> Then I used "timer.c" provided in the link (I have not used external
> DDR2 SDRAM), and the result:
>
> Starting Timer example
> Timer example FAILED
>
> So, I am really confused here!!
>
>
>
>
>
> > Click on the hyperlink or enter this URL into your web browser to
> > retrieve the file.
> > This file will remain on the server for approximately 5 days from the
> > date of the upload at which time it will be deleted. =A0Please be sure
> > to download it before the expiration time.
> > This file will expire on Dec =A01, 2008.
>
> > File Size: 232357 Bytes
>
> > On Nov 26, 12:22=A0am, bish <bishes...@gmail.com> wrote:
>
> > > On Nov 26, 4:58=A0am, David <simianfe...@gmail.com> wrote:
>
> > > > On Nov 26, 2:37=A0am, bish <bishes...@gmail.com> wrote:
>
> > > > > On Nov 25, 12:25=A0pm, Matthias Alles <REMOVEallesCAPIT...@NOeit.=
SPAMuni-
>
> > > > > kl.de> wrote:
> > > > > > Hi!
>
> > > > > > I wonder, whether "one_second_flag" is declared as volatile? If=
not, the
> > > > > > compiler optimizes your if-statement in the while(1) loop away.=
You can
> > > > > > check this by using mb-objdump.
>
> > > > > I tried using the volatile for one_second_flag, still it does not
> > > > > work. It just prints "the value of count =3D 1" once in terminal =
and
> > > > > nothing happens then.
>
> > > > > > Cheers,
> > > > > > Matthias
>
> > > > > > bish schrieb:
>
> > > > > > > I am trying to use a timer for regular interrupt in microblaz=
e. I am
> > > > > > > using edk 9.2i and spartan 3a dsp 1800a.
> > > > > > > Even following a simple lab example widely used by beginners =
didn't
> > > > > > > work:http://users.utcluj.ro/~baruch/ssce/labor/EDK-L5-e.pdf
>
> > > > > > > I have connected all the interrupt ports correctly as evident=
from the
> > > > > > > following portion of the mhs file:
> > > > > > > BEGIN microblaze
> > > > > > > =A0PARAMETER HW_VER =3D 7.00.a
> > > > > > > ...........
> > > > > > > ...........
> > > > > > > PORT INTERRUPT =3D interrupt
> > > > > > > END
>
> > > > > > > BEGIN xps_timer
> > > > > > > =A0PARAMETER INSTANCE =3D delay
> > > > > > > =A0PARAMETER HW_VER =3D 1.00.a
> > > > > > > =A0PARAMETER C_ONE_TIMER_ONLY =3D 1
> > > > > > > =A0PARAMETER C_BASEADDR =3D 0x8141c200
> > > > > > > =A0PARAMETER C_HIGHADDR =3D 0x8141c3ff
> > > > > > > =A0BUS_INTERFACE SPLB =3D mb_plb
> > > > > > > =A0PORT Interrupt =3D timer1
> > > > > > > =A0PORT CaptureTrig0 =3D net_gnd
> > > > > > > END
>
> > > > > > > BEGIN xps_intc
> > > > > > > =A0PARAMETER INSTANCE =3D xps_intc_0
> > > > > > > =A0PARAMETER HW_VER =3D 1.00.a
> > > > > > > =A0PARAMETER C_BASEADDR =3D 0x81418000
> > > > > > > =A0PARAMETER C_HIGHADDR =3D 0x814181ff
> > > > > > > =A0BUS_INTERFACE SPLB =3D mb_plb
> > > > > > > =A0PORT Irq =3D interrupt
> > > > > > > =A0PORT Intr =3D timer1
> > > > > > > END
>
> > > > > > > Now for the software settings since I am using edk 9.2i, it d=
oes not
> > > > > > > have option for registering our interrupt handler in software=
platform
> > > > > > > settings window (which is what the lab suggests), I used the
> > > > > > > microblaze_register_handler(...) function ( I took me 3 days =
to figure
> > > > > > > out this), =A0but I still don't get how it works differently =
from the
> > > > > > > function XIntc_RegisterHandler.
> > > > > > > The portion of C file is as follows:
> > > > > > > void timer_int_handler(void * baseaddr_p) {
> > > > > > > =A0 =A0 /* Add variable declarations here */
> > > > > > > =A0 =A0unsigned int csr;
> > > > > > > =A0 =A0/* Read timer 0 CSR to see if it raised the interrupt =
*/
> > > > > > > =A0 =A0csr =3D XTmrCtr_mGetControlStatusReg(XPAR_DELAY_BASEAD=
DR,0);
> > > > > > > =A0 =A0/* If the interrupt occurred, then increment a counter=
*/
> > > > > > > =A0 =A0/* and set one_second_flag to 1 */
> > > > > > > =A0 =A0if (csr & XTC_CSR_INT_OCCURED_MASK ) {
>
> ...
>
> read more =BB- Hide quoted text -
>
> - Show quoted text -
Article: 136642paas <pabloalvarezsanchez@gmail.com> wrote: > On 24 nov, 18:31, John Doe <j...@usenetlove.invalid> wrote: >> palvarez <pabloalvarezsanchez gmail.com> wrote: >> > <snipped spam> >> > What do you think? >> >> I think you are just another Google Groups cross-posting spammer, >> especially considering this is your only post to USENET. > > I am just using google groups as I could have used any other news > reader. I do not know what is wrong with it. John Doe is a troll. Ignore him. I plonked him long ago. Your post is on-topic and valuable. Thanks for the heads up. Mike MonettArticle: 136643
I finish the verilog coding for a non-restoring divider based gate level. but I don't know how to pipeline it. Could anyone help me out. thanks a lot JaneArticle: 136644
On Thu, 27 Nov 2008 12:19:08 -0800 (PST), jinyinglu@gmail.com wrote: >I finish the verilog coding for a non-restoring divider based gate >level. but I don't know how to pipeline it. Assuming you this is what you have: module divider(dividend, divisor, quotient); input ... dividend, divisor; output ... quotient; wire ... partial1 = f(dividend, divisor); ... wire partial2 = f(partial1, divisor); ... endmodule then you can just make partial remainders registers for pipeline: reg ... partial1, partial2, ...; always @(posedge clk) partial1 <= f(dividend, divisor); always @(posedge clk) partial2 <= f(partial2, divisor); Of course you have to remember to calculate the individual bits of the quotient correctly based on your delayed partial remainders. Hope this helps. Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.comArticle: 136645
On Nov 27, 1:32=A0pm, Muzaffer Kal <k...@dspia.com> wrote: > On Thu, 27 Nov 2008 12:19:08 -0800 (PST), jinyin...@gmail.com wrote: > >I finish the verilog coding for a non-restoring divider based gate > >level. but I don't know how to pipeline it. > > Assuming you this is what you have: > > module divider(dividend, divisor, quotient); > > input ... dividend, divisor; > output ... quotient; > > wire ... partial1 =3D f(dividend, divisor); > ... > > wire partial2 =3D f(partial1, divisor); > ... > endmodule > > then you can just make partial remainders registers for pipeline: > > reg ... partial1, partial2, ...; > > always @(posedge clk) > =A0 =A0partial1 <=3D f(dividend, divisor); > > always @(posedge clk) > =A0 =A0partial2 <=3D f(partial2, divisor); > > Of course you have to remember to calculate the individual bits of the > quotient correctly based on your delayed partial remainders. > > Hope this helps. > > Muzaffer Kal > > DSPIA INC. > ASIC/FPGA Design Serviceshttp://www.dspia.com Let me try. Thanks a lot. happy thanks giving.Article: 136646
On Nov 27, 10:28=A0pm, Uwe Bonnes <b...@elektron.ikp.physik.tu- darmstadt.de> wrote: > Sudhir.Si...@email.com wrote: > > Hi Guys, > > I am trying to figure out a way to infer dual port ROM using BRAM on > > Xilinx FPGAs. Documentation shows how to infer single port ROMs but > > couldn't find any info on dual port. > > Any info on this will be greatly appreciaied. > > A look in .../Xilinx/10.1/ISE/doc/usenglish/books/docs/xst/xst.pdf might > also help. =A0 > > -- > Uwe Bonnes =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0b...@elektron.ikp.physik.tu-dar= mstadt.de > > Institut fuer Kernphysik =A0Schlossgartenstrasse 9 =A064289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- Thanks for your help guys. Cheers SudhirArticle: 136647
Hi, I want to dither rgb-video signals with a Lattice ECP2 FPGA and I don't have any idea how I should do this. Can you give me some tips for this problem. Is there are a free ip-core available? Thank you for your answer. bye martin sauerArticle: 136648
On 24 Nov, 16:34, palvarez <pabloalvarezsanc...@gmail.com> wrote: > Hi, > > Have you had a look at the new FMC standard (VITA 57)? It looks > extremely promising as nowadays many designs are based on a simple > FPGA with variations on the front pannel. =A0Sofar I have only seen FMC > developments for high perfomance plataforms based on Virtex5, but I > feel that a great benefit would appear when using a flexible low > budget carrier with flexible low cost front pannels. > > Check this article for quick intro to VITA 57 > > http://www.vmecritical.com/articles/id/?3575 > > What do you think? > > Cheers > > pablo You can get the pinout from Xilinx, they use it on a dev board. However, I've been trying to get the proper spec from VITA for ages but it hasn't been formerly released yet. Presumably VMETRO & Xilinx are VITA members and have a pre-release. ColinArticle: 136649
Hello,
The only way I've found to infer a dual ROM memory is to describe a
dual RAM memory. Write Enable signal is a port of the entity and
connect to '0' at the upper level. I've already informed Xilinx about
this problem but I've got no answer.
Anyway, it's a great advantage to have dual ROM memory : simply divide
the number of Block RAM by 2 !
Best regards
ibrary ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Dual_Block_ROM is
port(XGSR : in std_logic;
CLK : in std_logic;
WE_Null : in std_logic;
Adr : in std_logic_vector(19 downto 0);
Dout : out std_logic_vector(19 downto 0));
end Dual_Block_ROM;
architecture BEHV of Dual_Block_ROM is
type Tab_std_vector10 is array (integer range <>) of
std_logic_vector(9 downto 0);
signal Tab_ROM : Tab_std_vector10(0 to 1023):=
("0000000011","0010000110"," ...
");
signal Dout_ROM : std_logic_vector(19 downto 0);
begin
g_Dual_ROM: for i in 0 to 1 generate
Dout_ROM_proc: process(CLK)
begin
if rising_edge(CLK) then
if (WE_Null='1') then -- Unused
Tab_ROM(To_Integer(unsigned(std_logic_vector'(Adr(10*i+9
downto 10*i))))) <= (others => '0');
end if;
Dout_ROM(10*i+9 downto 10*i) <= Tab_ROM(To_Integer(unsigned
(std_logic_vector'(Adr(10*i+9 downto 10*i)))));
end if;
end process Dout_ROM_proc;
end generate g_Dual_ROM;
Dout_proc: process(XGSR,CLK)
begin
if (XGSR='1') then
Dout <= (others => '0');
elsif rising_edge(CLK) then
Dout <= Dout_ROM;
end if;
end process Dout_proc;
end BEHV;
...
entity Top_Dual_Block_ROM is
port(XGSR : in std_logic;
CLK : in std_logic;
Adra : in std_logic_vector(19 downto 0);
Douta : out std_logic_vector(19 downto 0));
end Top_Dual_Block_ROM;
architecture BEHV of Top_Dual_Block_ROM is
component Dual_Block_ROM
port(XGSR : in std_logic;
...
begin
C_Dual_Block_ROM: Dual_Block_ROM
port map(
XGSR => XGSR,
WE_Null => '0',
CLK => CLK,
Adr => Adra,
Dout => Douta);
end BEHV;
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