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Thanks for the response. I have already come across that article. What I am looking for is how do I start working on it once i figure out the basics. For example to learn C++ i need C++ tutorials, a C compiler and a computer. similarly what all is required to get started on this. Also what all can I get for free. Will Hua Zheng suggested some simulation tools to learn verilog. Do I also need any hardware? thanksArticle: 85001
Hi Lina, I assume you're using an evaluation board. Which one? BCDArticle: 85002
xenos wrote:
> For example to learn C++ i need C++ tutorials, a C compiler and
> a computer. similarly what all is required to get started on this. Also
> what all can I get for free. Will Hua Zheng suggested some simulation
> tools to learn verilog. Do I also need any hardware? thanks
You only need an editor and simulator to get started.
Once you know how to write and simulate HDL code for
synthesis, you can try it out on hardware.
Until then, all you can do with hardware
is run the canned demos and flash the LEDs.
-- Mike Treseler
Article: 85003xenos wrote: > Thanks for the response. I have already come across that article. What > I am looking for is how do I start working on it once i figure out the > basics. For example to learn C++ i need C++ tutorials, a C compiler and > a computer. similarly what all is required to get started on this. Also > what all can I get for free. Will Hua Zheng suggested some simulation > tools to learn verilog. Do I also need any hardware? thanks > You don't need hardware to learn HDL. Cver + GTKWave will simulate most logic.Article: 85004
xenos wrote: > Thanks for the info. But I had a question and pardon my ignorance here. > Some one also suggested that I buy Xilinx Spartan 3 kit and free > WebPack > software. What is the use of that? Is that used to actually program > FPGA chip? As far as I understand i can use the tools you suggested to > practise simulations and then go towards the hardware to program the > chips. > The Spartan 3 kit comes with a prototyping board with a Spartan 3 FPGA. The software that comes with the kit lets you synthesize your design into the FPGA on the board. You should definitely get something like that if you want to get a feel of what the logic you wrote can do in real hardware. And you are right, you can practice with simulation tools first (this lets you see the inner-workings of your design, not just the output).Article: 85005
Joe wrote: > Hi Folks, > > Any inputs regarding interfacing USB1.1 with ARM Core(7TDMI) > using AMBA AHB/APB 2.0 Specification?? Your help will be greatly > appreciated. Please take a look at our USB IP Cores as well (www.asics.ws), we have USB 1.1 and USB 2.0 Device and OTG IP Cores. All of our IPs support AHB, OPB, AVALON, PLB, OCP, WISHBONE and many custom buses as well. Best Regards, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and SynthesisArticle: 85006
> Suppose I have an AC power system, and I can digitize a pair of > voltage and current waveforms. I want to report everything: trms > volts/amps, true power, reactive power, phase angle. The line > frequency could vary from maybe 20 to 80 Hz for a stationary > generator, or 200-800 for an aircraft system (including startup and > weird situations.) I'll digitize to 16 bits, at maybe 20K > samples/second or something. I'm considering doing all the signal > processing in an FPGA, crunching maybe 8 voltage+current pairs. > > For the rms volts/amps, we could just square the samples, filter, and > allow my pokey uP to occasionally pick up that and square root. > > True power is just the product of the e*i samples, lowpass filtered. > Easy. > > What's tricky is the reactive power/phase angle thing. reactive power is defined: reactive power = squareroot (apparent power ^2 - true power ^2) cos phi = true power / apparent power reactive power = sin phi * apparent power This was done in this way because if voltage and current are not purely sinusoidal, the reactive power contains power products of harmonics. They cannot be calculated using the hilbert transform of the fundamental only. Reactive power is the square root of the square sums of fundamental rp, reactive products of equal harmonics, and products of unequal harmonics. Reactive products of equal harmonics are products of equal harmonics with integral zero ( i.e. harmonic reactive power). The time integrals of nonequal harmonics products are always zero. This is called distortion power, but its is a part of the reactive power. True power is the square root of the square sums of fundamental real power and real products of equal harmonics. This is the same as your > True power is just the product of the e*i samples, lowpass filtered Most important is to use a sampling rate which is high enough to saisfy Nyquist's theorem. A sampling frequency 100* line frequency may be a starting point, but *1000 or above may be necessary. hope this can help to simplify your problem! regards ...gerhardArticle: 85007
CD-ROM's are so 90's "Jedi" <me@aol.com> wrote in message news:lFDne.179$YR2.156@read3.inet.fi... > So for how long is NIOS2 5.0 out? > > Just received today my NIOS2 1.1 upgrade... > Unbelievable fast they are (o; > > > /jedi >Article: 85008
fpga00@gmail.com wrote:
> Hi,
> I am receiving some data from the uart.I take it and keep it in
> memory using a pointer.I use the following condition in my code:
> while (!XUartLite_mIsReceiveEmpty(XPAR_RS232_UART_BASEADDR))
> {
> *uart2ram=XUartLite_RecvByte(XPAR_RS232_UART_BASEADDR);
> uart2ram++;
>
> }
> then i have to do some processing on the data stored in the memory.I
> intend to do that after i receive the complete frame of data from uart.
> Now what happens is that the uart takes the first byte puts it in the
> memory and comes out of the interrupt handler.then goes back again and
> receives the rest of the data.I am not able to figure out y is it
> coming out of the handler after taking jsut one byte.shouldnt it take
> all the bytes from uart,store it in the ram?
> please give some suggestions if you guys can think about any thing that
> i am missing.
> thanx...
It looks like the code should work, but you need to be sure that
the interrupt only comes when there is a complete "frame". If the
interrupt happens whenever the uart isn't empty, you'll get exactly
the behavior you describe.
Article: 85009On Thu, 2 Jun 2005 22:18:30 +0200, "new.online.de" <birkelg@computer.corg> wrote: > >> Suppose I have an AC power system, and I can digitize a pair of >> voltage and current waveforms. I want to report everything: trms >> volts/amps, true power, reactive power, phase angle. The line >> frequency could vary from maybe 20 to 80 Hz for a stationary >> generator, or 200-800 for an aircraft system (including startup and >> weird situations.) I'll digitize to 16 bits, at maybe 20K >> samples/second or something. I'm considering doing all the signal >> processing in an FPGA, crunching maybe 8 voltage+current pairs. >> >> For the rms volts/amps, we could just square the samples, filter, and >> allow my pokey uP to occasionally pick up that and square root. >> >> True power is just the product of the e*i samples, lowpass filtered. >> Easy. >> >> What's tricky is the reactive power/phase angle thing. > >reactive power is defined: > >reactive power = squareroot (apparent power ^2 - true power ^2) >cos phi = true power / apparent power >reactive power = sin phi * apparent power > >This was done in this way because if voltage and current are not purely >sinusoidal, the reactive power >contains power products of harmonics. They cannot be calculated using the >hilbert transform of the fundamental only. In most ac power systems, the voltage waveform is reasonably sinusoidal, so I can get away with defining reactive power as the averaged product of current * (90 degree shifted voltage) waveforms. (A good Hilbert shifts all frequencies 90 degrees!) But I do need the phase angle. Arc-cos is ambiguous. >Reactive power is the square root of the square sums of fundamental rp, >reactive products of equal harmonics, and products of unequal harmonics. >Reactive products of equal harmonics are products of equal harmonics with >integral zero ( i.e. harmonic reactive power). >The time integrals of nonequal harmonics products are always zero. This is >called distortion power, but its is a part of the reactive power. > >True power is the square root of the square sums of fundamental real power >and real products of equal harmonics. This is the same as your >> True power is just the product of the e*i samples, lowpass filtered > >Most important is to use a sampling rate which is high enough to saisfy >Nyquist's theorem. A sampling frequency 100* line frequency may be a >starting point, but *1000 or above may be necessary. > Actually, no. Nyquist is irrelevant: we're not trying to reconstruct the waveform, but merely gather statistics on it. One can make a very nice, accurate power meter that samples at a fraction of the line frequency. JohnArticle: 85010
Hello John, > Actually, no. Nyquist is irrelevant: we're not trying to reconstruct > the waveform, but merely gather statistics on it. One can make a very > nice, accurate power meter that samples at a fraction of the line > frequency. As long as the goal isn't to meter cheap printers. Their cheap-as-can-be "power supplies" sound like a moped with fouled spark plugs and their current plot looks like 4th of July fireworks ;-) Regards, Joerg http://www.analogconsultants.comArticle: 85011
Joerg wrote: > Hello John, > >> Actually, no. Nyquist is irrelevant: we're not trying to reconstruct >> the waveform, but merely gather statistics on it. One can make a very >> nice, accurate power meter that samples at a fraction of the line >> frequency. > > > As long as the goal isn't to meter cheap printers. Their cheap-as-can-be > "power supplies" sound like a moped with fouled spark plugs and their > current plot looks like 4th of July fireworks ;-) > > Regards, Joerg ROTFLMAO! dont beat about the bush Joerg, tell us what you really think. Cheers TerryArticle: 85012
On Thu, 02 Jun 2005 21:11:27 GMT, Joerg <notthisjoergsch@removethispacbell.net> wrote: >Hello John, > >> Actually, no. Nyquist is irrelevant: we're not trying to reconstruct >> the waveform, but merely gather statistics on it. One can make a very >> nice, accurate power meter that samples at a fraction of the line >> frequency. > >As long as the goal isn't to meter cheap printers. Their cheap-as-can-be >"power supplies" sound like a moped with fouled spark plugs and their >current plot looks like 4th of July fireworks ;-) > But longterm, you'll still get the right number of KWHs! JohnArticle: 85013
Hello John, >>As long as the goal isn't to meter cheap printers. Their cheap-as-can-be >>"power supplies" sound like a moped with fouled spark plugs and their >>current plot looks like 4th of July fireworks ;-) > > But longterm, you'll still get the right number of KWHs! Yes, although it could be very long term if they are constantly printing something. Regards, Joerg http://www.analogconsultants.comArticle: 85014
Hello Terry, > ROTFLMAO! dont beat about the bush Joerg, tell us what you really think. No hidden agendas here. Seriously, I have a new printer where the power supply sounds like a Madagascan hissing cockroach, the scope won't sync on anything when checking the current intake and the topper was that it was able to swamp the X10 signal in that area. These signals were a whopping 3V. I wonder how it ever passed the smog check. It needed two Dollar-sized toroids just to make X10 work again. Regards, Joerg http://www.analogconsultants.comArticle: 85015
John Larkin wrote: [...] > In most ac power systems, the voltage waveform is reasonably > sinusoidal, so I can get away with defining reactive power as the > averaged product of current * (90 degree shifted voltage) waveforms. > (A good Hilbert shifts all frequencies 90 degrees!) You don't even need it. Just lock a DDS or pll to 360 times the line frequency to drive the ADC's. You can get a 90 degree shift by looking 90 clocks ahead (or behind) in memory. You can multiply the actual ADC values and not have to apologize for approximations. This also gives the phase relations needed to handle 3-phase power. > But I do need the phase angle. Arc-cos is ambiguous. When you average the reactive power, capacitive and inductive loads give the opposite average values. So you automatically get the right answer. Averaging also helps eliminate noise in the current waveform and improves accuracy. You can change the average in software to suit conditions. [...] > >Most important is to use a sampling rate which is high enough to saisfy > >Nyquist's theorem. A sampling frequency 100* line frequency may be a > >starting point, but *1000 or above may be necessary. > Actually, no. Nyquist is irrelevant: we're not trying to reconstruct > the waveform, but merely gather statistics on it. One can make a very > nice, accurate power meter that samples at a fraction of the line > frequency. Yes, but you have to average for a very long time. You can provide much faster response to changing conditions by using a faster clock. This may be significant when debugging 400Hz a/c power systems during engine start, for example. Silicon and software are cheap, and will be even cheaper in the future. You can add a lot of benefit for the user with a very small increase in cost. A clock at 360X the line frequency should give plenty of resolution. It is not unreasonably high for a 16-bit ADC at 400Hz. The nice thing about using sine and cosine is the narrow current pulses from a rectifier in a power supply only affect the real power average. I was pleasantly surprised to find the pulses occur at the zero crossings for the reactive part, so they average to zero and have minimal affect on the result. I have some SPICE plots that show this and could post them if you like. > John Mike MonettArticle: 85016
The Virtex-4 lib manual suggests that the Architecture Wizard should be used, however I can't see how... The Virtex-4 RocketIO Guide doesn't seem to have this information either... Thanks, /MikhailArticle: 85017
I found that they actually had an option of instantiating the GT11CLK in some earlier version of the Architecture Wizard (http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&g etPagePath=17415), but it has been deleted in 7.1... Not very helpful... /MikhailArticle: 85018
I'm working on a simple ide interface to a spartan 3 fpga. I've gone over the ata specs and online projects and I keep getting stuck. All I am trying to do right now is read the status register and I can't get back anything that makes sense. All the fpga does is set the CS and address lines, pulse the Dior and before the pulse drops copies what is on the data line to a register. I have 4 older drives I'm working with, an old 730mb, a 650mb, a 4.3 gb which are not compatible with anything more than ata-3, and a 6.4gb which is ata-5 compatible. The outputs from the fpga are wired directly to the hard drive, i figured this was okay because I saw a few projects do it but my data lines would always seem on so I terminated them with a 10k ohm resistor to ground. The smallest drives give me back nothing, the 6.4gb gives back 0111 1110 and 0000 0000 on the error register. The spartan 3 is outputting 3.3v, so are the other drives needing 5v even though specs only say it needs greater than 2.4v on the lines, or is the 6.4gb drive broken. I keep testing all drives in my desktop and they seem fine. I know its hard to go on what I just explained, and I've been over time stuff on the ata specs a lot and they seem to fall into spec so Is this likely a voltage problem? I would apperciate any help anyone could give me. Thank you in advanceArticle: 85019
Jedi wrote: > So for how long is NIOS2 5.0 out? > > Just received today my NIOS2 1.1 upgrade... > Unbelievable fast they are (o; > > > /jedi Jedi, Nios II 5.0 has been out for a few weeks now and I have seen shipping packages that include Quartus II 5.0 & Nios II 5.0. The fact that you just got v1.1 indicates something is seriously wrong. This may be a moot point, but is your Nios subscription still valid? If so, I suggest three things: (1) Download the Nios II 5.0 evaluation tools from www.altera.com -- The evaluation edition does not include the Micrium RTOS but everything else is there. (2) Contact Altera Customer Service (non-technical-support) which handles these issues at (800) 767-3753 and explain the situation. (3) If that doesn't work or you cannot call them (I cannot find an email address for them immediately), please send me an email with your contact name/address/company and I will contact customer service for you. Jesse Kempa Altera jkempa -at- altera -dot- comArticle: 85020
Hi Ed, Could u please tell me how o use tri-mode-ethernet MACs embedded in Virtex 4 FX12 for Ethernet application. Is there any reference design available that uses only embedded MACs but not Gigabit MAC(I suppose that needs licence and given in ML403 reference design). Thank in advance with regards RajeshArticle: 85021
xenos wrote: > Thanks for the info. But I had a question and pardon my ignorance here. > Some one also suggested that I buy Xilinx Spartan 3 kit and free > WebPack > software. What is the use of that? Is that used to actually program > FPGA chip? As far as I understand i can use the tools you suggested to > practise simulations and then go towards the hardware to program the > chips. > The steps are Create the design: 1) edit design source files 2) create test bench files - these files simulate other parts of the system your FPGA goes in, provide stimulus. For trivial designs, the you might get away without testbench and just use the simulator to apply stimulus. 3) simulate your design in the testbench environment. Go back to step 1 until it appears to work right. The simulator is seldom provided for free by the fpga vendor, although xilinx supplies a free but hobbled version of modelsim, which is very good. 4) use a logic synthesizer to convert your design source files into a structural/schematic implementation of the logic. This tool is usually supplied by the vendor, but sometimes 3rd party tools are even better. 5) use place and route tools to map the schematic onto the cells of a particular fpga. Timing constraints tell the tool how fast your design must be. This tool is always supplied by the fpga vendor. 6) after verifying that timing constraints were met, load the results of 5 into the fpga, watch the blinkenlights. Most fpga vendors provide free gui type programs that tie all these things together. You can run all the tools from command line also. I prefer doing steps 1-3 "stand alone". There are some cases where simulation is called for after step 4 and 5, but that is rare for simpler designs.Article: 85022
Average frequency resolution is trivial with DDS. I recently built a box that generates 1 Hz to 640 MHz in 1 Hz increments ( and 1 mHz would have meant just another ten stages in the accumulator.) The issue is jitter and stability or "wander". The DDS gives you a whole clock period of systematic and deterministic jitter. So that's a couple of nanoseconds plus the original clock jitter plus DCM jitter. Then you can play all sorts of tricks to reduce the jitter, but don't expect to get below 50 ps of cycle-to-cycle jitter for any adjustable frequency. (Fixed frequency generators with high-Q resonators are a different thing) Agilent can barely get below 40 ps, and they have 60+ years of experience, and charge thousands of dollars... Then figure out the instantaneous frequency stability: 50 ps @ 100 MHz = 50 parts in 10,000 = 1 part in 200 = 500 kHz "sidebands". Things get really ugly when you move between the frequency and the time domain. :-( Peter Alfke, Xilinx Applications Falk Brunner wrote: > "John_H" <johnhandwork@mail.com> schrieb im Newsbeitrag > news:tPDne.35062$GN3.17984@trnddc04... > > > > I need to generate 35.328 MHz clock > > > > > > I have an external xtal of 35.328 MHz feeding to FPGA. > > > > > > From this clock i need to generate 35.328 MHz square wave with fine > resolution. > > > > > > We need a resolution of 1Hz, that means i should be able to change the > square wave out put frequency by 1 Hz resolution. > > Hmm, how about using a cheap VCO based PLL (ala 4046) and a DDS (inside the > FPGA) generating lets say 3.5328 MHz. Multiply the 35.328 by four. Run the > DDS at this frequency, a 32 bit accu will give a resolution of 0,03 Hz. Use > the analog PLL to multiply by ten. This way your frequency resolution is > degraded to 0,3 Hz, but this sounds enough for your application. If the loop > filter is designed properly the broadband/high frequency jitter is filtered > out. > > Regards > FalkArticle: 85023
On Thu, 02 Jun 2005 04:40:46 -0700, praveenkumar1979 wrote: > Hi Guys, > > Is there another standard of PCI for master? i think of this because i > have observed that clock trace > in the motherboard of personal computer from noth bridge to 3th slot of > PCI connector is more than 2.5 inches. > We are designing an PCI master in one of our design. > > Thanks and regards > Praveen If you are designing a PCI system, I suggest you get a book on the PCI standard, or get the standard itself from the PCI SIG. The clocks which go from the host board to the PCI slots are supposed to be matched in length and under some maximum, IIRC. They can actually be pretty long (12" or more) and still work at 33 MHz, but they are supposed to be matched in length. --MacArticle: 85024
On Tue, 31 May 2005 17:20:07 -0700, John Larkin wrote: > Hi, > > Can anybody recommend a book that has good stuff about implementing > the discrete Hilbert transform, preferably in an FPGA? I need > practical stuff, like accuracy over frequency ranges for given tap > count, windowing, truncation effects, etc. > > I need to take a stream of digitized (16 bit) analog samples and > produce an I-Q data stream pair over roughly a 20:1 frequency range, > to maybe 1 degree accuracy. Max signal frequency will be low, 1 KHz > maybe. > > Any other resource tips would be appreciated. We could pay for a bit > of consulting maybe, too. > > Thanks, > > John It seems like it would be more cost effective and easier to do this using a DSP. The Hilbert transform of a real-valued signal is as easy as two FFT's, basically, and DSP's are good at FFT's. In any event, Xilinx has tons of notes about doing FFT's and convolution and correlation and so on on their website. --Mac
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