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jjlindula@hotmail.com wrote: > Hello, I'm looking for some information that describes some of the best > practices or habits for successful electronic design or embedded > design. I'm trying to convince some co-workers that it is important to > document their work and follow standards in their designs. Some of my > co-workers are very fast designers and are respected by their peers, > but in their rush to get the design done they often ignore standards > and don't document their work, such as in their schematics or in their > FPGA code. I feel these habits and behavior actually wastes money, by > that I mean that if someone has to take their undocumented work, they > won't know what is going on. I realize that I might not be able to > change more senior engineers, but I might be able to leave an > impression on the newer engineers. If anyone knows of some habits or a > list of some best practices that make a successful design, please pass > them onto me. Most of these habits I would assume fall into proper > system engineering. > > thanks, > joe If the designs are 1) going to be reused or 2) need to be interfaced with other engineers such as dedicated verification engineers for formal verification, then the appropriate documentation and standards are appropriate. However, if the design is a single-point solution and will not be reused there *will* be significant waste in getting the code "pretty" enough for someone else to use. A good engineer can parse through HDL and understand the flow of the modules with minor comments. The time to get the understanding is typically less than the time needed to generate documentation in the first place. Once. If the code has to be perused more than once, the payback starts to come in. For huge code or schematics, documentation is a sincere help. If a Verilog module is used for some glue logic, typically the great dissertations on what the individual elements are up to isn't necessary. So it's not clear but depends more on the product, the design environment, the support requirements (1 year? 20 years?) and to some extent the turnover rate in the engineering group. If Charlie will always be around, he can always help when his code needs tweaking. If Charlie's expected to move on in a year and the code has a long support lifespan, something's needed.Article: 85601
The standards for any piece of software are the same regardless of what they are compiled to do. The technique you use depends on how you are brought up and what company policy is but every variable or group of variables should be described in one line same with process (function calls) It is also incredibly important to document exceptions well... if there is something unusual to be handled, then the description should explain the fault, how it is created and what the fixup is. This is more so for hardware than software as real life timings are involved. Hardware should also document interactions between modules... makes it easier to identify triggers especially in state machines. The idea is to make sure the next person to work on the design understands what is happening.. this can mean the difference between spending a week going thru a design and a month or more. Simon "JJ" <johnjakson@yahoo.com> wrote in message news:1118530886.298739.256360@o13g2000cwo.googlegroups.com... > > Perhaps you need the "Synopsys Design Reuse Style Guide". >Article: 85602
I would be a little wary of dual cores at the moment http://www.tomshardware.com/index.html has been stress testing an Intel and AMD system lately.. 5 motherboards, a ram and a FAN all replaced in an Intel System. I personally would wait until the power drops below 100Watts to make sure the system would cope or buy a good name brand. the AMD system seems to be going well however. I also thing a dual Pentium-M around 2G would leave the Pentium 4 in its dust and be cool and quite... shouldn't be too far away. But if your serious about high end.. get away from Intel its the slowest system out there. I would be seriously looking at Spark or what ever else the manufacturers support as an alternative, The Intel Architecture is rather old and full of compromise. I also don't think your system is so bad.. I still use just a hyperthread 2.8G P4 with 512 Megs RAM :-) and I enjoy the coffee breaks. Simon "Jim Granville" <no.spam@designtools.co.nz> wrote in message news:42aa848c$1@clear.net.nz... > Ray Andraka wrote: > > Time has come for a computer upgrade (I'm currently using a dual Athlon > > 1.8GHz with 4GB memory and 15000RPM scsi raid array running Win2K, > > matrox dual head video with a pair of 19" monitors), but I haven't kept > > up at all with the computer market. I'm wondering what people are using > > these days for high end designs (for simulation and PAR especially). > > I'd like something that doesn't sound like a vacuum cleaner and heat the > > room like a space heater this time around too, perhaps I need to > > consider liquid cooling? ANy comments would be appreciated. Yes, I > > admit I am being lazy. > > Dual core chips are the latest 'hot thing', so you might want to track > that, and decide if they are mature enough to move to, or wait a few > months. ie right now, with both 64 bit and Dual core as recent crests, > is not an ideal time to expect rock solid systems. If you do not HAVE to > move asap, I'd wait a few months. > AMD do claim to be on schedule for 65nm in 2006 :) > -jg > >Article: 85603
On Fri, 10 Jun 2005 11:51:02 -0400, Ray Andraka wrote: > Time has come for a computer upgrade (I'm currently using a dual Athlon > 1.8GHz with 4GB memory and 15000RPM scsi raid array running Win2K, > matrox dual head video with a pair of 19" monitors), but I haven't kept > up at all with the computer market. I'm wondering what people are using > these days for high end designs (for simulation and PAR especially). > I'd like something that doesn't sound like a vacuum cleaner and heat the > room like a space heater this time around too, perhaps I need to > consider liquid cooling? ANy comments would be appreciated. Yes, I > admit I am being lazy. The dual core Athlon 64 should be available in a few weeks, thats the machine to go for. The most important thing is cache size not clock speed. There are four A64 X2s, a 2.2GHz 1/2M Cache version, a 2.2GHz 1M cache version, a 2.4 GHz 1/2M cache version and a 2.4GHz 1M cache version. The one you want is the 2.2GHz 1M cache version, it's much cheaper then either of the 2.4GHz models and it will run rings around the 2.4GHz 1/2M cache part. I have two A64 machines, a 3400+ which is 2.2GHz 1M Cache, 754 pin, and a 3800+ which is 2.4 GHz 1/2M cache, 939 pin. The 3400+ is twice as fast as the 3800+ running NCverilog. I did a bunch of benchmarks a couple of months ago, here are the results, http://www.polybus.com/linux_hardware/index.htmArticle: 85604
Hello! Does anyone know where I can get the symbol for an XC2VP30-FF896 part? I use OrCAD. Many thanks, RobertArticle: 85605
On 11 Jun 2005 15:03:31 -0700, "jjlindula@hotmail.com" <jjlindula@hotmail.com> wrote: >Hello, I'm looking for some information that describes some of the best >practices or habits for successful electronic design or embedded >design. I'm trying to convince some co-workers that it is important to >document their work and follow standards in their designs. Some of my >co-workers are very fast designers and are respected by their peers, >but in their rush to get the design done they often ignore standards >and don't document their work, such as in their schematics or in their >FPGA code. I feel these habits and behavior actually wastes money, by >that I mean that if someone has to take their undocumented work, they >won't know what is going on. I realize that I might not be able to >change more senior engineers, but I might be able to leave an >impression on the newer engineers. If anyone knows of some habits or a >list of some best practices that make a successful design, please pass >them onto me. Most of these habits I would assume fall into proper >system engineering. > >thanks, >joe Do the three things that nobody teaches and almost nobody does: Comment, comment, and comment. JohnArticle: 85606
Hi Rob, > Does anyone know where I can get the symbol for an XC2VP30-FF896 part? I > use OrCAD. Sorry, but I've never really understood the thinking behind asking this type of question. As a note, it seems like this same question is asked by more OrCAD users than any other schematic capture package. The reason I don't understand this, is that I don't understand how one can use a generic symbol, or a symbol someone else made for their design, for a part that has 896 pins (or even 300+ pins)? Wouldn't you want to treat parts like this as 1) Heterogeneous...as in, has multiple symbol bodes, and 2) where each body is a function of YOUR design, not someone else's, and not generic (like per bank or something like that)? Personally, I treat these parts like ASICs, where I use multiple symbol bodies, one for each functional block. That way the design is easily understood, and signals for a specific function can be contained on a single page. For example, PCI interface, 1 symbol. DDR interface, one symbol used multiple times, configuration interface symbol, and a power symbol per bank, and one for VCCAUX & VCCINT (fixed voltages). The later symbols could be "generic" enough, but the former, again, better done for your design IMO. So, I guess, my suggestion is for you to make your own individual symbol bodies that are specific for the functions of your design. If you're asking for one as a starting point, that makes sense...but...sorry, I can't help you there, I use ViewDraw and Concept ;-) Regards, AustinArticle: 85607
Austin: Yes, I would treat the part as hetrogenous, of course. I would think everyone would have to do that otherwise you would have a part so big that it would be unreasonable to work with. I would also think that others would build the part by function: power/grnds, diff I/O, I/O, configuration, etc. Actually, much like you have listed below. If you build these types of parts by function it will pretty much suffice for most designs. The large FPGA's that I have built were done in this fashion and I've used them for different projects. I would think if somebody had this Xilinx part built that it would be segregated in a logical fashion and work fine for me. Furthermore, it would save me MUCH time in building. Obsurd schedules made by unsympathetic management sometimes pushes one to look for ALL the help they can get. Cheers, Robert "Austin Franklin" <austin@dark99room.com> wrote in message news:vQNqe.18677$mZ2.17616@fe07.lga... > Hi Rob, > >> Does anyone know where I can get the symbol for an XC2VP30-FF896 part? I >> use OrCAD. > > Sorry, but I've never really understood the thinking behind asking this > type > of question. As a note, it seems like this same question is asked by more > OrCAD users than any other schematic capture package. > > The reason I don't understand this, is that I don't understand how one can > use a generic symbol, or a symbol someone else made for their design, for > a > part that has 896 pins (or even 300+ pins)? Wouldn't you want to treat > parts like this as 1) Heterogeneous...as in, has multiple symbol bodes, > and > 2) where each body is a function of YOUR design, not someone else's, and > not > generic (like per bank or something like that)? > > Personally, I treat these parts like ASICs, where I use multiple symbol > bodies, one for each functional block. That way the design is easily > understood, and signals for a specific function can be contained on a > single > page. For example, PCI interface, 1 symbol. DDR interface, one symbol > used > multiple times, configuration interface symbol, and a power symbol per > bank, > and one for VCCAUX & VCCINT (fixed voltages). The later symbols could be > "generic" enough, but the former, again, better done for your design IMO. > > So, I guess, my suggestion is for you to make your own individual symbol > bodies that are specific for the functions of your design. If you're > asking > for one as a starting point, that makes sense...but...sorry, I can't help > you there, I use ViewDraw and Concept ;-) > > Regards, > > Austin > >Article: 85608
Austin Franklin wrote: > Hi Rob, > > > Does anyone know where I can get the symbol for an XC2VP30-FF896 part? I > > use OrCAD. > [...] > The reason I don't understand this, is that I don't understand how one can > use a generic symbol, or a symbol someone else made for their design, for a > part that has 896 pins (or even 300+ pins)? Wouldn't you want to treat > parts like this as 1) Heterogeneous...as in, has multiple symbol bodes, and > 2) where each body is a function of YOUR design, not someone else's, and not > generic (like per bank or something like that)? Howdy Austin, So when you use that same part for additional designs, you'd rather spend the effort to do a unique 500 or 900 pin symbol for each of those designs rather than making it generic (per bank) to begin with so it only has to be done once? Sounds like a significant amount of extra work. Regards, MarcArticle: 85609
Hi Rob, > I would also think that others would build the part by function: > power/grnds, diff I/O, I/O, configuration, etc. Actually, much like you > have listed below. ...well, except for diffI/O and I/O...those are by function, and completely configurable. So, yes, you can "generic-ized" power/gnd and configuration symbols. That leaves a good %70 of the pins non-generic. Using generic symbols for these I/O banks, to me, seems, well, unusable (not my first choice of words) for such a large part due to fact it will poorly document the design, and make for a poor schematic (signals all over the place). A lot changes on these BGAs for PCB routing and internal FPGA timing reasons, as the bondout means you can't necessarily use seemingly adjacent pins. > If you build these types of parts by function it will > pretty much suffice for most designs. The large FPGA's that I have built > were done in this fashion and I've used them for different projects. In the hundred or so FPGAs that I've designed, I've never had one that was exactly the same...I've reused sections, like PCI interfaces, SDRAM, DDR, CameraLink, Configuration...of course. Without knowing what your functions are, it I think it would be hard for someone to offer you any symbols that would work for you. I guess what I'm trying to say is you may not find what you are looking for, and if you do, it may not be what you really want. Just MNASHO. It takes me a number of hours to make a new FPGA or ASIC symbol, and I get exactly what it is I want. I thought OrCAD was purported to be easier than most other schematic capture programs to create symbols in? I used it a number of years ago, and found I didn't like it...but was told I just wasn't good with it, which was true enough...but OrCAD still seemed obtuse to me. Regards, AustinArticle: 85610
jjlindula@hotmail.com wrote: > Hello, I'm looking for some information that describes some of the best > practices or habits for successful electronic design or embedded > design. I'm trying to convince some co-workers that it is important to > document their work and follow standards in their designs. Some of my > co-workers are very fast designers and are respected by their peers, > but in their rush to get the design done they often ignore standards > and don't document their work, such as in their schematics or in their > FPGA code. I feel these habits and behavior actually wastes money, by > that I mean that if someone has to take their undocumented work, they > won't know what is going on. I realize that I might not be able to > change more senior engineers, but I might be able to leave an > impression on the newer engineers. If anyone knows of some habits or a > list of some best practices that make a successful design, please pass > them onto me. Most of these habits I would assume fall into proper > system engineering. You can get an improvement in this area, if you change what 'finished' means. To some, it is the first sign of a pulse, on the test bench :) If you make finished more precisely defined as a sign-off, that includes a verified schematic == HW, & true BOM, that solves the schematic/PCB side. Getting someone to follow standards in source code is more difficult but you can encourage this with a common template/form for source block headings, that everyone agrees on, and they need to fill out. A problem with mandates on comments, and style itself, is that can degenerate into nit-picking, and there are also the types that view clearer code as reduced job security! -jgArticle: 85611
Hi all, There is another question: Why Xilinx designed 18k ram? 18k isn't 2^n. How to seperate its address into "1XX...XX" and "0XX...XX"? Best regards, DavyArticle: 85612
"Davy" <zhushenli@gmail.com> schrieb im Newsbeitrag news:1118562757.483278.159870@g43g2000cwa.googlegroups.com... > Hi all, > > There is another question: Why Xilinx designed 18k ram? 18k isn't 2^n. > How to seperate its address into "1XX...XX" and "0XX...XX"? It has additional bit lanes for extra use, like parity, control, whatever. It can be configured as 16k x1 8k x 2 4k x 4 2k x 9 1k x 18 0.5k x 36 Regards FalkArticle: 85613
Hi Mr.Brunner, Thank you for your help! And if I want two 8k ram in one 18k ram, how to declear this situation? And can nine 2k or four 4k ram in one 18k ram be access at the same time? Best regards, DavyArticle: 85614
> And if I want two 8k ram in one 18k ram, how to declear this situation? 8k and 18k isnt a clean statement. How wide shall the RAMs be? 1 bit? 32 Bit? You can use CoreGen to get a full configured macro, fit to your settings. Or you can use the templates from the VHDL template wizard and wire them up on your own. > And can nine 2k or four 4k ram in one 18k ram be access at the same > time? ??? There are multiple RAM block inside the FPGA. every block can be accessed individually. Even more, since they are true dual ported, you can access each port on every BlockRAM individually. Regards FalkArticle: 85615
Hi all, It's intuitive to pipeline a feed-forward combinational logic. But how to pipeline the Loop without changing the timing? For example, when I insert a reg to feed-forward logic, shall I delete a reg in feedback logic at the same time? And if the datapath logic is a iteration one(Logic A -> Logic B -> Logic A -> Logic B ...)? How to do pipeline? Any suggestions will be appreciated! Best regards, DavyArticle: 85616
On 12 Jun 2005 02:47:14 -0700, "Davy" <zhushenli@gmail.com> wrote: >Hi all, > >It's intuitive to pipeline a feed-forward combinational logic. But how >to pipeline the Loop without changing the timing? > >For example, when I insert a reg to feed-forward logic, shall I delete >a reg in feedback logic at the same time? > >And if the datapath logic is a iteration one(Logic A -> Logic B -> >Logic A -> Logic B ...)? How to do pipeline? > >Any suggestions will be appreciated! > >Best regards, >Davy If by loop logic you mean feedback ie LMS adaptive FIR filter etc. then the answer is: very carefully. If you don't want the hardware to get very expensive you need to apply some relaxation to your pipeline calculations. You can look at the following book for some ideas: http://www.amazon.com/exec/obidos/tg/detail/-/0792394631/qid%3D1118570326/103-6481589-6671845Article: 85617
Hi,
Can anybody help with the situation described below?
I followed the best information I could find, but it doesn't work and I
would like some tips that could give me information on what goes wrong,
Thanks
Kris Heyrman.
--
kernel: kernel-2.6.11-1.27_FC3, compiled from src.rpm
compiler: gcc (GCC) 3.4.3 20050227 (Red Hat 3.4.3-22.fc3)
xps: Xilinx EDK 7.1.1 Build EDK_H.11.3
used guidelines from:
http://www.fpga-faq.org/FAQ_Pages/0044_Xilinx_Parallel_on_Linux.htm
but installed windrvr version 7.00 from www.jungo.com (WD700LN.tgz
instead of WD623LN.tgz), in which I believe Tyson Harding's fix from
3/18/2005 has been applied.
/etc/rc.local: wdreg windrvr6 yes
WinDriver v7.00 Jungo (c) 1997 - 2005 Build Date: Apr 26 2005 X86
loaded
With a Xilinx XUP Virtex-II PRO Development System,
trying to download Xilinx's Base System:
# lsusb
Bus 004 Device 001: ID 0000:0000
Bus 003 Device 002: ID 03fd:0009 Xilinx, Inc.
Bus 003 Device 001: ID 0000:0000
Bus 002 Device 001: ID 0000:0000
Bus 001 Device 001: ID 0000:0000
$ make -f system.make download
*********************************************
Downloading Bitstream onto the target board
*********************************************
impact -batch etc/download.cmd
Release 7.1.02i - iMPACT H.40
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
// *** BATCH CMD : setMode -bs
// *** BATCH CMD : setCable -port auto
AutoDetecting cable. Please wait.
Reusing 78020001 key.
Connecting to cable (Parallel Port - parport0).
WinDriver v7.00 Jungo (c) 1997 - 2005 Build Date: Apr 26 2005 X86
21:13:49.
parport0: baseAddress=0x378, ecpAddress=0x778
LPT base address = 0378h.
ECP base address = 0778h.
Cable connection failed.
Reusing 79020001 key.
Connecting to cable (Parallel Port - parport1).
WinDriver v7.00 Jungo (c) 1997 - 2005 Build Date: Apr 26 2005 X86
21:13:49.
Cable connection failed.
Reusing 7A020001 key. WinDriver v7.00 Jungo (c) 1997 - 2005 Build Date:
Apr 26 2005 X86 21:13:49.
Cable connection failed.
Reusing A0020001 key.
Connecting to cable (Usb Port - USB21).
Checking cable driver.
File version of /home/krish/binaries/Xilinx/bin/lin/xusbdfwu.hex =
1018(dec),
03FA.
File version of /etc/hotplug/usb/xusbdfwu.fw/xusbdfwu.hex = 1018(dec),
03FA.
Cable connection failed.
Reusing B4020001 key.
Connecting to cable (/dev/ttyS0 Port).
Cable connection failed.
Reusing B5020001 key.
Connecting to cable (/dev/ttyS1 Port).
Cable connection failed.
Reusing B6020001 key.
Connecting to cable (/dev/ttyS2 Port).
Cable connection failed.
Reusing B7020001 key.
Connecting to cable (/dev/ttyS3 Port).
Cable connection failed.
Cable autodetection failed.
make: *** [download] Error 1
Connecting to cable (Parallel Port - parport2).
WinDriver v7.00 Jungo (c) 1997 - 2005 Build Date: Apr 26 2005 X86
21:13:49.
Cable connection failed.
Reusing 7B020001 key.
Connecting to cable (Parallel Port - parport3).
Article: 85618Rob,et.al. Oleda technologies has a web-based tool that will create heterogeneous Orcad or Viewlogic schematic symbols for your parts. Fully functional trial-accounts are available. Your symbols can be generic which use the Xilinx pin descriptions for pin lables, or they can be based off of the UCF, or PAD file for your design which allows the use of your design signal names for the pin labels. The symbol set can be partitioned based on the architecture, a symbol for each IO bank, one for power and ground, configuration etc, or it can be partitioned by function based on your signal names. You can also generate symbols for footprint compatible parts which will check your pin assignments against all the parts which are available in the same family and package. Pins with NCs in one or more parts will be annotated on the symbol. This tool provides a very quick way to generate custom schematic symbols for any design. A graphical editor is available to examine or reposition pins after you have configured your symbol set. You can move pins between symbols or reposition pins on a symbol etc. In addition to generating the symbol, it generates a cross-reference table which can be helpful in documenting your fpga or checking your schematics. Oleda also has a program called PCB_Review which will examine the FPGA connections in your PCB netlist file and compare them to your FPGA design. It will check all the power and ground pins and the decoupling caps. It checks VREFs for IO standards which require them. It checks the configuration pins, looks for pullups on done, Init etc, checks DCI resistor connections, trace out your JTAG chain for multiple FPGAs etc. It will look at your the signal connections for the design and report any FPGA signals which are not connected to nets on the board, or any board nets which go to pins without an FPGA signal assignment in your design. Differential signal pairs are checked to match pairs on the board to pairs on your design and against the IO standards in your UCF. It will check and report termination resistors on each signal in your design. A table of all the connections for your FPGA is generated. This is definitely a set of tools that will help with "Obsurd schedules made by unsympathetic management". JohnArticle: 85619
Duh, I forgot the link! Oleda Technologies can be found at www.oledatech.com JohnArticle: 85620
On Thu, 9 Jun 2005 09:20:07 -0400, "Vladislav Muravin" <muravinv@advantech.ca> wrote:
>Davy,
>
>Just to complemenmt what Peter and Jochen said, as you go
>simulating your memory,
>remember that write and read to the same address entry
>will give you unknown values. you will have to bypass this.
>Vladislav
Actually, the situation of both ports accessing the same address
is somewhat more complex than "it never works" .
I described it here:
http://www.fpga-faq.com/archives/72650.html#72651
Philip Freidin
Fliptronics
Article: 85621On 12 Jun 2005 00:52:37 -0700, "Davy" <zhushenli@gmail.com> wrote: >Hi all, > >There is another question: Why Xilinx designed 18k ram? 18k isn't 2^n. The Xilinx BRAM has configurable width. When it is 1, 2, or 4 bits wide, the depths are 16K, 8K, and 4K respectively. All deliver 16K bits total. I.E. in 4 bit wide mode, the memory has 4K locations, and each read or write transfers 4 bits at a time. For 8 and 16 bits wide, there is an extra bit for each 8 bits, so the widths are really 9 or 18 bits, and the depths are 2K and 1K respectively. I.E. in 18 bit wide mode, the memory is 1K deep, for a total of 18K bits, and reads and writes transfer 18 bits at a time. "Why is it designed this way?" you ask. The optimal size for on chip block rams is 16K bits, although the organization (width by depth is scattered among the 5 different arrangements I have just described). 2K bytes holds a standard length ethernet packet (1.5K), A line of video from a high res screen (1600 pixels), (or maybe multiple blocks for RGB) A reasonable amount of a track of a disk drive, A CPU cache that isn't trivially small, and lots of other things. Since you can gang them together, that lets you build bigger structures. Either wider, or deeper, or both. Since you can use them separately, you can have enormous on chip bandwidth that you would not get if you built a smaller number of larger blocks. In the grand scheme of things, 16K bits covers the most possible applications efficiently, especially if it is also dual port, and hopefully synchronous. If you asked designers whether the memory should include parity, a high percentage would say that it is mandatory. So that makes the 8 and 16 bit widths, 9 and 18. When you actually look at what designers do with the memories at 9 and 18 bits width, almost none use the extra bit for parity. But is is heavilly used for tag/flag type info. For example, if you built a FIFO with block RAM, and you had a stream of packets that were each 53 bytes long (an ATM packet), you could set the 9th bit on the first byte of the packet as you store it into the FIFO, and when you were reading out of the FIFO, there it would be to differentiate a start of packet from the rest of the packet. >How to seperate its address into "1XX...XX" and "0XX...XX"? So the only time the memory is 18K bits is for by 9 and by 18 width. At by 9, the depth is 2K, or 11 address bits, and all the addresses are valid. Similarly, for 18 bit wide mode there are 10 address bis, and all addresses are valid. >Best regards, >Davy Cheers, Philip =================== Philip Freidin philip.freidin@fpga-faq.org Host for WWW.FPGA-FAQ.ORGArticle: 85622
Hi Marc, > So when you use that same part for additional designs, you'd rather > spend the effort to do a unique 500 or 900 pin symbol for each of those > designs rather than making it generic (per bank) to begin with so it > only has to be done once? Correct. I do reuse symbols I've already made, obviously, and it may require a pinning change. For new symbols, I take an existing one, and re-do it. > Sounds like a significant amount of extra > work. No, not really. It is far less work, and makes for far more usable (clean and able to be followed and better document the design) schematics since I don't have to hunt around for pins, draw busses to many different places, cross pages for logically grouped functions etc. I've done both, and my current method works far better for my needs. It really is a matter of whether you simply consider your schematics simply a netlist or a document. I consider my schematics documentation, and need them to be as descriptive as possible of the design, as well as easy to logically follow so others can garner the gist of the design easily. Regards, AustinArticle: 85623
jjlindula@hotmail.com wrote:
> I'm trying to convince some co-workers that it is important to
> document their work and follow standards in their designs.
The only way to do this is by example.
> Some of my
> co-workers are very fast designers and are respected by their peers,
> but in their rush to get the design done they often ignore standards
> and don't document their work, such as in their schematics or in their
> FPGA code.
Let it go and get on with your own work.
> I realize that I might not be able to
> change more senior engineers, but I might be able to leave an
> impression on the newer engineers.
Consider publishing your own design documentation
as a reference for other engineers.
-- Mike Treseler
Article: 85624Hi , I have build an system with 2 ppc 405 and I want to run application programs on 2 nd ppc but not on 1 st, I dont know at which point I have to specify whether in the application program or somewhere in the EDK tool I have to use certain options ..... some of your drop outs would be grateful for me... thanks for your time... Jagadeesh
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