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Hi, Has anyone tried connecting the P160 Comms2 module to the Memec S3-1500 board? Using Base System Builder with Memc's XBD files, it assumes the module is on P160 Slot A (left hand side of the board). However, when placed in this slot the P160 MAC phy_rx_d<3> pin, defined as 3.3V LVCMOS, connects to FPGA pin AD13 which is on the same IO bank as most of the main board's DDR signals (2.5V SSTL) e.g.: fpga_0_DDR_SDRAM_16M IO SSTL2_I 1.25 2.50 PAD327 AC13 fpga_0_P160_Ethernet I LVCMOS33 NR 3.30 PAD326 AD13 PAR refuses to continue, and rightly so. I'm redoing my constraints to try the module in the other slot, hopefully that will not have such a conflict. If anyone from Insight/Memec is listening, please let your engineering teams know - or is this a known issue? Cheers, JohnArticle: 85726
Here's an opinion (emphasis on the last word there): The world seems to fall into 2 camps. Altera is fundamentally a STAPL house. They invented the language and are the only strong supporters of it. They have several variations - JAM (the original non-standard flavor), STAPL (the JEDEC standard version) and a variation that is compiled into a proprietary byte code. Altera's support of the STAPL has been tailing off for the past few years but they will help you out if you pester them enough. If your board is only to have Altera devices on it for the foreseeable future that is your best bet. You will find tepid support from other vendors. 1532, on the other hand, is more accepted at Xilinx. The standard is published by the IEEE and there are no proprietary variations of it. Xilinx has a free, source code interpreter for 1532 called JDrive that you can pick up from their web site. Most manufacturers - even Altera - will support you using 1532 if you pester them enough. The key differences are as follows: 1. The run time memory requirement for STAPL may be significantly larger than that of 1532 2. 1532 has separation of data (ISC file) and algorithm (BSDL file) making update a simpler operation and limiting your exposure to silicon changes. 3. 1532 supports concurrency at configuration time; STAPL must compile it into the STAPL source file I do not know if 1532 or STAPL is faster in execution. I suspect that may depend on the platform and the device you are targeting. I think that because STAPL has data and algorithm intertwined in the same file, there would be fewer IO operations than 1532 yielding a run time advantage to STAPL. This may be nullified though because of its larger run time memory requirement. But again, given that the content of your system is completely Altera product, I think you will be able to extract better support from them by using STAPL. mandana@physics.ubc.ca wrote: > Hi all, > > We want to implement a JTAG programmer in an Altera Stratix device to > program a chain of EPC16 devices. The Stratix device is commanded > through a fibre interface connected to a PC (the ONLY possible > connection to the PC). > > So far, as we understand we have two options, one is to use JAM/STAPL > format and the other option is to use isc files (IEEE 1532). In either > case, we could instantiate a NIOS to handle the JTAG programming. I > wonder if we can get an expert's opinion on which option makes more > sense perhaps depending on the quality of the JAM/isc files that > Quartus generates and how long it takes to program the part. > > Is it true that the programming time is shorter when using isc files? > What are the pros and cons of each option? > > Thanks, > m >Article: 85727
Did you try http://www.sierraic.com/ . I never purchased from them, but it looks like they may have stock. I found 34 of the XCR3384XL10TQ144C at this site. D Brown "Bruno" <bmscc@netcabo.pt> wrote in message news:42af5b7d$0$32020$a729d347@news.telepac.pt... > Does anyone know where can I buy a Xilinx XCR3384XL tq144 CPLD? > > Thanks in advance > Best Regards > Bruno > >Article: 85728
I wrote: > However, when placed in this slot the P160 MAC phy_rx_d<3> pin, defined > as 3.3V LVCMOS, connects to FPGA pin AD13 which is on the same IO bank > as most of the main board's DDR signals (2.5V SSTL) e.g.: > I'm redoing my constraints to try the module in the other slot, > hopefully that will not have such a conflict. OK so it's even worse :( ERROR:Place:348 - The IOB fpga_0_P160_Ethernet_MAC_PHY_rx_data_pin<2> is locked to site AE16 in bank 4. This violates the SelectIO banking rules. ERROR:Place:348 - The IOB fpga_0_P160_Ethernet_MAC_PHY_dv_pin is locked to site AF17 in bank 4. This violates the SelectIO banking rules. ERROR:Place:348 - The IOB fpga_0_P160_Ethernet_MAC_PHY_tx_er_pin is locked to site AE17 in bank 4. This violates the SelectIO banking rules. and so it goes. There are about 7 Comms module IOs that are unplaceable because of this. At least in the left slot there's only one impossible IO. Overall, it seems that the P160 Comms2 module is unusable with the S3MB1500 board. Any ideas on how I might get past this? I could fudge the IOSTD constraints to force it to map, but intermixing 2.5V FPGA pins with 3.3V signals seems like a bad idea. Thanks, JohnArticle: 85729
Strange that - you'd have thought if you're making TV's you'd plan to sell enough to pay for an ASIC "Dave Garnett" <dave.garnett@metapurple.co.uk> wrote in message news:42aea2f7_2@spool9-east.superfeed.net... > As someone who is still working with Spartan II, I was amused to see that > my mothers new television has a Spartan 3 inside ... > > Dave > > > > > Posted Via Nuthinbutnews.Com Premium Usenet Newsgroup Services > ---------------------------------------------------------- > ** SPEED ** RETENTION ** COMPLETION ** ANONYMITY ** > ---------------------------------------------------------- > http://www.nuthinbutnews.comArticle: 85730
Oleda Tech has the answer. Anyone out there looking to create a part should stop by this site. You can create a part by bank or user-defined function. This package is sweet. I put together the Xilinx part in minutes. I saved myself hours of work. This is a MUST see package. "pipjockey" <pipjockey@yahoo.com> wrote in message news:1118576581.183362.243210@g49g2000cwa.googlegroups.com... > Rob,et.al. > > Oleda technologies has a web-based tool that will create heterogeneous > Orcad or Viewlogic schematic symbols for your parts. Fully functional > trial-accounts are available. > Your symbols can be generic which use the Xilinx pin descriptions for > pin lables, or they can be based off of the UCF, or PAD file for your > design which allows the use of your design signal names for the pin > labels. > The symbol set can be partitioned based on the architecture, a symbol > for each IO bank, one for power and ground, configuration etc, or it > can be partitioned by function based on your signal names. You can > also generate symbols for footprint compatible parts which will check > your pin assignments against all the parts which are available in the > same family and package. Pins with NCs in one or more parts will be > annotated on the symbol. This tool provides a very quick way to > generate custom schematic symbols for any design. A graphical editor > is available to examine or reposition pins after you have configured > your symbol set. You can move pins between symbols or reposition pins > on a symbol etc. In addition to generating the symbol, it generates a > cross-reference table which can be helpful in documenting your fpga or > checking your schematics. > > Oleda also has a program called PCB_Review which will examine the FPGA > connections in your PCB netlist file and compare them to your FPGA > design. It will check all the power and ground pins and the decoupling > caps. It checks VREFs for IO standards which require them. It checks > the configuration pins, looks for pullups on done, Init etc, checks DCI > resistor connections, trace out your JTAG chain for multiple FPGAs > etc. It will look at your the signal connections for the design and > report any FPGA signals which are not connected to nets on the board, > or any board nets which go to pins without an FPGA signal assignment in > your design. Differential signal pairs are checked to match pairs on > the board to pairs on your design and against the IO standards in your > UCF. It will check and report termination resistors on each signal in > your design. A table of all the connections for your FPGA is > generated. > This is definitely a set of tools that will help with "Obsurd schedules > made by unsympathetic management". > > John >Article: 85731
Gary Pace wrote: > Strange that - you'd have thought if you're making TV's you'd plan to sell > enough to pay for an ASIC Could be a time-to-market thing :) Sell lots, then go to asic later. JeremyArticle: 85732
Jeremy Stringer wrote: >> Strange that - you'd have thought if you're making TV's you'd plan to >> sell enough to pay for an ASIC > > Could be a time-to-market thing :) Sell lots, then go to asic later. Or even better (from Xilinx' perspective), reinvest the income from being early to market into your next generation of product, rather than spending the big bucks recreating in ASIC something that's already working and selling. JohnArticle: 85733
Hi, Yes I know re-timing, it just push pull the register(rely on the original netlist), but not insert register. Is there any tool to insert registers? Thanks! DavyArticle: 85734
Jeremy Stringer wrote: > Gary Pace wrote: > >> Strange that - you'd have thought if you're making TV's you'd plan to >> sell enough to pay for an ASIC > > > Could be a time-to-market thing :) Sell lots, then go to asic later. Or a Digital TV effect. I see the FCC is trying to mandate obsolescence on all Analog TVs in the USA, by forcing a move to digital. Waste / landfill ? Not our problem!! This is a high stakes gamble: would you roll an ASIC, or use an FPGA while you wait to see the what the political fallout and lobbying brings, once the dust settles ? -jgArticle: 85735
Two possible causes. 1. You are not using the latest version of the Impact tool. When Xilinx updates the FAB process to various chips, it will sometimes render older versions of Impact incompatiable. If you haven't purchased the latest version of ISE, try the Webpack version of Impact from their website. 2. The parallel 3 cable is prone to noise. Check all your connections an try moving the cable away from any noise sources. dejavu99@hotmail-dot-it.no-spam.invalid (damidar) wrote in news:MfidnZJr6fJ5nzLfRVn_vg@giganews.com: > hi....Please help me for a programmer xilinx XC9536XL (parallel LPT) > > When i starter to program, it stopped on: > > "Error:IMPACT 583 :the idcode read from the device does not match the > idcode in the bsdl" > > :( > > Help me thanks a lot..... >Article: 85736
I get the following message when I run XPS or its other components (like Create/Import Wizard, Xilinx Cygwin Shell, etc.). "This application has failed to start because libPortability.dll was not found. Re-installing the application may fix this problem". I have installed EDK 7.1 (original version) on a Win XP machine that has ISE 7.1 SP2 successfully installed and working. I tried to install EDK 7.1 SP1, but the issue persists after installing it. Also, I made sure that the environment variables, XILINX_EDK and XILINX, are set and placed first in the path as suggested by a related Xilinx Answer Record #16591 (http://www.xilinx.com/xlnx/xil_ans_display.jsp?BV_UseBVCookie=yes&getPagePath=16591&iLanguageID=1). Finally, after installing, I restart the machine just to make sure the variables are set. EDK exhibits the same behavior when installed on another Win XP machine. Any one with tips to get around this? Thanks, NNArticle: 85737
I have the Parallel Driver xp4drv also installed, but I believe for the USB cable windrvr6 is OK. I received the (good ) advice to change, in the file /etc/hotplug/usb.usermap, on the line containing the label `xusbdfwu', the Product ID 0x0007 to 0x0009. It now goes further already, so I am on the good path, but I still get: # make -f system.make download ********************************************* Downloading Bitstream onto the target board ********************************************* impact -batch etc/download.cmd impact: error while loading shared libraries: /home/krish/binaries/Xilinx/bin/lin/libSTL.so: cannot restore segment prot after reloc: Permission denied make: *** [download] Error 127 That looks like a file permission or security problem. Could not yet trace it, however. All ideas are welcome.Article: 85738
Nju Njoroge wrote: > I get the following message when I run XPS or its other components > (like Create/Import Wizard, Xilinx Cygwin Shell, etc.). > > "This application has failed to start because libPortability.dll was > not found. Re-installing the application may fix this problem". Where does your XILINX-environment-variable point to? This error usually occurs when you're using different versions of EDK and ISE. If you want to use EDK7.1, you have to use ISE7.1 as well, otherwise you get the above error message. cu, SeanArticle: 85739
You can use the Virtex2pro for highspeed LVDS, but extreme care must be taken with the board layout when operating at those frequencies. Impedance control of your microstrip LVDS signal must be maintain from the I/O pins to the output connector. Most manufacturers will use external LVDS drivers an receivers because of this critcal routing. It is easier to place the external chips near the connector than the FPGA. "Lucas" <lucas_bossetti@hotmail.com> wrote in news:Y9cre.3$yM4.193@twister2.libero.it: > Hi, > I want to implement a SCSI Ultra-160 or SCSI Ultra-320 host on a > VirtexII-Pro FPGA. > My goal is to connect the FPGA to an array of SCSI disks. > This is proprietary link so I don't need full adherence to the > specifications. > > My questions are: > 1- Is Xilinx LVDS I/O compatible to the SCSI LVD standard? > 2- Is it possible to implement a LVD Multidrop SCSI bus with a > VirtexII-Pro FPGA? > > Thanks! > > >Article: 85740
Try this site: http://legacy.memec.com/devkits/americas.shtml http://www.memec.com/?cmd=supplierlanding&supplier=2#7Article: 85741
There is no good excuse for sloppy work. It doesn't take much time to
properly outline and structure code. For FPGA vhdl code I fine following
this simple rule useful.
Top level should contain no processes if possible. Processes
should be grouped into seperate entities and used as components in the
top level.
This has several advantages.
1. You can create individual test benches for simulation of the seperate
components. Simulation is much faster.
2. Generation of the RTL schematic provides a cleaner, block diagram
look.
3. Individual components(entities) are easier to troubleshoot and
optimize.
4. Easier to locate parts of the design which are slow and require
additonal work.
5. Tighter control of shared signals. Althought routing these signals
between entities is more difficult. It is easier to follow their useage
and prevent conflicts.
6. Xilinx ISE tool shows a nice hierarchy tree.
7. Updating the design is easier by adding addtional componets, or
modifing only the appropriate component.
Example.
module_control (top.vhd)
top.ucf
system_tstbd (system_test.vhd) --SIMULATION TESTBENCH
pc_interface (pc_intrfc.vhd)
pc_tstbd (pc_test.vhd) --SIMULATION TESTBENCH
data_in (data_in.vhd)
datain_tstbd(datain_test.vhd) --SIMULATION TESTBENCH
data_out (data_out.vhd)
dataout_tstbd(dataout_test.vhd) --SIMULATION TESTBENCH
motor_control (mtr_cntrl.vhd)
mtr_tstbd (mtr_test.vhd) --SIMULATION TESTBENCH
Each of the components can be individually synthesized, checked for
functionality and maximum performance. Synthesis tool will report the
maximum speed. If the design was flat with only one entity, synthesis
would report the maximum speed for the slowest process, but you would not
know which process.
FPGA's must always be functionally simulated. With most designs, there
are thousands of signals and a logic analyzer is useless. A good
functional simulation with the proper stimulus will always find your
errors and quickly identify the problem.
"jjlindula@hotmail.com" <jjlindula@hotmail.com> wrote in
news:1118527411.599463.25430@g49g2000cwa.googlegroups.com:
> Hello, I'm looking for some information that describes some of the best
> practices or habits for successful electronic design or embedded
> design. I'm trying to convince some co-workers that it is important to
> document their work and follow standards in their designs. Some of my
> co-workers are very fast designers and are respected by their peers,
> but in their rush to get the design done they often ignore standards
> and don't document their work, such as in their schematics or in their
> FPGA code. I feel these habits and behavior actually wastes money, by
> that I mean that if someone has to take their undocumented work, they
> won't know what is going on. I realize that I might not be able to
> change more senior engineers, but I might be able to leave an
> impression on the newer engineers. If anyone knows of some habits or a
> list of some best practices that make a successful design, please pass
> them onto me. Most of these habits I would assume fall into proper
> system engineering.
>
> thanks,
> joe
>
Article: 85742
> Yes I know re-timing, it just push pull the register(rely on the
> original netlist), but not insert register.
> Is there any tool to insert registers?
Well, inserting registers changes your design in a fundamental way.
Most circuits I can think of would just stop working if you added
registers to them at random. Only you, the designer, know exactly
how much pipelining it is legal to apply to a given part of your
circuit. So I don't believe such a tool exists - certainly not in the
general case.
Cheers,
-Ben-
Article: 85743Davy wrote: > Hi, > > Yes I know re-timing, it just push pull the register(rely on the > original netlist), but not insert register. > > Is there any tool to insert registers? > I would think that would be a very bad idea to try to do automatically - it would completely change your timing. It's one thing to automatically do re-timing to improve your margins or your maximum clock rate, but adding registers will change the function of your logic. You might just as well ask for a tool to insert extra logic to improve your design. > Thanks! > Davy >Article: 85744
Sean Durkin wrote: > Nju Njoroge wrote: > > I get the following message when I run XPS or its other components > > (like Create/Import Wizard, Xilinx Cygwin Shell, etc.). > > > > "This application has failed to start because libPortability.dll was > > not found. Re-installing the application may fix this problem". > Where does your XILINX-environment-variable point to? This error usually > occurs when you're using different versions of EDK and ISE. > > If you want to use EDK7.1, you have to use ISE7.1 as well, otherwise you > get the above error message. > I installed ISE 7.1 first with the SP's and that worked by itself. I then installed EDK (refer to my original posting). > cu, > Sean Thanks for the response. NNArticle: 85745
Hi,
Can any body help me by giving website address or info
about VHDL synthesis coding techniques.
Thank u.
Hima.
Article: 85746Hello, We utilizes 3 stratix kit dsp board EP1S25 where we have disconnected the +5V, +3.3V, +1.5V voltage regulator and have directly connected these 3 voltage with DC/DC converter. Sometimes, one of the three cards don't program them. This is the MAX chip which program the FPGA through the Flash Memory. This chip is connected to the 3.3V We notice that when the +3.3V is OK, the +1.5V is not really arrive to 1.5V, and so I think that the MAX begin the programmation when the Vcc core is not OK and that fail the programming sequence ? Do you have suggestions or did you have this problem yet ? Thanks..Article: 85747
From: <jjlindula@hotmail.com> > I'm trying to convince some co-workers that it is important to > document their work and follow standards in their designs. Good luck. > Some of my > co-workers are very fast designers and are respected by their peers, > but in their rush to get the design done they often ignore standards > and don't document their work, such as in their schematics or in their > FPGA code. I feel these habits and behaviour actually wastes money, by > that I mean that if someone has to take their undocumented work, they > won't know what is going on. Agree with you entirely. However many (most?) companies are in a mad rush to do things faster. They don't see the point of slowing down code production for future benefit. At one job, my predecessor was a fast coder, could re-write heaps overnight, but left the company with next to no documentation about how he meant his code to work. I spent heaps of time reverse engineering it, found lots of things to clean up, and some bits were just messy/confusing. The system had some kind of state machine I could not make elegant or modify without it falling over. That job didn't last! Only my predecessor could understand it, which he did because his new job did not work out and he came back. One old cow-orker there had a closed mind: "Can't do it like that, there ain't time". Kept repeating statements like that so he didn't have to listen to heretical suggestions that things could be done better or differently. One of my friends is a software project manager. He regularly finds code that isn't documented and says it is almost always quicker to re-write than to document the old code. Making anything complex without documentation is like driving without insurance. It saves you time and money and is perfectly fine. Right up to the moment when it isn't! Then you are up shit creek. Don't skip documentation unless you are prepared to throw your work away, because sooner or later somebody will. If you are an employer, be aware of the consequences of letting coders skip documentation. They will have you by the snarglies when they ask for a pay rise and you dare not let them go. (hmm, that's not encouraging coders to document stuff is it?)Article: 85748
himassk wrote:
> Can any body help me by giving website address or info
> about VHDL synthesis coding techniques.
Here's a reference design and testbench
to get you started.
http://home.comcast.net/~mike_treseler/
-- Mike Treseler
Article: 85749Have you seen Answer #20762? --------From Xilinx Answer 20762---------- For USB cable support, it must be installed with the ISE CD install. The USB cable driver in 7.1i ISE is precompiled for Red Hat Enterprise Linux 3. The Platform Cable USB uses the windrvr6 device driver. This is the same driver that is used for the Parallel cables. In addition, the following files are also required: setup_pcusb -> install script xusbdfwu.hex -> cable firmware xusbdfwu,xusbdfwu.usermap -> linux setup/script files These files are copied to the %XILINX%/bin/lin directory when ISE is installed. To run the driver installation, cd to the %XILINX%/bin/lin directory and run setup_pcusb. For Linux Kernel 2.4.x, the windrvr6 device driver should be built from the source code. See solution 18612 for the driver compilation instruction. If the files are missing, the user can install the drivers from the Installer CD.
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Compare FPGA features and resources
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