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Philip Freidin wrote:
>Yes, You are rignt. X18 works fine too, it is x36 that uses up all the
>fabric interface.
>
>Philip
>
>
>Philip Freidin
>Fliptronics
>
>
And that problem is avoided in Virtex 4. FWIW, the FIR filter core
generator does fine with generic stuff, but when you have special
considerations it often doesn't give you the best solution.
Unfortunately, you can't get under the hood to tweak it at all, so your
choices are to live with the core generator as is, or create your own
filter from scratch (not hard to do, but time consuming by the time you
get through verification).
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 86201I think the online store is meant for sending you really small numbers of devices, really fast. That's the Digi-Key model: "Single-unit price, but you have it next day. No discussion, no rebates, no returns, no support". Ideal for prototyping. If you need a hundred, talk to the distributor. Peter AlfkeArticle: 86202
Ray Andraka wrote:
> Unless you are putting RLOCs on the DSP48's. That is still broken in
> SP2. Last version it worked correctly in is ISE6.3 SP3. ise7.1 SP3
> fixes that, but has a problem with the C ports on the DSP48 (the C
> Port is physically shared by two DSP48 slices, but shows up
> individually for each slice in the library. If both DSP48s do not
> have the same value tied to the C Port, its CE input and its reset
> input, the mapper crashes. If you are careful, that isn't a problem.
> The problem comes if one DSP48 uses the Cport and one doesn't, you
> still have to specify the same inputs on both. That creates a packing
> problem unless you've pre-packed the DSP48s making sure both Cports
> are wired identically.
>
I was just told that they managed to get the CR for the Cport error into
SP3, so it sounds like that might work correctly. Time will tell:-)
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 86203The "Create and Import Peripheral Wizard" is the place to start. It generates an example user pcore and the device drivers to interface to it. http://www.xilinx.com/ise/embedded/est_rm.pdf Paul nrivera.eng@gmail.com wrote: > > Does anyone has an example of a user IP core hooked up to the PLB bus > for a Virtex 2P in EDK? > I am wondering how I can get my core to be connected to the PLB bus in > the Virtex 2P anmd controlled it viua Software, > I am using Xilinx EDK. > > Thanks > NRArticle: 86204
Shadows of the past. I was "The Applications Department" for the Z80, 27 years ago. Good things never die :-) Peter AlfkeArticle: 86205
I'm designing with a V2PRO and its config PROM. I noticed that I will need: 1. VCCint (PROM) = 1.8V 2. VCCint (FPGA) = 1.5V 3. VCCAUX = 2.5V The system will only deliver me 5.0V and 3.3V which means that I will need to generate the above voltages. If I were to use an Altera Stratix part, and its config device, I would only need to generate the 1.5V--much cleaner. I have tight board space constraints which make working with Xilinx much more difficult. Seems as if Altera has an advantage in this area??Article: 86206
Thanks Antti ... So ... what's the most appropriate approache to follow ? Virtex II + jbits ? What are the restrictions of jbits ? why do you say that it's dead ?Article: 86207
Ok ... this was a momentrly problem (perhaps they were updating some server ... I got in .... but too expensive for me ... the problem is that I don't have access to any Xilinx University Program :( because our university is not a subscriber :(:(:(Article: 86208
Hi, we are reading an ADC o/p through FPGA. To remove the DC Offset present in the ADC input we have a DAC which can remove this DC offset using a subtractor before the actual analog input (with added DC offset) goes to ADC. Now I want my FPGA to calculate the DC offset from ADC outputs and then feed this value to DAC input which in turn cancel the DC offset using subtrator. can anybody suggest me how can i implement this in FPGA? I just gone through net and realized that i can use a subtractor and a MAC. The ADC output will go to this Subtractor which has the final output of MAC as other input. the subtractor output will be multiplied with some small value K (??) and then an accumulator. The final output of accumulator can be feedback to the DAC. The DAC o/p is going to Mixer to cancel the DC offset? this is what i understood. can somebody through some light? suggestions are welcome.Article: 86209
Subroto Datta wrote: > Here is a link to some of the Consumer Products which use FPGA's > today. > > http://www.altera.com/corporate/cust_successes/customer_showcase/view_industry/csh-vindustry-consumer.jsp This is interesting... it mentions Gibson Guitar Corp. as one of the customers for the Cyclone. And every time I install ISE, I see a picture of Gibson proclaiming "Spartan-3 - I made it my ASIC". Looks like they're using a Cyclone for one product and decided to use Spartan-3 for another. "The best of both worlds" in one company :) cu, SeanArticle: 86210
"GaLaKtIkUsT" <taileb.mehdi@gmail.com> wrote in message news:1119500021.703961.282300@g14g2000cwa.googlegroups.com... > Ok ... this was a momentrly problem (perhaps they were updating some > server ... I got in .... but too expensive for me ... the problem is > that I don't have access to any Xilinx University Program :( because > our university is not a subscriber :(:(:( > Well join yourself. Contact xilinx and see what you need to do, its well worth it. AlexArticle: 86211
Duane Clark wrote:
> Go to the Cypress website. Download the datasheet, and the VHDL/Verilog
> models for the SRAM. Put the SRAM HDL model in your testbench and write
> your interface code. An SRAM is simple to use; it barely justifies being
> called a "memory controller". You should read the datasheet and do it
> yourself; you will learn a lot more than asking here.
All true enough, but I hope I'm still allowed one question :-)
My sram memory interface works, but I've had to insert an idle cycle to
make the read data settle.
Reading the spec for the IDT71V416S10 it claims both tAA and tRC to be
10ns, with a tOH hold time of 4ns min hold time. I thus expected
something like this to work:
always @(posedge clk100MHz) begin
sram_a <= <new addr>;
latched_data <= sram_d;
end
where latched_data is from the previous address obviously. It worked
fine under simulation against the idt71v416s10.v model from IDT, but on
the board it wasn't reliable.
I didn't supply any timing constraints for the FPGA pins connected to
the SRAM and I suspect that to be the problem, but I'm a bit unsure what
should I give as constaints. Suggestions?
Thanks,
Tommy
Article: 86212Hi, has anyone ever seen a Virtex-4 FX-part with RocketIO-MGTs? Any FX bigger than the FX12? And I'm talking about seeing it in real life, holding it in your hand, putting it on your boards, not just seeing a Xilinx-manufactured, unpowered eval-board at some trade fair... Originally, we wanted to use a Virtex-4 FX20 in our latest design. Cool new part for a cool new prototype, we thought... so we ordered some engineering samples through our distributor (Insight Memec)... first they said "No problem, you'll get them in June", so we put it into our design... after all the schematics were done, and the layout halfway through, it was "Sorry, you won't get the devices until late July", which was of course too late, so we had to go back into the design, change everything to Virtex2 Pro, and cancel the order on the Virtex-4 parts. Now I wanted to use the FX20 for the next design... thinking "Hey, they told us we would get it in July", so I put it in the schematics, and ordered the FX20. So now the distributor says "No way, no parts available, not even engineering samples, production doesn't even start before October, don't even bother ordering." Now last I heard was that *mass production* was supposed to start in October, but engineering samples should be available long before that. Anyway, again I have to re-do half of my schematic, again I have to waste a lot of time for nothing, and again, I can't use a Virtex-4. Meaning that for us Virtex-4 is now dead for all designs and projects this year. What's up with that? Is there some problem with the MGTs? I can't even get a single development board with FX20 parts or bigger, they all have unknown availability dates. FX12 is no problem, anything bigger I just can't get my hands on. Did they find some serious bug in the silicon and then decided to stop production or something? cu, SeanArticle: 86213
Hi Peter, > Shadows of the past. > I was "The Applications Department" for the Z80, 27 years ago. Good > things never die :-) And life was simpler too... That was about the time I started coding for it, on my uncle's TRS80. I could have started earlier but I had to learn English first in order to read Rodnay Zaks's book ;-) Ah.. the times... BenArticle: 86214
Hi, I wanted to know if there is any lower limit on the minimum possible clock frequency that can be given to a Nios 2 processor. The Stratix 2 board has a 50 Mhz clock which also drives the Nios2. But I want to run the processor much slower, in Khz range. Can I go on reducing frequency? The board also contains some offchip SRAM and SDRAM, whic Nios2 can access. Will the frequecy be limited by the clock given to SDRAM ? TIA SunnyArticle: 86215
I dont believe that there are any minimum clock frequency. Though, you will propably find some practical challenges on your way. 1. I don't think that you can drive the output frequency of the pll's down as far as you want. You can propably splve this by using a clock divider circut, feeding the result back to the global clock networks. 2. I would expect some timing problems with the interface to circuits like the SDRAM, but nothing that can not be solved. So the simple answer is: Go ahead and try! HavardArticle: 86216
Sunny wrote: > Hi, > > I wanted to know if there is any lower limit on the minimum possible > clock frequency that can be given to a Nios 2 processor. The Stratix 2 > board has a 50 Mhz clock which also drives the Nios2. But I want to run > the processor much slower, in Khz range. Can I go on reducing > frequency? > The board also contains some offchip SRAM and SDRAM, whic Nios2 can > access. Will the frequecy be limited by the clock given to SDRAM ? > TIA > Sunny > The Nios 2 itself, and all surrounding logic, should run at any speed up to the maximum for the design. As long as a design does not rely on timing delays (and a good design should not, obviously), there should be no problem clocking it all with an external toggle switch. The SDRAM, on the other hand, will be a problem - data is stored in tiny capacitors, and needs to be refreshed at regular intervals or it will leak. As you lower the clock speed, there is less time (i.e., fewer clock cycles) between refreshes, until you can't do anything with it but refreshes. Lower than that, the SDRAM is useless. PLLs also have limits on their frequency range - you just have to add divider logic to reduce the clock further.Article: 86217
I think there was a similar discussion on www.niosforum.com . The problem was that the JTAG-UART (for debugging) did no longer work a low frequencies (I think it was around 10MHz). The SDRAM will not operate successfully at these low frequencies as others mentioned. I think, with the latest Nios-version it is possible to use a different clock for the SDRAM than for the Nios. But why do you want to operate the Nios that slow? (If it is for power-reduction, I think you should not choose a Nios-solution anyway...) Regards Thomas www.entner-electronics.com "Sunny" <shiladitya.biswas@gmail.com> schrieb im Newsbeitrag news:1119509254.050750.291260@g14g2000cwa.googlegroups.com... > Hi, > > I wanted to know if there is any lower limit on the minimum possible > clock frequency that can be given to a Nios 2 processor. The Stratix 2 > board has a 50 Mhz clock which also drives the Nios2. But I want to run > the processor much slower, in Khz range. Can I go on reducing > frequency? > The board also contains some offchip SRAM and SDRAM, whic Nios2 can > access. Will the frequecy be limited by the clock given to SDRAM ? > TIA > Sunny >Article: 86218
Let's assume your top level is called 'system', which is the default. EDK produce the simulation files, along with another file called 'system_init.[v/vhd]'. That last file contain the initialization for the memory. You need to initialize the memory with that file. Depending on if you are making verilog or vhdl target, the procedure may be different. I don't know about VHDL, I use Verilog. For Verilog, you need to start simulation of 'system' (in system.v) and 'system_conf' (the main module in system_init.v) at the same time, both as top-level. 'system' must be top-level in simulation too so if you have a testbench, it must run in parallel with 'system' module. You do this by specifying multiple modules to the 'vsim' command in ModelSim. Ex: vsim -t ns system_conf system testbench glbl In your testbench, you connect to 'system' as follow ---- module testbench() //top-level 'testbench' only serve to connect to top-level 'system' module. test test1(.clk(system.clk), .a(system.a), .b(system.b), .y(system.y)) endmodule module test(clk,a,b,y) //Put your stimulus here reg a reg b reg clk wire y ... endmodule ---- For VHDL, I think there's a command called 'configure' which verilog lack an equivalent. In that case, you can configure the system unit with the system_conf module. This make it easier.Article: 86219
Hi Any body used FFT core given by coregenerator in Xilinx ? Does it work as they said in their data sheet.. regards bijoyArticle: 86220
Sunny wrote: > Hi, > > I wanted to know if there is any lower limit on the minimum possible > clock frequency that can be given to a Nios 2 processor. The Stratix 2 > board has a 50 Mhz clock which also drives the Nios2. But I want to run > the processor much slower, in Khz range. Can I go on reducing > frequency? > The board also contains some offchip SRAM and SDRAM, whic Nios2 can > access. Will the frequecy be limited by the clock given to SDRAM ? As far as I know, the lower frequency limit applies to the PLL. So when you don't use the PLL, you should be able to go down to DC. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 86221
Hi Thomas, Thanks for your reply. The reason I want to slow processor clock frequency is that I basically want to stop the processor from executing when I want, and give it clocks only when needed (through some clock gating mechanism). It is a multiprocessor system where one processor will run at high speeds (~50 Mhz) and the other processor will run only when needed. So I wanted to know if can the processor retain its state for an indefinite time? I will take care of SDRAM clocks separately. Some processors like Pentium have a specification for the lowest clock frequency because they cannot retain the state for long enough (due to capacitors getting discharged). Is there any such limitation for Nios 2 ( essentially the FPGA fabric) ? So what I am looking for is that clock period should be theoretically infinite. For JTAG - UART can you direct me to some place where I can read exactly how it works and why debugging fails below 10Mhz. Thanks SunnyArticle: 86222
Hello Peter, Thanks a lot. Actually in my design JTAG controls the DGBC405DEBUGHALT pin of the PPC1, i just OR-ed debug signal from JTAG and debug halt from my core such that both of them can control the processor execution. To my suspect i directly assigned halt signal '1'so that processor halts at begining of program,but unfortunately it didn't stopped. Do i need to take some other aspects into consideration to halt PPC1? You mean that once we send processor to debug halt mode we need to give interupt to bring back for resume execution apart from making DBGC405DEBUGHALT '1'? Thnaking You. With Regards, JagguArticle: 86223
It is a slight inconvenience but here are a couple of things that might help. (1) Consider using a multiple ouput power controller like the TI TPS75003. (2) You could generate 1.8V by a diode drop from 2.5V. It should be near enough for a prom. I would not normally recommend putting anything that switches on Vccaux but a prom that will normally only operate at startup is unlikely to be a problem. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "Rob" <robnstef@frontiernet.net> wrote in message news:Eypue.1512$yg4.642@news01.roc.ny... > I'm designing with a V2PRO and its config PROM. I noticed that I will > need: > > 1. VCCint (PROM) = 1.8V > 2. VCCint (FPGA) = 1.5V > 3. VCCAUX = 2.5V > > The system will only deliver me 5.0V and 3.3V which means that I will need > to generate the above voltages. If I were to use an Altera Stratix part, > and its config device, I would only need to generate the 1.5V--much > cleaner. > > I have tight board space constraints which make working with Xilinx much > more difficult. Seems as if Altera has an advantage in this area?? > >Article: 86224
Philip Freidin wrote: > >> The BRAMs are still available when using the co-located multiplier, > >> except for BRAMs in the widest data path mode. I.E. you can use the > >> co-located BRAM in x1, x2, x4, x9 mode, but not x18 . > >I'm pretty sure the widest mode is x36 and x18 is O.K. with > >co-located multiplier... > Yes, You are rignt. X18 works fine too, it is x36 that uses up all the > fabric interface. The problem is that I don't know exactly how the FFT core uses these BRAMs. I need to implement an FFT transform with 24bits data and phase factors. Should I assume it implements x36 BRAMs? If that's true I can't use these co-located BRAMs! ... but maybe the FFT core uses BRAMs co-located with it's own multipliers. I'm just a little bit confused :-/
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