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Messages from 85975

Article: 85975
Subject: Re: Spartan 3 availability
From: Sylvain Munaut <com.246tNt@tnt>
Date: Sun, 19 Jun 2005 16:38:00 +0200
Links: << >>  << T >>  << A >>
Mike Harrison wrote:
> Further to recent discussiuons here, I Just noticed That S3s have appeared in the Xilinx web store. 
> A few are even shown as in stock....
> 

Great !
Way to go Xilinx !


	Sylvain

Article: 85976
Subject: Re: damage Atmel AT40k/AT94k with wrong bitstream?
From: "Peter Alfke" <alfke@sbcglobal.net>
Date: 19 Jun 2005 09:24:17 -0700
Links: << >>  << T >>  << A >>
Just to clarify:
A wrong FPGA bitstream can create massive internal contention, which
can damage a part. (I have seen a puff of smoke coming out of a totally
misconfigured XC3042 15 years ago...)
Xilinx has had CRC protection since XC4000, > 12 years ago. CRC
protects against accidental errors, but does not protect against
feeding a legitimate bitstream, meant for one part type, into the wrong
part type.
To protect against this, the Xilinx bitstream also checks the chip ID.
We have not heard about any problems ever since.
Peter Alfke


Article: 85977
Subject: Xilinx webshop
From: "Dr Justice" <sorry@no.spam.wanted>
Date: Sun, 19 Jun 2005 18:33:51 +0200
Links: << >>  << T >>  << A >>
Following the Spartan 3 availability threads, I visited the Xilinx webshop.
The only FPGA on offer there is the Spartan 3. IIRC the webshop used
to have a much better selection. It seems a bit strange to me to reduce
the (FPGA) offerings to only 1 kind of FPGA and 1 handbook for
a different FPGA.

Questions:
  Why isn't the full product range available at the webshop?
  What are the plans for the webshop?
  Where's the best online place to buy Spartan II in low volume?

DJ
--



Article: 85978
Subject: Xilinx LPT programmer help
From: Mouarf <toto@toto.de>
Date: Sun, 19 Jun 2005 19:45:25 +0200
Links: << >>  << T >>  << A >>
hello all,

I've built my own Xilinx parallel cable as described here: 
http://www.xilinx.com/support/programr/jtag_cable.pdf.

My version is here: http://cjoint.com/?gttCeFju7q (Vdd is adjusted so 
that Vcc is 5V exactly).

Unfortunately, it does not work even after electrical checks. After 
lauching "cable autodetect" (I've tried 2 ways: programmer connected to 
a custom minimalist xc9536 board and programmer only connect to power, 
the cable length should not be important to detect to programmer(?) ):

"Connecting to cable (Parallel Port - LPT1).
Checking cable driver.
  Driver windrvr6.sys version = 6.2.2.2. LPT base address = 0378h.
  ECP base address = 0778h.
Cable connection failed."

Since it does not work in Impact software (available in  webpack 7.1i 
under Win2000) I have a couple of questions to ask:

- should the parallel cable be detected by Impact when it is only 
connected to power (JTAG pins are left unconnected) or is it absolutely 
necessary to connect it to a CPLD/FPGA?

- my parallel port settings under BIOS and Win2K are "ECP DMA:3" is this 
correct (EPP needed?)?

- Impact allows to manually select the cable, is this a parallel cable 
III or IV?

- in this schematics, could 74HC125 be replaced by 74LS125?

- how is it possible to test the cable without FPGA/CPLD hardware?

Best regards.


PS: I don't want to buy any programmer neither build a programmer with 
different schematics since it should work, I would like to learn from my 
hardware building errors.

Article: 85979
Subject: FPGAs: Where will they go?
From: "lovesinghal" <lovesinghal@gmail.com>
Date: 19 Jun 2005 11:07:42 -0700
Links: << >>  << T >>  << A >>
Hi All,

I have some general questions related to FPGA.
What do people in this forum see is the future of FPGA 4 to 5 years
down the line?
What are the applications it is most widely used right now, and what
will be the applications that it will be highly used in a near future?
Currently, on average, a consumer (who may own cellphone, camera,
camcorder, ipod, etc.) owns zero FPGAs. Do you see this ratio of number
of FPGAs/consumer changing?

Or. Do you see power and clock speed to continue to remain as major
bottlenecks for FPGAs compared to ASICs in the next few years? Or will
the difference diminish in sub 65nm technologies? Or will it blow up??

There are two main advantages, as I see, of FPGAs over ASICs or
processors - ability to implement designs faster (shorter time to
market) and ability to perform easy "firmware updates". Will these two
factors ever influence the decisions of designers to switch to FPGAs
completely in the future?

If you are not as optimistic about FPGAs as I am sounding, what major
bottlenecks do you think will check FPGA growth?

I am starting my PhD in FPGAs (and looking for topics of research!?!)
and thus interested in knowing the future uses of FPGAs.

Thanks.


Article: 85980
Subject: Re: Interesting question on CPLD
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Sun, 19 Jun 2005 20:25:55 +0200
Links: << >>  << T >>  << A >>
"Peter Alfke" <alfke@sbcglobal.net> schrieb im Newsbeitrag
news:1119109675.203436.102620@g49g2000cwa.googlegroups.com...

> In Xilinx CoolRunner CPLDs the current consumed by each unused
> macrocell is already a small fraction of a microamp. Not worth any
> extra hoopla.

The OP said he want to power down some macrocells for some time and to do
clock gating to reduce power. I dont think he referes to macrocells that are
not used at all (which as you said draw almost no power since the are
automatically disabled by the software).

Clock gating is no problem, but do it properly(tm).
Power down, controled by logic at runtime inside the CPLD is not possible.

Regards
Falk






Article: 85981
Subject: Re: Interesting question on CPLD
From: "Peter Alfke" <alfke@sbcglobal.net>
Date: 19 Jun 2005 11:35:42 -0700
Links: << >>  << T >>  << A >>
O.K., so let me be more specific:
There is no way to physically detach anything inside the CoolRunner
from Vcc, but it's also not necessary. Static current consumption is
close to zero. As long as you prevent nodes from wiggling, they consume
practically no power. "Proper" clock gating is one way, but not the
only way. One can also gate the logic in front of the flip-flop (which
really is what Clock Enable does anyhow).
Peter Alfke


Article: 85982
Subject: Retrieving code from an old PAL
From: boothmultipler@hotmail.com
Date: 19 Jun 2005 11:51:21 -0700
Links: << >>  << T >>  << A >>
Dear All,
I have to duplicate a board that was designed by our company 18 years
ago. It has a PLS101 PLA on it. Unfortunately the old codes are lost.
Is it possible to recover code from the PAL by applying inputs and
getting the outputs?
The PLS101 PLA is 16x48x8, 16 inputs and 8 outputs.
What would be the time complexity for retrieving all the equations?
If I connect the PLA to a PC to get the equations, are ther any SW
tools to check the outputs and retrieve the equations?

All kind of help will be appreciated. 
Thanks


Article: 85983
Subject: Re: Interesting question on CPLD
From: Jim Granville <no.spam@designtools.co.nz>
Date: Mon, 20 Jun 2005 07:39:18 +1200
Links: << >>  << T >>  << A >>
Falk Brunner wrote:
> "Peter Alfke" <alfke@sbcglobal.net> schrieb im Newsbeitrag
> news:1119109675.203436.102620@g49g2000cwa.googlegroups.com...
> 
> 
>>In Xilinx CoolRunner CPLDs the current consumed by each unused
>>macrocell is already a small fraction of a microamp. Not worth any
>>extra hoopla.
> 
> 
> The OP said he want to power down some macrocells for some time and to do
> clock gating to reduce power. I dont think he referes to macrocells that are
> not used at all (which as you said draw almost no power since the are
> automatically disabled by the software).

Not quite.

> Clock gating is no problem, but do it properly(tm).
> Power down, controled by logic at runtime inside the CPLD is not possible.

There are different CPLD cores :

a) Those that use Wide AND sense amplifiers, with FLASH Logic fuses, 
have high currents ( tens of mA) and they can save power by power-down. 
Altera and Atmel have a PD pin, and Atmel's L models also have 
edge-transition shutdown - they wake up/sense logic/clock MC/sleep 
again.  Their static Icc is some uA

b) Those that have CMOS trees and load the steering/fuse logic, at power 
up. These have no run time FLASH read currents, and are faster, but do 
have a finite startup time. [and possible RAM corruption issues ? ]
  The Coolrunner CPLDs are in this family, as are the new Lattice 4000,
and the MAX II.
  Static Iccs in these are in the some uA region.

All CPLDs have clock enables, but that saves only the Q power, and not 
the Clock Tree drive power.

So the answer to the OP, varies with the core-model.
Individual run-time MC Power control is not available to the user, but 
device wide and automatic/inherent power control, is in there already.

-jg


Article: 85984
Subject: Re: AbusivepPricing information in marketing publications
From: Kolja Sulimma <news@sulimma.de>
Date: Sun, 19 Jun 2005 21:46:31 +0200
Links: << >>  << T >>  << A >>
I have no problems with large volume pricing. It is useless for most
users, but it is valid.
I (and the UWG) have a problem with disguising future prices as current
prices.
Actually the text has improved a litte. The Vortex-4 press release had
the formulation "are available *now* for under...", but even without the
word "now" the use of present tense is very far streched for 2006.

Kolja Sulima

John_H schrieb:
> The text ALWAYS clearly states what the pricing timeframe and quantity
> are for the price.
> 
> Engineers looking to design in a new part in large quantities are
> typically looking for production a little ways out.  I would prefer to
> see 1H2006 pricing, but still... they make it clear.
> 
> The pricing method is used by too many vendors so why should Xilinx say
> this snazzy new part is available for $XX now in small quantities when
> others are advertizing the "mature volume" pricing?
> 
> If you know what the "typical markup" is for early adoption of a device
> or for small quantities of the part as purchased by your company, you
> can get a ballpark to the pricing without having to call for specifics.
> 
> I'm surprised that the UWG makes illegal the practice of giving a price
> where the price is clearly marked with a note and that note supplies the
> timeframe and quantitiy.  This is misleading why? 
> We do have market
> realities to consider, after all.
>Kolja Sulimma wrote:
> >There are three correct formulations possible for these facts:
> >- The devices will be available for under US$2.

Article: 85985
Subject: Re: FPGAs: Where will they go?
From: Jim Granville <no.spam@designtools.co.nz>
Date: Mon, 20 Jun 2005 07:53:37 +1200
Links: << >>  << T >>  << A >>
lovesinghal wrote:

> Hi All,
> 
> I have some general questions related to FPGA.
> What do people in this forum see is the future of FPGA 4 to 5 years
> down the line?
> What are the applications it is most widely used right now, and what
> will be the applications that it will be highly used in a near future?
> Currently, on average, a consumer (who may own cellphone, camera,
> camcorder, ipod, etc.) owns zero FPGAs. Do you see this ratio of number
> of FPGAs/consumer changing?
> 
> Or. Do you see power and clock speed to continue to remain as major
> bottlenecks for FPGAs compared to ASICs in the next few years? Or will
> the difference diminish in sub 65nm technologies? Or will it blow up??
> 
> There are two main advantages, as I see, of FPGAs over ASICs or
> processors - ability to implement designs faster (shorter time to
> market) and ability to perform easy "firmware updates". Will these two
> factors ever influence the decisions of designers to switch to FPGAs
> completely in the future?

What about the NRE costs of ASICs ?

> 
> If you are not as optimistic about FPGAs as I am sounding, what major
> bottlenecks do you think will check FPGA growth?
> 
> I am starting my PhD in FPGAs (and looking for topics of research!?!)
> and thus interested in knowing the future uses of FPGAs.
> 
> Thanks.

  You can forecast FPGA trends a little by looking at the foundres.

eg Look up the recent PR by TSMC, that their first release devices on
65nm will be power optimised, not speed optimised, driven by customer 
demand.

  Also, a new entrant 'mix' in the FPGA arena comes from ST,
http://www.st.com/stonline/books/ascii/docs/11335.htm

  They call this a "RECONFIGURABLE MICRO-CONTROLLER WITH DUAL MAC DSP"
which has 16MBit DRAM, 300MHz ARM9, 600MHZ DSP, and a 200K FPGA,
Dual ethernet, ADC/DAC....

  FPGAs have been moving from custom-cell-less ( simple sea of LCs ) to
include more hard silicon blocks, like multipliers, RAM, DSP kernal 
cells, and even uP.
  That trend will continue, & the 'Gate Array' name no longer strictly
applies.

-jg


Article: 85986
Subject: Re: Retrieving code from an old PAL
From: Jim Granville <no.spam@designtools.co.nz>
Date: Mon, 20 Jun 2005 09:59:18 +1200
Links: << >>  << T >>  << A >>
boothmultipler@hotmail.com wrote:

> Dear All,
> I have to duplicate a board that was designed by our company 18 years
> ago. It has a PLS101 PLA on it. Unfortunately the old codes are lost.
> Is it possible to recover code from the PAL by applying inputs and
> getting the outputs?
> The PLS101 PLA is 16x48x8, 16 inputs and 8 outputs.
> What would be the time complexity for retrieving all the equations?
> If I connect the PLA to a PC to get the equations, are ther any SW
> tools to check the outputs and retrieve the equations?
> 
> All kind of help will be appreciated. 
> Thanks

I just checked and the TopMAX programmer from eetools can read a PLS101, 
and shows no Secure option. It will also vector test this device.
Other device programmers will be similar.

Thus you can probably get the fuse info, directly, and simply program 
new devices.  JDR still show stock ;)

If you need to move to a new device, you could work from this fuse into,
with an old PLS101 data sheet, and your circuit diagrams.
The vector test feature allows you to confirm, as far as your test
coverage goes :)

Candidate replacement devices ( assumes you want to keep ~package,
and 5V ) can be found at http://www.anachip.com/eng/product/pld.php
or you could look at ATF1502ASL from Atmel, different package, but
lower power.

-jg



Article: 85987
Subject: Re: Microblaze address space and variables
From: John Williams <jwilliams@itee.uq.edu.au>
Date: Mon, 20 Jun 2005 08:14:11 +1000
Links: << >>  << T >>  << A >>
Hi Marco,

Marco wrote:

> I must create a memory for a display lcd. This is part of a microcontroller
> based on microblaze.
> 
> I thought to do it using a variable, a matrix:  display[X][Y]  (the software
> video memory).
> 
> In this way, working with my variable I could edit hardware video memory.
> 
> But I'm not able... how may I do it?

#define HEIGHT ...
#define WIDTH ...

unsigned char *display[HEIGHT][WIDTH] = (unsigned char *)0x77200000;

display[y][x] = ...

Regards,

John

Article: 85988
Subject: use lattice and actel synplify together...
From: Jedi <me@aol.com>
Date: Sun, 19 Jun 2005 22:23:44 GMT
Links: << >>  << T >>  << A >>
Is it possible to have for each tool an own license file
path set?

Lattice ispLever Base with synplify bites Actel Libero Platinum
with synplify since each version of synplify doesn't like
the other license file...


thx in advance
jedi

Article: 85989
Subject: Re: BGA Rework/Prototype Placement Anyone?
From: "John Adair" <loseitintheblackhole@blackholesextreme.co.uk>
Date: Mon, 20 Jun 2005 00:32:44 +0100
Links: << >>  << T >>  << A >>
Very early days at the moment on this one but probably looking at before tax 
price of about 30 ($50) for something like a XC3S1500. Generally we would 
be aiming to keep the cost down as one of the principal markets would be 
hobby electronics. One of the debates we are having is what to add in 
addition to the FPGA. Mainly this revolves arround fitting regulators for 
Vccint and Vccaux. Having a straight 3V3 drop-in solution is nice for the 
market but the more we add the more the cost and where do you stop.

The I/O count as yet is not settled but we are likely to using the FG456 
package to keep it common with our other products. It does add a bit to cost 
but the substantially better SSO performance, over something like the PQ208 
package, is worth having even if the PCB limitations reduce the benefit. Not 
all the I/O is likely to available but wait and see how well we do. Whatever 
we do it will be 0.1 inch pitch pin-out so you can even fit it to stripboard 
(do I hear a few people shuddering).

Adding more than the above starts to look like a development board and we 
are going to cover this very low end market with our next board release once 
the dust has settled on our MINI-CAN launch. The next board will incorporate 
some very low cost design techiques and will give us a lot of info on what 
we could get away with on the PGA module. We are aiming at a 4-layer 
approach on this board to reduce the cost but keep most of the performance. 
Our current MINI-CAN is 8 layer and Broaddown2 is 10 layer so you can make 
your own guess on the price point of the new board.

John Adair
Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development 
Board.
http://www.enterpoint.co.uk

"Mike Harrison" <mike@whitewing.co.uk> wrote in message 
news:tcj5b1hkrlh9ld2d4vrv0jk50k5fpbb4qe@4ax.com...
> On Fri, 17 Jun 2005 11:04:01 +0100, "John Adair"
> <removethisthenleavejea@replacewithcompanyname.co.uk> wrote:
>
>>We have a product coming to assist in this area. Based on Spartan-3 in 
>>FG456
>>it consists of a PGA style board with the Spartan-3 in the middle. This
>>module is aimed at hobby or small run board builders that don't want the
>>setup charges of BGA lines.
>
> Sounds like a really good idea - having started playing with the S3 devkit 
> I keep having ideas of
> other fun, low-volume or 1-off things that I could use an FPGA for if it 
> were more easily
> connect-to-able.
>
> Do you have a rough spec yet ? Number of pins, size, price etc. ?
>
> You may have already thought of some/all of these, but a few 
> suggestions...
>
> Would be nice if the pinout is arranged such that you can easily trade off 
> required number of layers
> needed on the host PCB against pins used, e.g useable on a 2-layer PCB if 
> you don't need a lot of IO
> pins.
>
> Having a power connector on the board would be useful, to reduce the 
> amount of big tracks you'd need
> (and allow a 2-layer host PCB for less demanding applications). Perhaps 
> have JTAG and power
> connection pins along an edge with some perforations, so that can be 
> snapped off if you want minimum
> module size, or left on to make it easier to use with simpler host boards.
> 1.5 and 2.5V regulators on board ?
>
> Any chance the footprint can be the same as one of the various PC CPUs, so 
> sockets can be found
> cheaply ?
>
> Probably don't need seperately accessible connections to all of the IO 
> bank supplies, but at least
> one seperately connectable bank would be nice for when you want a few 
> 'odd' standards that need a
> different supply, e.g. lvds.  Maybe have some solder-bridge type link 
> options for this?
>
> Footprint for a user-fittable  SMD oscillator module or two  so high-speed 
> clocks can stay on the
> module.
> 



Article: 85990
Subject: Re: Retrieving code from an old PAL
From: cs_posting@hotmail.com
Date: 19 Jun 2005 16:45:46 -0700
Links: << >>  << T >>  << A >>
No non-ouput registers (no registers at all in that device) means no
hidden state.  So you can just read it out as eight 64k x 1 roms.   And
"compress" the data.  First by eliminating any inputs that don't effect
a given output.  Then by identifying all local areas where changing one
or several inputs does not change the output.  Write a product term for
each such group anding the state of the inputs that do mattter, then or
all such product terms together to create that output.  It's a fun
undegrad exercise for 4-input devices, circling the product terms on a
little grid of two bits by two bits counted in grey code  - but for 16
inputs and 8 outputs you want software...

Of course the tools exist as the Jim mentioned.  But you could also do
it in a long afternoon with a pc printer port, an 8255 for I/O
expansion, and the programming language of your choice.


Article: 85991
Subject: Re: Ideal CPU for FPGA?
From: "Piotr Wyderski" <wyderskiREMOVE@ii.uni.wroc.pl>
Date: Mon, 20 Jun 2005 02:23:20 +0200
Links: << >>  << T >>  << A >>
dave wrote:

> What type of CPU architecture are FPGAs more suited to implement?

Primitive CPU architectures are easier to implement on an FPGA chip. ;-)
FPGAs generally have problems with multiport memories -- it's easy to
implement a 1-write N-read port memory bank, but if the number of write
ports is higher, you will have a big problem. And since such blocks are
commonly used by DSPs (and remaining architectures that exploit
massive parallelism, but not VLIW-like, i.e. with complex inter-stage
datapath dependencies), its hard do implement them using on FPGA.

    Best regards
    Piotr Wyderski


Article: 85992
Subject: Need Application note for Motion Controller with Xilinx
From: "Leeinhyuk" <engtech1@kornet.net>
Date: Mon, 20 Jun 2005 12:44:28 +0900
Links: << >>  << T >>  << A >>
Hello sir
I would like to realize motion controller with Xilinx CPLD chip.
Does anyone know an application note for motion controller with Xilinx CPLD
or FPGA?
I hope to receive with email leeih@chollian.net
Best regards
IH Lee




Article: 85993
Subject: Re: FPGAs: Where will they go?
From: "Marc Randolph" <mrand@my-deja.com>
Date: 19 Jun 2005 20:54:20 -0700
Links: << >>  << T >>  << A >>


lovesinghal wrote:
> [...]
> What do people in this forum see is the future of FPGA 4 to 5 years
> down the line?
> What are the applications it is most widely used right now, and what
> will be the applications that it will be highly used in a near future?
> Currently, on average, a consumer (who may own cellphone, camera,
> camcorder, ipod, etc.) owns zero FPGAs. Do you see this ratio of number
> of FPGAs/consumer changing?

Although on average it is indeed very, very low, it's already more than
zero:

http://groups.google.com/groups?&q=loewe+xelos+fpga

Now, it was wondered in that and other threads if the FPGA was a
permanent fixture in the product, or a stop-gap due to high profit
margins and fast design rollout (such that once the design has settled
down, they will likely switch to an ASIC?).

> Or. Do you see power and clock speed to continue to remain as major
> bottlenecks for FPGAs compared to ASICs in the next few years? Or will
> the difference diminish in sub 65nm technologies? Or will it blow up??

I assume Altera does this as well, but Xilinx likes to throw around
meaningless comparisons about how much it would cost their customer(s)
do to a design in the current state-of-the-art (90 nm, for example).
What they neglect to mention is that you would likely not need to use
anything close to that to achieve your performance targets (if you
design was gong to work in an FPGA), so your NRE's would likely be
considerably lower than theirs.  Note that I am not saying anything
about which is actually cheaper for a given design.  The actual NRE or
per-piece prices are so highly variable from one design to another that
I dont think anything except a formal quote on a particular design
would be able to tell you the answer.

> There are two main advantages, as I see, of FPGAs over ASICs or
> processors - ability to implement designs faster (shorter time to
> market) and ability to perform easy "firmware updates". Will these two
> factors ever influence the decisions of designers to switch to FPGAs
> completely in the future?

There's also resource availabilty (money and man-power, in addition to
design time, as you mentioned): at least for smaller design firms, the
obvious answer is to use FPGA's initially, for all the usual reasons.
But after it has hit the market, do you dedicate your scarce resources
to respinning that part into an ASIC, or to develop the next best thing
that might sell even better?  You might take a hit of a few percent of
the gross profit margin, but in the grand scheme of things, perhaps
that is the smarter thing to do.

> If you are not as optimistic about FPGAs as I am sounding, what major
> bottlenecks do you think will check FPGA growth?

Despite the above statements, I'm fairly optimistic that overall FPGA
sales will continue to grow... I think the $/LUT has dropped low enough
that companies will continue to go for the FPGA's for all the usual
reasons.

> I am starting my PhD in FPGAs (and looking for topics of research!?!)
> and thus interested in knowing the future uses of FPGAs.

A few ideas were thrown around on a related topic recently:
http://groups.google.com/groups?q=future+fpga

Good luck,

   Marc


Article: 85994
Subject: Re: Idea exploration - Image stabilization by means of software.
From: "Jon Harris" <jon_harrisTIGER@hotmail.com>
Date: Sun, 19 Jun 2005 21:43:20 -0700
Links: << >>  << T >>  << A >>
"Anton Erasmus" <nobody@spam.prevent.net> wrote in message
news:1119169974.ea68157269af093d1f453f607f949e3c@teranews...
> On Sun, 19 Jun 2005 00:57:12 -0700, "Jon Harris"
> <jon_harrisTIGER@hotmail.com> wrote:
>
> >> "Anton Erasmus" <nobody@spam.prevent.net> wrote in message
> >> news:1119000420.d54828b53b9bcd51f76b2b5b640103a6@teranews...
> >> >>
> >> > I have read a bit about the astronomical image processing mention in
> >> > one of the other posts. One thing that came up quite often, is that
> >> > CCD sensors are linear. i.e. double the exposure time gives double the
> >> > energy recieved. (They do not mention CMOS, but it is probably the
> >> > same.)
> >> > I agree that blurring occurs when taking a single photo when the
> >> > camaera is moved and the exposure is to long. If one can say take in
> >> > stead of 1x 2sec exposure, take 20x 0.1 sec exposures, and stack them
> >> > into a single picture in software, one should end up close to the
> >> > exposure level of the 2sec picture, but without the blur.
> >
> >I'm assuming that the software wouldn't simply stack the pictures exactly on
top
> >of each other, but move each one around slightly so as to best align them.
> >
> >One potential difficulty is the time it takes to read out the data from the
> >sensor and "clear" it for the next exposure could be significant, especially
for
> >very short exposures.  I don't know specifics, but for example, it might take
> >3-4 seconds to take your 2 seconds worth of exposure.  Clearly that is not a
> >good thing!
>
> Lots of cheap digital cameras can take short mpeg movies, so it cannot
> be that slow for the sensor to recover.
> If someone has better information regarding the technical specs of
> these devices, as well as what the theoretical limits are, it would be
> quite nice to know.

Keep in mind that the mpeg movies are at best 640x480 at 30 frames per second.
30 fps corresponds to a frame time of 33.3 milliseconds.  Is 640x480 adequate
for the still photography being discussed?  I doubt it.  Sorry I don't have
specifics on the technical specs, so I am inferring the approximate order of
magnitude of the speed.  If someone else has better info, please chime in, but
it seems to me that you can't get too much more than 30 fps at ~VGA resolution
out of today's consumer camera technology.  (Maybe the HD camcorders can do a
bit better, but still nothing close to the megapixels in a few milliseconds you
would want to use the original idea ("Image stabilization by means of
software.").

> >> > In the astronomical case, the "short" exposure pictures are in minutes
> >> > for a total exposure time of hours. Of course the subject must not
> >> > move during the "short" exposure time.
> >
> >Another difficulty I see is that when you have a severely underexposed
picture,
> >you are going to lose a lot of shadow detail since it ends up below the noise
> >floor .  A perfectly linear sensor with no noise wouldn't have this problem,
but
> >real-world ones certainly do.  Consider, for example, a picture that has a
> >black-to-white gradient.  When exposed normally, the camera records levels
from
> >0 (full black) to maximum (full white).  But with an exposure that is 1/20 of
> >the proper value, much of the dark gray portion will be rendered as 0 (full
> >black). Even after you add the 20 exposures together, you still get full
black
> >for those dark gray portions.  So everything below a certain dark gray level
is
> >clipped to full black.
>
> Yes one would need a sensor with a low noise floor. The lower the
> better. AFAIK the more pixels they pack into a sensor, the higher the
> noise floor. Currently the whole emphasis is on producing sensors with
> more pixels. If the emphasis was on producing sensors with very low
> noise floor, I am sure a suitable sensor can be developed.

Yes, if you only required, say a 1MP image, this would certainly help, both in
terms of noise and ability to read out the data quickly.



Article: 85995
Subject: Re: comp.arch.fpga.<mfr>
From: Jeremy Stringer <jeremy@_NO_MORE_SPAM_endace.com>
Date: Mon, 20 Jun 2005 17:29:09 +1200
Links: << >>  << T >>  << A >>
Jon Beniston wrote:
> comp.arch.fpga.cpu might be a good idea. Somewhere for all the NIOS &
> MicroBlaze queries.

I'd second that :)  It's one of the few major topics that generate quite 
a lot of traffic, while being quite distinctly separate from the other 
topics discussed here - different toolflows, compiler issues etc.  If 
you were to consider a split, this would seem to be an obvious one.

I don't think separate hierarchies for vendors would benefit anyone 
particularly though - a lot of stuff is quite general.  I think this was 
covered elsewhere in this thread.

My 2c
Jeremy

Article: 85996
Subject: ISE 7.1 Service Pack 2 - Ready yet?
From: Jeremy Stringer <jeremy@_NO_MORE_SPAM_endace.com>
Date: Mon, 20 Jun 2005 18:45:38 +1200
Links: << >>  << T >>  << A >>
I'm starting a new project at the moment, and I'm looking at upgrading 
to ISE 7.1, since I prefer not to change synth/par tool versions 
mid-project.  I noted that a number of people complained about 7.1 when 
it first came out, but also noted that Service Pack 2 is out now.  Can 
anybody comment on the state of ISE 7.1 at the moment?

Thanks,
Jeremy

Article: 85997
Subject: Re: damage Atmel AT40k/AT94k with wrong bitstream?
From: Adam Megacz <megacz@cs.berkeley.edu>
Date: Mon, 20 Jun 2005 00:19:39 -0700
Links: << >>  << T >>  << A >>

"Peter Alfke" <alfke@sbcglobal.net> writes:
> A wrong FPGA bitstream can create massive internal contention, which

This is not ALWAYS true.  It was untrue for the XC6200 sieres:

  http://www.fpga-faq.org/archives/10625.html#10627

But that post (which I just found) explains *why*, and I know that the
Atmel chips don't share the same feature (single source per wire).

  - a

Article: 85998
Subject: Re: comp.arch.fpga.<mfr>
From: "Symon" <symon_brewer@hotmail.com>
Date: Mon, 20 Jun 2005 02:17:46 -0700
Links: << >>  << T >>  << A >>
Bob,
Now you're talking! How about
.good-book-about

.i-cant-get-linux-to-work-with.impact
.i-cant-get-linux-to-work-with.ise
.i-cant-get-linux-to-work-with.edk
.i-cant-get-linux-to-work-with.anything

.i-cant-get-any.spartan3
.i-cant-get-any.virtex4
.i-cant-get-any.satisfaction

To help folks filter stuff, I'd be happy to include [XILINX] or [ALTERA] in 
the subject line of posts specific about a vendor, but extra groups is a 
rubbish idea, IMO.
Cheers, Syms. 



Article: 85999
Subject: How to reset a PLB/OPB Peripheral
From: "Joey" <johnsons@kaiserslautern.de>
Date: Mon, 20 Jun 2005 12:43:25 +0200
Links: << >>  << T >>  << A >>

Hi

I would like to know how we can reset an OPB/PLB Peripheral during runtime.

Thank you
Joey





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