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looks like Chess and FPGAs are making news all around, esp Hydra, Alphadata, and xcell article http://www.xilinx.com/publications/xcellonline/xcell_53/xc_hydra53.htm How long before someone builds a lowend version spartan3 version with cpu and chess engine inside, no external H8 etc. What would the ELO ranking be? johnjakson at usa dot comArticle: 86351
Finally... The last 4 days working with NIOS2 since I can't upgrade my subscription... ...or is there an opensource alternative like the "utnios" before? rickArticle: 86352
dear i am using 'unisim' for Xilinx component for VHDL "simulation" in Modelim. So, as far we know the name of the component, no VHDL description (implementation) was required, which was convenient. Now I am wondering whether it is possible to - synthesize Xilinx component uing unisim only, Should I use 'coregenerator' to synthesize? Thankyou in advanceArticle: 86353
"Ulf Samuelsson" <ulf@atmel.nospam.com> writes:
>>> Hey, does anybody know if you can damage Atmel's newer FPGAs with a
>>> bad bitstream (ie vdd-to-ground contention)?
> AT94Sxx Secure FPSLIC?
Sure; I'm working mainly with the AT94xx, which is just an AT94Sxx
without the EEPROM. Which, in turn, is just an AT40xx plus the AVR
microcontroller. Atmel hasn't really changed their fabric since '98.
- a
--
"I didn't see it then, but it turned out that getting fired was the
best thing that could have ever happened to me. The heaviness of
being successful was replaced by the lightness of being a beginner
again, less sure about everything. It freed me to enter one of the
most creative periods of my life."
-- Steve Jobs, commencement speech at Stanford, June 2005
Article: 86354pasacco wrote: > dear > > i am using 'unisim' for Xilinx component for VHDL "simulation" in > Modelim. So, as far we know the name of the component, no VHDL > description (implementation) was required, which was convenient. > > Now I am wondering whether it is possible to > > - synthesize Xilinx component uing unisim only, Yes. You do not actually have to synthesize the unisim components, and I never do (though I think they are synthesizable). Everything in the unisim library is a primitive, or a "primitive" macro. The Xilinx PAR (place and route) software understands the unisim names, and it will insert the proper construct. > > Should I use 'coregenerator' to synthesize? > Coregen is used to create non-primitive cores. That is completely different from the unisim library. If you are not used coregen generated cores in your simulation, then you won't use them in your synthesis.Article: 86355
kierenj wrote: > Hi there, > > Originally I didnt include all the code since there are several > modules, and lots of lines in them. I've changed the state machine to > use a case statement and symbolic names. > (Yes, it is intentional, after the initial power-up reading I'd like it > to go through the states 0, 1, and stay at 2). > The full source is attached below. I suggest you code your FSM with an asynchronous reset pointing to INIT. Otherwise, there is no state leading to Init, and the extremely clever sythesizer in Quartus II might have noticed... - Never an FSM without a reset. - Do NOT initialize variables at declaration ! /most/ synthesis tools will simply ignore this. and make sure you don't mix up signals from different clock domains without proper resync. Hope this helps, Bert CuzeauArticle: 86356
Jedi wrote: > Finally... > > The last 4 days working with NIOS2 since I can't upgrade > my subscription... Why ? are you a hobbyist ? In the Education, you should have no problem, since Altera policy is quite generous. In the Industry, the investment is modest and very much worth it IMO. If you are a hobbyist, I think the eval mode lets you generate systems that work for some time and / or in a tethered configuration ? I don't think there is today a better/cheaper/nicer SOPC environment than NIOSII, but it's a very personal opinion indeed. If you've used it, I'm sure you know what I mean :-) Bert CuzeauArticle: 86357
info_ wrote: > Jedi wrote: > >> Finally... >> >> The last 4 days working with NIOS2 since I can't upgrade >> my subscription... > > > Why ? > are you a hobbyist ? No...company.. But according to "EBV" it is too expensive to open me up as a customer (o; > In the Education, you should have no problem, since Altera policy > is quite generous. > In the Industry, the investment is modest and very much worth it IMO. > > If you are a hobbyist, I think the eval mode lets you generate systems > that work for some time and / or in a tethered configuration ? I know that...but would not work in my case for building Linux tools. > > I don't think there is today a better/cheaper/nicer SOPC environment > than NIOSII, but it's a very personal opinion indeed. If you've > used it, I'm sure you know what I mean :-) rickArticle: 86358
Aah brilliant, nowhere near the amount of warnings/errors - I'll download it into my board and see what happens! I had been advised that async resets were bad, and that you can assume that registers will ALWAYS power-up with 0. When Quartus complained that it was making registers high because I hadn't specified a power-up value, I thought I'd try initialisers... Thanks.. I'll let you know how it goes! Cheers!Article: 86359
kierenj wrote: > Aah brilliant, nowhere near the amount of warnings/errors - I'll > download it into my board and see what happens! > > I had been advised that async resets were bad, and that you can assume > that registers will ALWAYS power-up with 0. And that is true and I disagree with the reset advise. It usually a waste of resources if you don't need it. I in particular *never* use asynchronous reset, thought I can see the use in ASICs. > When Quartus complained > that it was making registers high because I hadn't specified a power-up > value, I thought I'd try initialisers... Initializers are ignored for synthesis -- You used non-zero initializers? I usually add zero initializers to make simulation match what you get in the FPGA. TommyArticle: 86360
Uwe Bonnes wrote: > Jim Granville <no.spam@designtools.co.nz> wrote: > ... >> Imagine a stacked die FPGA, with a large VFast SRAM, and Config device ? > > You're dreaming :-) Of course, but it is realistic of what might be on our desks in 2-3 yrs time ? [Which means we should be thinking about it now, and if one FPGA vendor sees this, and the others miss it == big lead] Other industries have this stacked die, today - so this allows some inertia in the smaller, more inwardly looking, FPGA sector :) -jgArticle: 86361
JJ wrote: > looks like Chess and FPGAs are making news all around, esp Hydra, > Alphadata, > > and xcell article > > http://www.xilinx.com/publications/xcellonline/xcell_53/xc_hydra53.htm Interesting - but no info on the size of the Knowledge database. > How long before someone builds a lowend version spartan3 version with > cpu and chess engine inside, no external H8 etc. What would the ELO > ranking be? You mean truly one chip, or with off-chip database storage ? Once they are able to claim to better the best human players, then the goals can move to : ** First Computer cluster smaller/lighter than its human opponent to win :) ** First Computer cluster drawing less power than its human opponent ( ~100W? ) to win - that will be harder still.... -jgArticle: 86362
Tommy Thorn wrote: > I in particular *never* use >asynchronous reset, thought I can see the use in ASICs. Enable FF on a three state bus might need one. Or a control line that needs to be set to a level when the clock isn't running. -- Phil Hays Phil-hays at posting domain (- .net + .com) should work for emailArticle: 86363
Very neat, thank you Charles. "Charles Gardiner" <site_blackhole@trellisys.ie> wrote in message news:d9i1qi$45u$04$1@news.t-online.com... > And, you can check your result against the web-tool output at > > http://www.easics.com/webtools/crctool > >Article: 86364
Hi, I am implementing a particular voice compression algorithm in a Spartan 3 FPGA and am directly instantiating Xilinx primatives to get the best (and most reliable) performance, I hope. The spartan 3 datasheet provides a "Figure 6: Simplified Diagram of the Left-Hand SLICEM". This info is good but I'm wanting more detail than is provided in this diagram. The datasheet hints there is more "Options to invert signal polarity .... are not shown". Is there any documentation that gives an even more detailed view of the Spartan 3 Slice? (I've googled without success so far.) I suspect FPGA Editor will tell me more but I don't have access to that yet. Also I see the ISE 7.1i Timing Analyser pops up some nice diagrams of the slice when one clicks on some of the hyperlinks in the timing analysis report. These diagrams show invertor options on some of the slice input signals but I can't help wondering if there are other options? Regards AndrewArticle: 86365
Ben Bradley wrote: > Kris Neot wrote: >>Does this idea work? :) > > > Yes, probably, sort of. Wanna bet? There are six motion axes. How many will the ball track? Jerry -- Engineering is the art of making what you want from things you can get. ŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻArticle: 86366
We are not just inward-looking. Of course we also look at the possibilities of stacked die. But the applications flexibility that makes FPGAs so great, works against die stacking. Pentiums and cell phones are more "single purpose" where the manufacturer can aim at a well-defined application without too many variations. FPGAs are used all over the place, in all sorts of constellations. Which one should we concentate on, which one to ignore? Just my opinion... Peter AlfkeArticle: 86367
If you use a LUT as a 16-bit ROM (its normal application), then there is no benefit whatsoever in the ability to invert any or all of the 4 inputs, or the output. Anything you might do with inverters can be done by just redefining the 16 LUT bits. Clock enable Write Enable and Clock polarity may sometimes "need" inverters, but even that is rare. The LUT is a very versatile tool; that's why we are so loyal to it... Peter AlfkeArticle: 86368
Peter Alfke wrote: > We are not just inward-looking. Of course we also look at the > possibilities of stacked die. > But the applications flexibility that makes FPGAs so great, works > against die stacking. > Pentiums and cell phones are more "single purpose" where the > manufacturer can aim at a well-defined application without too many > variations. FPGAs are used all over the place, in all sorts of > constellations. Which one should we concentate on, which one to ignore? > Just my opinion... Neither Configuration memory, nor fast SRAM are single purpose, they are used all over the place.... and a key point of this, is it does NOT impact those FPGA users who do not want it (unlike the present on die fruit-fest)... Consider : The price of Config memory is (at last) moving to match mainstream SPI memory devices, some vendors even employ std SPI memory. Config within the package can raise the security-level hot button. Choices of "how much config?" are relatively simple, falling into two classes - everyone needs enough to load the device itself, and some need more to also hold the boot code of a soft CPU. Soft CPUs have a BIG drawback of needing off-chip code memory. Think of 256K-512K-1MBytes of 2-3ns SRAM, and the EMC and Speed benefits the average Soft CPU user could reap from using this ? -jgArticle: 86369
Jedi wrote: > Finally... > > The last 4 days working with NIOS2 since I can't upgrade > my subscription... > > ...or is there an opensource alternative like the "utnios" before? > > > rick Did you look at www.opencores.org ? I don't think there is a nios replacement, but there sure are many alternatives ... Regards, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and Synthesis ****** Certified USB 2.0 HS OTG and HS Device IP Cores ******Article: 86370
Hi all, There is a problem on How to write FSM in Verilog(http://www.asic-world.com/tidbits/verilog_fsm.html). Most synthesis tools recommend second "Using Two Always Blocks" style. But I would like to use third "Single Always" style. It seems more compact. What's the pros and cons between the two styles? I see that the third style may have state transition latency. But does the third style gain higher frequency and shorter critical path? Thanks! Best regards, DavyArticle: 86371
Hi Peter, Thanks for your comments, I understand the LUT implements any boolean function of 4 variables(as well as 16x1 RAM, SRL, etc of course). But say I have a slice where the F-Lut and FFX(flop) are already used, and furthermore it is the F-LUT output that is routed to the FFX D input. If the underlying slice hardware provides for an invertor on the BX path say - then don't I have a "free" additional invertor that can be used with BX as the input and BXOUT as the output? This is additional logic than what is already provided by the LUT. In case anyone is interested, what I am actually trying to do is take a 14 bit +ve number and convert it to floating point. For example, to find the exponent the first step is to use a priority encoder to find the position of the most signficant bit. I use the carry chain configured for "propagate-kill". Starting from the MSB a 1 is propagated down the carry chain until an input bit with a 1 is encountered, from then on the carry chain propagates a 0. One LUT controls the MUXCY carry propagation. The other LUT AND's the input bit and the input carry to generate the priority encoded output. I then encode the 14 bit priority encoded value to 4 bits that represent the exponent. I can do that encoding with 2 Luts per bit. I wish I could find some way to exploit the FAND, XORF or F5MUX to reduce the amount of LUTS required..... Hmm if the inputs to the FAND could be inverted then don't we have a "free" 2 input LUT also in the slice? Of course that would make the carry chain unusable in that slice. Regards Andrew Peter Alfke wrote: > If you use a LUT as a 16-bit ROM (its normal application), then there > is no benefit whatsoever in the ability to invert any or all of the 4 > inputs, or the output. Anything you might do with inverters can be done > by just redefining the 16 LUT bits. > Clock enable Write Enable and Clock polarity may sometimes "need" > inverters, but even that is rare. > The LUT is a very versatile tool; that's why we are so loyal to it... > Peter AlfkeArticle: 86372
Rudolf Usselmann wrote: > Jedi wrote: > > >>Finally... >> >>The last 4 days working with NIOS2 since I can't upgrade >>my subscription... >> >>...or is there an opensource alternative like the "utnios" before? >> >> >>rick > > > Did you look at www.opencores.org ? > Of course (o; > I don't think there is a nios replacement, but there sure are > many alternatives ... Only have this old utnios design which based on nios32 and then the distribution was prohibited by Altera... But speaking of...has anybody ever done a CPU SOPC component? rickArticle: 86373
"Jedi" <me@aol.com> schrieb im Newsbeitrag news:SnNve.45$v17.23@read3.inet.fi... > Rudolf Usselmann wrote: > > Jedi wrote: > >>Finally... > >> > >>The last 4 days working with NIOS2 since I can't upgrade > >>my subscription... > >> > >>...or is there an opensource alternative like the "utnios" before? > >> > >>rick > > > > Did you look at www.opencores.org ? > > > Of course (o; > > > I don't think there is a nios replacement, but there sure are > > many alternatives ... > > Only have this old utnios design which based on nios32 and then > the distribution was prohibited by Altera... > > But speaking of...has anybody ever done a CPU SOPC component? > > rick what you mean was prohibitied by Altera? utnios is is still available I just checked! What Altera DID try to prohibit was, well they told me that I can promote a sell NIOX - a NIOS-2 compatible core. So I removed the public links to NIOX from my website. there is nothing at opencores that could be used as nios-2 replacement, the only opensource environment that i would consider is LEON3/GRLIB, and that is not hosted on opencores. I have tried to make SOPC processors components and also EDK processor components with EDK I succeeded, I had a AVR processor that was possible to use in EDK/XPS with SOPC it should also be possible, actually it does exist, and is available from altera the Avalon microsequences, its a processor component for SOPC, with full sources, so you can use it as base to design your SOPC processors... antti news://news.openchip.orgArticle: 86374
Antti Lukats wrote: > "Jedi" <me@aol.com> schrieb im Newsbeitrag > news:SnNve.45$v17.23@read3.inet.fi... > >>Rudolf Usselmann wrote: >> >>>Jedi wrote: >>> >>>>Finally... >>>> >>>>The last 4 days working with NIOS2 since I can't upgrade >>>>my subscription... >>>> >>>>...or is there an opensource alternative like the "utnios" before? >>>> >>>>rick >>> >>>Did you look at www.opencores.org ? >>> >> >>Of course (o; >> >> >>>I don't think there is a nios replacement, but there sure are >>>many alternatives ... >> >>Only have this old utnios design which based on nios32 and then >>the distribution was prohibited by Altera... >> >>But speaking of...has anybody ever done a CPU SOPC component? >> >>rick > > > what you mean was prohibitied by Altera? utnios is is still available I just > checked! > It was offline for a while..believe me (o; Yes..back at: http://www.eecg.toronto.edu/~plavec/utnios.html > What Altera DID try to prohibit was, well they told me that I can promote a > sell NIOX > - a NIOS-2 compatible core. So I removed the public links to NIOX from my > website. > > there is nothing at opencores that could be used as nios-2 replacement, the > only opensource > environment that i would consider is LEON3/GRLIB, and that is not hosted on > opencores. Did some tests with it...looks nice... > > I have tried to make SOPC processors components and also EDK processor > components > with EDK I succeeded, I had a AVR processor that was possible to use in > EDK/XPS > with SOPC it should also be possible, actually it does exist, and is > available from altera > the Avalon microsequences, its a processor component for SOPC, with full > sources, so > you can use it as base to design your SOPC processors... Gonna dig it out then...kiitoksia (o; rick
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