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Amir, you can take a look at the following module on 4DSP's website: http://www.4dsp.com/modules/F298VP.htm It comprises a Virtex-II Pro, 120 LVTLL I/O , two banks of QDR SRAM (512k x 36 each) and can be hosted on a PC104 carrier card. Send an email to info@4dsp.com if you need more details. Pierrick VulliezArticle: 86701
<sidney@jigsaw.nl> wrote in message news:1120519944.599307.249010@g49g2000cwa.googlegroups.com... > > > Here's the code. > > Thanks. I hope this was something you had made already and not > something you did specially for me- I'd feel all guilty. :) > > One small nit: your line: > > push <= not full and (shift_in = '1'); > > Couldn't this be replaced by > > push <= (not full or shift_out = '1') and (shift_in = '1'); > > This would allow shifting into an already full buffer, iff in the same > cycle you are shifting data out. > > Regards, Sidney > Hi, You could do this. But if you want to use the fifo in a fully handshaking system, you loose an important property! The fifo breaks the combinatorial handshake path and is required to leverage the increased latency in the handshake. In your design, this isn't an issue. It's just a matter of habit. As for the coding: the exercise was usefull to refresh my modelsim knowledge a bit. Regards, Alvin.Article: 86702
Hi Rick, > So...then the downloadble NIOS2 evaluation version breaks the GPL > since it only contains gcc/binutils binaries? Comment 1: Bollocks. Hogwash. Comment 2: I'm not employed by Altera. Elaboration: The GPL states that the author of a GPL derivative is allowed to charge a nominal fee for redistribution of the source. Publishing the code on a web or ftp site would be convenient, but is not a requirement. In order to comply with the GPL, Altera _must_ be willing to send you a copy of the source code for a nominal shipping and handling fee or they'd be violating the GPL - and they are willing. They just happen not to ship the source code with the eval edition. If you want a copy of the source code, I can send it to you and Altera won't object. Not including it with the eval edition is therefore not against the GPL. I guess they made a tradeoff: how many moans do you get from blowing up the downloadable version by ~50MB by providing source code that just about nobody is going to use, and how many moans do you get from users in Finland for not providing the source code and claiming you're violating the GPL. Just my $.02 BenArticle: 86703
Much appreciated Jonathan. It looks like there is no nice way of doing this - although ChipScope is capable or relating the PAR'ed netlist to originally defined signal names in the behavioural model - so I was hoping a similar capability would be available for timing simulation. One way that I can see might be to connect all signals of interest to a port on the top level entity as the port names are retained after synthesis and PAR. One could then simulate and view the ports, but this would introduce additional routing delay and I/O buffer delay - I'd like to hear your thoughts on this. The I/O buffer delay would be the same for all signals (a constant delay offset if you like) so the only unknown would be the routing delay. 1. Do you think this is sensible? 2. What magnitude of delay (range) would be typically introduced? I guess there would be a min and max value corresponding to the port being placed at an I/O site close to the source component and at the furthest possible site, respectively. I have a design where the highest clock speed is 100 MHz, and I'd like to know if the above approach would give useful results for debugging glitches and timing violations. -- Kind regards and thanks again for your insight. Peter Celinski Gecko Audio Pty Ltd Level 4, 35 Saunders St, Pyrmont, NSW 2009, Australia www.geckoaudio.com Tel: +61 (2) 9660 0676 Fax: +61 (2) 9660 0672 Email: peter (AT) geckoaudio.comArticle: 86704
Why would an adder be slower than an increment. In Xilinx, I see no difference. It's all a matter of carry propagation ( and it is pretty fast in either case.) Or is this a case of generics and portability? My analogy for generics is Fast Food. Throw a coin whether you go to McDon or to BurgerKing. it's all the same mediocre or below stuff. Same with a design that is fearful of being Xilinx specific. Using only the ingredients that everybody has, means lowering yourself to the lowest common denominator. Have guts and be specific! There is more stuff than Altera ever dreamt of. Sorry, couldn't resist the plug. Peter AlfkeArticle: 86705
"PeterC" wrote: >1. Do you think this is sensible? > >2. What magnitude of delay (range) would be typically introduced? I >guess there would be a min and max value corresponding to the port >being placed at an I/O site close to the source component and at the >furthest possible site, respectively. > >I have a design where the highest clock speed is 100 MHz, and I'd like >to know if the above approach would give useful results for debugging >glitches and timing violations. This wouldn't be a reasonable way to find most timing violations. Remember that the routing has a very significant variation between two routes of almost the same design. The only way to be reasonably sure that timing will be correct on the next route of the design is to have constraints that check all paths. For a design with a single clock, that means Period, Setup to clock for all inputs and inouts, Clock to output for all outputs and inouts. There should be no gated clocks, and nothing other than the clock should be connected to the clock input of FFs or RAM. There should be no asynchronous resets or presets. When needing multiple clocks, it gets harder. How many clocks do you have? Do you have full static timing constraints? Timing simulation is useful for only when reasonably sure isn't good enough. I've found exactly two real problems in the past decade of doing FPGA designs by doing timing simulations. One of them was a problem in the tools, and the other was my mistake. I know the tools have gotten better, and I hope that I have as well. -- Phil Hays Phil-hays at posting domain (- .net + .com) should work for emailArticle: 86706
Thanks Phil. I have about a dozen clocks, and I do have non-clock signals connected to clk inputs of FFs (not RAM), and only one asynchronous reset which is not part of the problem which I'm trying to resolve. I'm very confident my gated clocks are not a cause of the problem - they are not part of the datapath where I'm seeing glitches. I do have muxed clock using a bit-MUX (not using a BUFGMUX), but chipscope is telling me the events around the mux'ed clock are fine. Specifically, the mux'ed clock is used to control the input and output of a shift register - across two clock domains (synchronous but of different frequencies). The shift register feeds the coefficient input (LD_DIN) port of the DA FIR v9.0 core, and I need to load it at a slower rate than the filter core clock frequency. I'm trying to determine the cause of the glitches on the FIR output - I'm loading a new set of coefficients every few output samples. I do not have full static timing constraints - only two clock period constraints on my highest frequency clocks (both approx. 100 MHz). The FIR runs at 100 MHz, with 8 clock cycles per output sample. Where would you suggest to include static timing constraints? Any hints in this area would be greatly appreciated. Cheers, Peter.Article: 86707
Hi there, This is my first post, so my apologies if this is inappropriate. I have designed an FPGA dev. board with an Altera Cyclone FPGA, National semi 10/100 PHY, 0.5Mx16 10ns SRAM, RTC, EEPROM, Serial flash configuration loader, RS232 and some other misc stuff... I have already had one version working, and have recently released this new version for manufacturing. Details, schematics, pics of the first version (second to be posted wehn it arrives) and other docs can be found here: http://via.dynalias.org Any feedback/comments would be appreciated. If anyone wants bareboards or populated ones, feel free to let me know. They will be given away for cheap since this isn't a for-profit project.Article: 86708
I use Verilog version of xapp 635 and find the same problem with you. I made a small change and it can work well in simulation. You can try this change. In the first "process" of file rx_4_128_right.vhd, change the "we <= "0000" ;" to "we <= "0001" ;". Good luck. "Brijesh" <brijesh_xyz@cfrsi_xyz.com> ???? news:d9f34l$qfi$1@solaris.cc.vt.edu... > Hello, > > Started to look at the xapp635 to implement link port interface in Virtex II > device. I ran a simulation (VHDL version) with the test bench that came with the > app note and it did not pass the test. There is a bug in the receiver > implementation. It fails at the very first reception. > > I have identified the bug to be we_en signal going to the block ram. > > Did anyone have any other issues with this core? > The app note claims to have achieved 500 Mb/s per line, which translates to 250 > MHz clock. Now I have my suspicions on these numbers :-). Does anyone have any > numbers that they achieved? > > The test board Xilinx used seems to be Danube DSP board from Bittware. The > Bittware website claims a max throughput on these links to be 1GB/s which > translates to 125 MHz clock rate. > > Maybe someone had better luck with Verilog version of the core. Cursory look > into verilog source files tells me it also has the same bug. > > Fixing the bug is going to be a pain as there are no comments what so ever in > the code. Looks like they intentionally stripped all the comments before > releasing the code. Wondering if its better to write my own receiver based on > the same technique rather than trying to fix this one. > > Wondering if I can open a webcase or 'bug' Xilinx about this one as its only a > xapp, is free and comes with no warranty what so ever. > > Brijesh > > >Article: 86709
English as a second language is ok. I sympathize for obvious reasons. But please do not tease us with cryptic weird statements. The less you know a certain language, the more explicit you should be. Stick to basic sentences... And ration the exclamation marks and question marks... Peter AlfkeArticle: 86710
In article <Qwzwe.12169$zM2.10928@newsfe4-gui.ntli.net>, hans64@ht- lab.com says... > > I emailed their support line to see if they can supply the board with a 1C12 > and they replied that an updated 2C20/2C35 is in the make. They offered to > replace the board as soon as the 2C20/2C35 becomes available (obviously you > need to pay the price difference :-). > > Hans. > www.ht-lab.com These guys appear to be pretty strong in the customer-service department. I ordered one of their boards and they actually UPS overnighted it from Taiwan to the US for $20 shipping. The board powered up fine, and has a lot of stuff on it to play with (a la the Spartan 3 boards), but I haven't had time to install the software and mess with it as of yet. -- john ------------------------------------------------------ http://www.qsl.net/ke5fx Note: My E-mail address has been altered to avoid spam ------------------------------------------------------Article: 86711
Peter Alfke wrote: > Same with a design that is fearful of being Xilinx specific. Using only > the ingredients that everybody has, means lowering yourself to the > lowest common denominator. I respectfully disagree; in my opinion, your reasoning is the wrong way around. The standard is VHDL (or Verilog) and it's the job of synthesis tool builders to make sure that sensible generic HDL compiles efficiently to their target hardware. It's essentially the same choice as you have in software between implementation in assembly and a processor-independent high-level language. That choice was settled a long time ago for almost any application, and for good reason. > Have guts and be specific! There is more stuff than Altera ever dreamt > of. Sorry, couldn't resist the plug. I like the ability to simulate using GHDL. Furthermore, I dislike vendor lock-in in the extreme- I always like to keep open the option of switching with a reasonable amount of effort. That pretty much settles it for me. Having said all that, as a fellow engineer I can see why you like to push the things that you made yourself to the limits. Regards, SidneyArticle: 86712
Hi, i try to build a dynamic reconfiguration application with use of icap and the embedded powerpc. By reverse engineering i found a lot of the bit-combinations in the configuration-frames, which handle the routing in the switch-boxes. The reverse engineering process takes a lot of time. I think anybody can give me the remaining bit-combinations in the frames? Thanks, SvenArticle: 86713
http://www.gnu.org/licenses/gpl-faq.html#DoesTheGPLAllowDownloadFee "If you distribute binaries by download, you must provide "equivalent access" to download the source--therefore, the fee to download source may not be greater than the fee to download the binary." Cheers, JonArticle: 86714
Jon Beniston wrote: > http://www.gnu.org/licenses/gpl-faq.html#DoesTheGPLAllowDownloadFee > > "If you distribute binaries by download, you must provide "equivalent > access" to download the source--therefore, the fee to download source > may not be greater than the fee to download the binary." > > Cheers, > Jon > http://www.altera.com/support/kdb/2000/11/rd11272000_7307.html Pretty outdated...and ftp directory is empty since few weeks. rickArticle: 86715
The stat(g)es of a pipeline constantly applied to the same input sequence can be statically initialized so that the output is valid immediately. That is, no need to wait N cycles. However, the initalial stage computation can complicate the VHDL code considerably, so I am not sure this approach is decidedly more advageous than merely flagging "invalid" N first outputs of the pipeline.Article: 86716
Hi Alex,
First let me thank you for what has to be a trully unique posting
from a new participant to comp.arch.fpga .
-- Clearly stated problem (but missing density or speed as goal,
expected execution time (i.e. typical loop count per r,p pair))
-- Obvious effort put into defining the data to be manipulated
and careful description of what the data looks like
-- Well stated algorithm, with appropriate comments
-- Some initial thoughts on bandwidth to host system with
a proposed solution to keep the FPGA engine busy
-- Algorithm presented in terms that cleanly map to hardware
constructs
-- Some boundary case analysis (the r-- , r-=p) , since special
cases are the major pain in hardware algorithm accelaerators
-- No silly request that we email you the answer
-- Just really refreshingly clear!
>Obviously I'd like as many sieve units as possible on the final
>FPGA but I'd be looking to implement just one at first (without
>the control unit), then the control function, then multiple
>sievers.
Good plan, get one going. See where the bottle necks are. See
how big it is.
>Sound feasible for an FPGA?
Sure
>Sound feasible for an FPGA novice :-) ?
Depends on your other hardware design experience.
Looks like you need the following types of functional units:
>grab p and r from memory and mark this as 'in progress'.
Memory interface, pair of 64 bit registers
>set initial_r=r /* r being another 64 bit var */
another 64 bit register
>set n=1 /* n is a 64 bit counter */
64 bit counter
>while( n <= maxn ) {
Since you say that maxn is 2^26 or 50E6, maybe n is not 64 bits?
anyway, a comparator (includes a subtractor)
> if( r == 0 ) {
64 bit test for 0
> stop. shove n back into memory and mark result as done(1)
> }
> r=r<<1; /* multiply by 2 */
a 64 bit 2-1 mux
> r--; /* decrement r by 1. r will always be > 1 so no need for
> bounds checking */
Ooops, looks like r is a loadable counter, rather than just a register
> if( r >= p ) {
64 bit comparitor (includes a 64 bit subtractor)
> r-=p; /* again, always +ve result */
another 64 bit subtractor
> }
> n++; /* increment n by one */
> if( r == initial_r ) { /* comparison */
64 bit comparitor (no subtractor for this one)
> stop. shove n back into memory and mark result as done(2)
> }
>}
plus a controller.
The initial design should not care about timing, just get it to do
the algorithm.
Then there are wonderful opportunities for pipelining:
-- between the various algorithm statements,
-- within the counters and adders/subtractors (because at 64 bits
there may be oppportunities that do not exist for smaller structures)
-- Multiple instances of the algorithm processing different r,p
pairs, but sharing the pipeline. Barrel processing. This is hinted
at, because it looks like your algorithm can't start the next
itteration of the loop until the current one is finished.
This is also referred to as C-slow approach by Nicholas Weaver who
posts to this news group on occasion. Try a Google search and this:
http://www.cs.berkeley.edu/~yatish/cs252/252slides.ppt
Looks like you have some fun ahead of you.
On 28 Jun 2005 06:58:12 -0700, "Alex" <alex@greenbank.org> wrote:
>Hello,
>
>I know FPGA's are not suitable for sieving large numbers however
>one set of numbers (Proth numbers, related to the Sierpinski
>conjecture) I think would fit an FPGA quite well.
>
>Sorry if this is a relatively basic or silly question but I'm
>a novice with FPGAs although I've been reading up on them and
>playing around with the software.
>
>I'd be dealing with numbers in the 32 to 64 bit range (current
>limits of sieving are around 50 bit numbers) and hoping to put
>many sievers on one FPGA (I have a Spartan-3 dev kit with
>200k gates).
>
>The basic algorithm is this:-
>
>p - 64 bit number (a prime) although top bit will never be set
>r - 64 bit number (0 <= r < p)
>maxn - 50,000,000 but easily replaced with 2^26 if easier
>
>The above would be supplied by a controlling computer via
>parallel or RS232 connection and stored somewhere in the 1M-byte
>of RAM. The controlling computer would make sure there are plenty
>of these values available in memory for the sievers to grab.
>
>An individual siever would:-
>
>grab p and r from memory and mark this as 'in progress'.
>set initial_r=r /* r being another 64 bit var */
>set n=1 /* n is a 64 bit counter */
>while( n <= maxn ) {
> if( r == 0 ) {
> stop. shove n back into memory and mark result as done(1)
> }
> r=r<<1; /* multiply by 2 */
> r--; /* decrement r by 1. r will always be > 1 so no need for
> bounds checking */
> if( r >= p ) {
> r-=p; /* again, always +ve result */
> }
> n++; /* increment n by one */
> if( r == initial_r ) { /* comparison */
> stop. shove n back into memory and mark result as done(2)
> }
>}
>
>Obviously I'd like as many sieve units as possible on the final
>FPGA but I'd be looking to implement just one at first (without
>the control unit), then the control function, then multiple
>sievers.
>
>Sound feasible for an FPGA?
>Sound feasible for an FPGA novice :-) ?
>
>Ta,
>
>-Alex
Philip Freidin
Fliptronics
Article: 86717Hallo, I'm trying to connect a Spi 16 bit ADC to Opb_Spi core. Where I could find some software examples? I have made some searches into Google but I don't have found anything. The only example into EDK documentation is about an eeprom. What is the meaning of : Status = XSpi_SetOptions(&Spi, XSP_MASTER_OPTION | XSP_MANUAL_SSELECT_OPTION); In this way ADC is a master? When acquiring data, ADC must be set as a master? Many Thanks in Advance MarcoArticle: 86718
"Marco" <marcotoschi@_no_spam_email.it> schrieb im Newsbeitrag news:dae5ja$pij$1@news.ngi.it... > Hallo, > I'm trying to connect a Spi 16 bit ADC to Opb_Spi core. > > Where I could find some software examples? > > I have made some searches into Google but I don't have found anything. > > The only example into EDK documentation is about an eeprom. > > What is the meaning of : > Status = XSpi_SetOptions(&Spi, XSP_MASTER_OPTION | > XSP_MANUAL_SSELECT_OPTION); > > In this way ADC is a master? > > When acquiring data, ADC must be set as a master? > > Many Thanks in Advance > Marco > > 1 there are no examples to be found by googling (my guess) 2 the meaning of what you asked is defined in the opb ip core manual, you better read it your setup seems to be OK, eg you set master and manual SS, that is you must yourself write to SS register to assert-deassert the ADC select signal Antti PS I almost always use a GPIO bit bang SPI emulation at first testing, the soft SPI code is a only a few lines of C code. only when the software SPI works with the connected hardware I proceed with special SPI hardware, controlling hardware SPI is usually more complex (need to read the manuals!!) then doing it 100% in sw.Article: 86719
I have two fpga boards; one of them pretends to be the device (say a mouse), the other one would be the host. I would like the host to read the data sending from the device thru the PS/2 port. I have got the PS/2 interface (from opencores.org CVS/ps2core); is this good enough for both the device and the host? such that I can use the same PS/2 interface on both the device and the host, and it will be fine to just connect the PS/2 port with a suitable cable? Thanks.Article: 86720
Jedi wrote: > Jon Beniston wrote: > >> http://www.gnu.org/licenses/gpl-faq.html#DoesTheGPLAllowDownloadFee >> >> "If you distribute binaries by download, you must provide "equivalent >> access" to download the source--therefore, the fee to download source >> may not be greater than the fee to download the binary." >> >> Cheers, >> Jon >> > > http://www.altera.com/support/kdb/2000/11/rd11272000_7307.html > > Pretty outdated...and ftp directory is empty since few weeks. > If Altera doesn't mind I setup something like nios.uclinux.net or altera.uclinux.net and upload the re-arranged sources... Just have to include/test elf2flt first since this isn't available as source from Microtronix either (o; rickArticle: 86721
"Jedi" <me@aol.com> schrieb im Newsbeitrag news:nOxye.221$kA1.202@read3.inet.fi... > Jedi wrote: > > Jon Beniston wrote: > > > >> http://www.gnu.org/licenses/gpl-faq.html#DoesTheGPLAllowDownloadFee > >> > >> "If you distribute binaries by download, you must provide "equivalent > >> access" to download the source--therefore, the fee to download source > >> may not be greater than the fee to download the binary." > >> > >> Cheers, > >> Jon > >> > > > > http://www.altera.com/support/kdb/2000/11/rd11272000_7307.html > > > > Pretty outdated...and ftp directory is empty since few weeks. > > > > If Altera doesn't mind I setup something like nios.uclinux.net > or altera.uclinux.net and upload the re-arranged sources... > > Just have to include/test elf2flt first since this isn't available > as source from Microtronix either (o; > > > rick > Altera CAN NOT say anything. The stuff is GPL so its ok to make it available in public as long as you comply to GPL no matter what way you obtained the sources AnttiArticle: 86722
"Antti Lukats" <antti@openchip.org> wrote in message news:dae8h6$pm0$01$1@news.t-online.com... > "Marco" <marcotoschi@_no_spam_email.it> schrieb im Newsbeitrag > news:dae5ja$pij$1@news.ngi.it... >> Hallo, >> I'm trying to connect a Spi 16 bit ADC to Opb_Spi core. >> >> Where I could find some software examples? >> >> I have made some searches into Google but I don't have found anything. >> >> The only example into EDK documentation is about an eeprom. >> >> What is the meaning of : >> Status = XSpi_SetOptions(&Spi, XSP_MASTER_OPTION | >> XSP_MANUAL_SSELECT_OPTION); >> >> In this way ADC is a master? >> >> When acquiring data, ADC must be set as a master? >> >> Many Thanks in Advance >> Marco >> >> > > 1 there are no examples to be found by googling (my guess) > 2 the meaning of what you asked is defined in the opb ip core manual, you > better read it > > your setup seems to be OK, eg you set master and manual SS, that is you > must > yourself > write to SS register to assert-deassert the ADC select signal > > Antti > PS I almost always use a GPIO bit bang SPI emulation at first testing, the > soft SPI code is a only a few lines of C code. only when the software SPI > works with the connected hardware I proceed with special SPI hardware, > controlling hardware SPI is usually more complex (need to read the > manuals!!) then doing it 100% in sw. > > I posted because I don't have found the core manual very clear... I have another doubt: ADC is 16 bit, but XSpi_Transfer works with 8 bit data buffer. That means to obtain a 16 data I must use 2 8bit buffers? In example a vector of 2 elements?Article: 86723
"Marco" <marcotoschi@_no_spam_email.it> schrieb im Newsbeitrag news:dae9vd$r6d$1@news.ngi.it... > > "Antti Lukats" <antti@openchip.org> wrote in message > news:dae8h6$pm0$01$1@news.t-online.com... > > "Marco" <marcotoschi@_no_spam_email.it> schrieb im Newsbeitrag > > news:dae5ja$pij$1@news.ngi.it... > >> Hallo, > >> I'm trying to connect a Spi 16 bit ADC to Opb_Spi core. > >> > >> Where I could find some software examples? > >> > >> I have made some searches into Google but I don't have found anything. > >> > >> The only example into EDK documentation is about an eeprom. > >> > >> What is the meaning of : > >> Status = XSpi_SetOptions(&Spi, XSP_MASTER_OPTION | > >> XSP_MANUAL_SSELECT_OPTION); > >> > >> In this way ADC is a master? > >> > >> When acquiring data, ADC must be set as a master? > >> > >> Many Thanks in Advance > >> Marco > >> > >> > > > > 1 there are no examples to be found by googling (my guess) > > 2 the meaning of what you asked is defined in the opb ip core manual, you > > better read it > > > > your setup seems to be OK, eg you set master and manual SS, that is you > > must > > yourself > > write to SS register to assert-deassert the ADC select signal > > > > Antti > > PS I almost always use a GPIO bit bang SPI emulation at first testing, the > > soft SPI code is a only a few lines of C code. only when the software SPI > > works with the connected hardware I proceed with special SPI hardware, > > controlling hardware SPI is usually more complex (need to read the > > manuals!!) then doing it 100% in sw. > > > > > > I posted because I don't have found the core manual very clear... > > I have another doubt: ADC is 16 bit, but XSpi_Transfer works with 8 bit data > buffer. > > That means to obtain a 16 data I must use 2 8bit buffers? In example a > vector of 2 elements? > no you use MANUAL SS assertion, you already had that setup in your code snippet actually so you set SS active do 8 bit transfer do another 8 bit transfer de assert SS ADC 'sees' one 16 bit transfer but I would says doing it that way is more complex and takes more time than bitbang software method AnttiArticle: 86724
Well, some people like "chopped up fatty meat", and don't know what they are missing: better taste, more variety, better health, and also lower cost and higher performance (the analogy fails me here). The battle between the FPGA vendors will not be in the direction of greater similarity.. We will never become DRAM-like commodities where ever lower price is the only differentiator. Our pride is in offering superb functionality and extreme performance at a very attractive price. If you decide not to take advantage of our features, maybe your competitor will... (Not meant as a threat, just a friendly reminder) With my apologies to McDonalds and BurgerKing for the analogy. Peter Alfke
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