Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Nju Njoroge wrote:
> Jason Zheng wrote:
> > Nju Njoroge wrote:
> > > Hi,
> > >
> > > I'm using the Verilog-2001 exponential operator to do the following:
> > >
> > > `define NUM_COUNTER_BITS 8;
> > > parameter NUM_COUNTER_CYCLES = 2 ** (`NUM_COUNTER_BITS);
> > >
> > > When I simulate this in ModelSim 6.0a, launched from Project Nav. (ISE
> > > 7.1 SP3), NUM_COUNTER_CYCLLES = 5. However, if I use a parameter for
> > > NUM_COUNTER_BITS instead of `define, as shown below, NUM_COUNTER_CYCLES
> > > = 256, which is the desired result.
> > >
> > > parameter NUM_COUNTER_BITS = 8;
> > > parameter NUM_COUNTER_CYCLES = 2 ** (`NUM_COUNTER_BITS);
> > >
> > > What are the inherent differences between a parameter and `define
> > > directive that could this problem to occur.
> > >
> > I tried it with ncverilog, and didn't get the bad answer. Is it
> > posssible that the ; at the end of `define is causing the problem?
> >
> > Try this in your module:
> >
> > initial
> > $display ("NUM_COUNTER_BITS = %d", `NUM_COUNTER_BITS);
> Thanks for the suggestion. I tried this below:
> $display("NUM_COUNTER_CYCLES=%d", 2 ** `NUM_COUNTER_BITS);
>
> and it does print out "NUM_COUNTER_CYCLES=256" in ModelSim. However, in
> the actual waveform, the value is still 5 and the logic uses that
> incorrect value.
>
> The main reason I want to use `define directive is because I'm using a
> `include file since this constant is used in many other modules.
>
> NN
By the way, the ";" at the end of the `define directive was a typo in
my original posting. I don't have it in the real code.
NN
Article: 86876Hi, I am trying to use the plb_tft driver provided in the ML401 reference design with a ML402 board. The reference design "slideshow" doesnot work if I try to download from the EDK enviroinment. Where as, if I use the design stored in the CF card, everything works!! The design stored in the CF card uses system0.bit ot configure the FPGA. I am not sure what it does and the source-code for that design is not known either. Can someone help me with this. Any suggestion is appreciated. Thanks, Krishna.Article: 86877
> Also kind of funny that they used a Quartus version three revisions old, > and the latest ISE and Synplify? Especially when the final (newer) Stratix II timing models have DSPs & Memories running much faster than in older releases, eliminating some of X's favourite "up to" numbers quoted... Paul Leventis Altera Corp.Article: 86878
>>>> Jim Granville wrote: >>>> Imagine a stacked die FPGA, with a large VFast SRAM, and Config device ? >>> >>> Uwe Bonnes wrote: >>> You're dreaming >> >> >> Of course, but it is realistic of what might be on our desks in 2-3 yrs time ? [Which means we should be thinking about it now, and if one >> FPGA vendor sees this, and the others miss it == big lead] >> >> Other industries have this stacked die, today - so this allows some inertia in the smaller, more inwardly looking, FPGA sector > Peter Alfke wrote: > We are not just inward-looking. Of course we also look at the > possibilities of stacked die. > But the applications flexibility that makes FPGAs so great, works > against die stacking. > Pentiums and cell phones are more "single purpose" where the > manufacturer can aim at a well-defined application without too many > variations. FPGAs are used all over the place, in all sorts of > constellations. Which one should we concentate on, which one to ignore? > Just my opinion... > Peter Alfke Further on this Stacked die discussion, I see the first example of "stacking technology" in a roadmap for the merchant Microcontroller market, which is about as far from "single purpose" as you can get. See pages 6-9 of : http://mcu.st.com/mcdfiles/1101944952.pdf [You can also see a smallish CPLD in some of these feature-packed devices...Ethernet.CAN.USB.2MF.96KR] Since ST have strong Burst FLASH, and Microcontoller/ASIC product lines, this is easy for them to do. So I believe it is more a question of who will be first to do this, in the FFGA sector ? [Altera/Lattice/Xilinx...] ? -jgArticle: 86879
Hello Mr.Ray Andraka, I have heard that you are written a book on "DSP on FPGA". Please let me know when it is schedule to be available in stores. Thanks and Regards JamesArticle: 86880
stud_lang_jap@yahoo.com wrote:
>Hello Mr.Ray Andraka,
>I have heard that you are written a book on "DSP on FPGA".
>Please let me know when it is schedule to be available in stores.
>
>
>Thanks and Regards
>James
>
>
>
It is scheduled to be in the stores in the fall, but I have to turn it
over to the publisher first.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 86881Thanks for the info, Waiting for your book, JamesArticle: 86882
One difference is that parameters can be over-ridden by the calling module via the defparam command. Not true with `define. On 7 Jul 2005 16:16:48 -0700, "Nju Njoroge" <njoroge@stanford.edu> wrote: >Hi, > >I'm using the Verilog-2001 exponential operator to do the following: > >`define NUM_COUNTER_BITS 8; >parameter NUM_COUNTER_CYCLES = 2 ** (`NUM_COUNTER_BITS); > >When I simulate this in ModelSim 6.0a, launched from Project Nav. (ISE >7.1 SP3), NUM_COUNTER_CYCLLES = 5. However, if I use a parameter for >NUM_COUNTER_BITS instead of `define, as shown below, NUM_COUNTER_CYCLES >= 256, which is the desired result. > >parameter NUM_COUNTER_BITS = 8; >parameter NUM_COUNTER_CYCLES = 2 ** (`NUM_COUNTER_BITS); > >What are the inherent differences between a parameter and `define >directive that could this problem to occur. > >Thanks, > >NNArticle: 86883
You should run through place and route. I think you'll find the actual speed is much better. I assume you have specified an appropriate timing constraint such as 10ns? If you don't tell the tools how fast you want to run, they won't try very hard. On 7 Jul 2005 05:15:52 -0700, "Giox" <giovanniparodi79@yahoo.it> wrote: >Hi, I'm using a virtex 300E and after the synthesis step (not place and >route), the frequency is estimated as 82.129MHz. >The performances are better than whose that I need, but the occupied >area is considerable. >GioArticle: 86884
Hi, I'm a student from germany and try to develop a dynamic reconfiguration application for a virtex-2 pro fpga. The application/system will use the icap-module and the embedded ppc for the reconfiguration process. On Xilinx Websites and otherwise sources i don't find any information about the structure of the configuration frames and the meaning of the bits in this frames. Is it possible to get such informations from anywhere? In the last two month i got out, that the configuration is stored in a 80x22 bit matrix for each clb-element of a virtex-2 pro fpga. Furthermore i found out the bit-combinations for a lot of connections, which can be formed in the switch-boxes of an clb-element, but there are some more bit-combinations in what i'm intressted. Can anybody give me some tipps or the remaining informations? Thanks, SvenArticle: 86885
I need to use Rocket-IO in Vertex-4 to receive data at the rate of 6.22Gbps. My reference clock input to the Rocket-IO is 155.5MHz. Data rate is 40X of that clock. I need to have a parallel output in 40-bit-wide format and output at 155.5MHz rate. I do not need any other process inside the Rocket-IO. I just need to do serial-to-parellel conversion. I have followed the guide of Rocket-IO and also got some help from Xilinx engineer to get a start. Now I have simulated with VCS to see the Rocket-io output data as I intended to. However if I run the simulation longer I see the parallel output become incorrect at every 40th parellel output word. The expected value is not there. Instead the value in the previous clock cycle is repeated. This goes on at every 40th word. All other output words are correct. I am wondering if any other V4 Rocket-IO user faces the same problem. Could it be the simulation model's problem, Xilinx Rocket-IO's bug, or something I did not set up correct? Unfortunately the same Xilinx engineer keeps quite since I sent my question to him. Maybe too busy? Appreciated for any help. If needed I can send all the files including instantiation to GT11 and testbench. These are verilog files.Article: 86886
Thanks again for your help. :o) Andre Ben Jones schrieb: > Hi Andre, > > Interesting to know that the Lattice simulations models work just like the > Xilinx ones in this respect. > > > Are the synchronous elements in the real design immediately ready when > > leaving Global Reset (Pll is already locked) ? Or is there some "wait" > time > > according to the timing simulation? > > They are ready immediately. The "wait" time is really just an artefact of > the simulation environment. It may be possible when generating your > simulation model to pull the "configuration reset" signal out and turn it > into a port on the model, so that you can control exactly when it gets > de-asserted (relative to other devices in your simulation, for example). > However as I mentioned, I've not used the Lattice tools so I'm guessing a > bit here! > > Glad you got it all working. > > -Ben-Article: 86887
Hi Joel, As suggested before I would simply write some time/area critical blocks of your design, then synthesize/P&R for the three different families and see what you get. obviously you need to study all 3 architectures since you might need to do some low level stuff. If you don't have an all vendors synthesis tool then get an evaluation copy of Precision/Synplicity which should sort you out for at least 30 days :-) You might also want to speak to an FAE from all three companies (ask the Actel guy when the ProASIC3+ARM core will be available :-) to see what support is like. For debugging I would suggest you have a look at Temento's Dialite which is an FPGA independent JTAG debugger on steroids :-) Regards, Hans. www.ht-lab.com "Joel Kolstad" <JKolstad71HatesSpam@yahoo.com> wrote in message news:11cp5ptpk3jg1c2@corp.supernews.com... > Hi, > > It's been a couple of years since I've been a heavy FPGA user, but it > appears > that I'll now be getting back into them. As of a few years back, I was > using > Xilinx Virtex IIe parts and was quite happy with them... I kept up with > what > Altera was doing as well, and while it always seemed to me that for DSP > applications Xilinx tended to have the edge, in many ways Xilnx and Altera > were the Coke and Pepsi of FPGAs -- both were good, solid products where > either could have gotten the job done in the vast majority of > applications. > > Where I am now there's been some historical use of the Actel 54SX parts, > something I've never used. However, I do recall that -- as of a few years > ago -- the deal with Actel was always that the parts were antifuse-based, > so > while you _might_ be able to gain something in speed, you gave up a lot in > the > way of being able to issue field upgrades, bug fixes, etc. However, I now > see > that Actel has their ProASIC line of parts so they can perhaps compete > somewhat closer to Xilinx and Altera than previously. Could anyone > summarize > how the ProASIC parts stack up to the contemporary Xilinx and Altera > parts? > (E.g., Xilinx Virtex II or 4, Altera Stratix II.) In particular I'm > interested in: > > -- DSP usage. Things seemed to get a lot easier when Xilinx starrted > introducing fixed DSP blocks (e.g., multiply-accumulate blocks) within the > FPGA fabric. > -- Embedded processor usage. I never used them, but Xilinx and Altera's > embeeded "soft cores" (microblaze and NIOS) both seemed pretty neat, and > Xilinx was offering ARM hard cores if you really wanted "big iron." > -- Debugging support. Xilinx had some "soft probe" thing that would let > you > poke around the internal nets of the FPGA as it was running, and I believe > Altera had something like this even before Xilinx. > -- Tool support. I used to use Synplify for VHDL synthesis, which worked > quite well. I tried Xilinx's built-in synthesis tool, and given the price > (vs. Synplify), it was really pretty good as well. > > How does Actel performs in these area? I realize they're very general > questions, but I'm trying to get a feeling for how viable ProASICs are for > something like a software defined radio (i.e., plenty of "real" DSP, > desire > for some "supervisory" soft core CPU, etc.) vs. just going with what I > know > would work -- Xilinx or Altera. > > Thanks, > ---Joel Kolstad > >Article: 86888
I have no CF card reader. But I have 2 PROMs on my board, and I would like to store the progam there. If all I have is 6 block RAMs remaining, is it possible at all, to run the program on this board. My design uses up 38 out of the 44 BRAMs available. Can you advice me a possible solution. "Peter Ryser" <peter.ryser@xilinx.com> schrieb im Newsbeitrag news:42CC13E2.2060906@xilinx.com... > Since you have System ACE CF in your system that is the easiest way to > load both bitstream and ELF file. Please read up in the EDK > documentation how to generate an ACE file for your system. > > - Peter > > > Andi wrote: > > Hi, > > > > do you want to run the program out of sdram or out of the bram? What is the size of the c-code? Do you use the edk system as top level? Or do you integrate the edk system in your own top level? > > > > The tool flow from edk supports the mechanism to fit the c-code -> elf-file in the bram during the bitgen procedure. > > > > Then when the fpga is loaded the c-code starts directly. >Article: 86889
Hi, I would like to know how we can store a program in the on-board PROMs. My CORE takes up 36 out of the 44 available BRAMs. By the way, I would want to mention a couple more of things. 1. I use a Virtex2Pro board and this design uses the PowerPC 2. I dont have a CF reader / ACE CF Reader 3. It has 2 Xilinx Flash PROMs -- This is what I want to use. 4. I have 32MB SDRAM available. Thank you, JoeyArticle: 86890
Have a look at this application note http://www.xilinx.com/bvdocs/appnotes/xapp482.pdf which is a similar application for MicroBlaze. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "Joey" <johnsons@kaiserslautern.de> wrote in message news:dalgql$q3f$1@news.uni-kl.de... > > Hi, > > I would like to know how we can store a program in the on-board PROMs. My > CORE takes up 36 out of the 44 available BRAMs. By the way, I would want > to > mention a couple more of things. > > 1. I use a Virtex2Pro board and this design uses the PowerPC > 2. I dont have a CF reader / ACE CF Reader > 3. It has 2 Xilinx Flash PROMs -- This is what I want to use. > 4. I have 32MB SDRAM available. > > Thank you, > Joey > >Article: 86891
Joey wrote: > Hi, > > I would like to know how we can store a program in the on-board PROMs. My > CORE takes up 36 out of the 44 available BRAMs. By the way, I would want to > mention a couple more of things. > > 1. I use a Virtex2Pro board and this design uses the PowerPC > 2. I dont have a CF reader / ACE CF Reader > 3. It has 2 Xilinx Flash PROMs -- This is what I want to use. > 4. I have 32MB SDRAM available. > > Thank you, > Joey > > Hi Joey, if your programm don't fit in the BRAMs (i think you have plb/opb BRAM in your PPC design) you have a problem. It sounds like you use a Memex Eval board. Is this right? Best regards, MichaelArticle: 86892
I'm using EDK 6.3 + SP2, along with ISE 6.3 + SP3 + IP updates 4 + XFFT patch. Yes, I had no problem building the reference design, and no problems adding my own plb peripherals. I'm working on a sonar beamformer app. using plb peripherals with xfft3_1. My problem was that the reference design included many cores that I didn't need, and my plb peripherals were getting pretty big (big FFTs), so I wanted to strip down the reference design. However the resets and clocks for different parts of the reference design were all a bit coupled (misc_logic, sys_proc_reset etc.) so I initially had difficulty separating things out. Because I couldn't find an XBD file, last week I started from scratch with a new XPS project, adding only the ip I needed, and making my own entities with DCMs for the system, plb and ddr sdram clocks. I used the reference design's constraints file (system.ucf) as a guide - its working fine. I think the reference design uses some deprecated cores - only thing I can think of is perhaps you accidentally changed these to newer versions which aren't compatible? - In Xilinx Platform Studio, did you go into 'add/edit cores' and accidentally upgrade these cores? Best regards Allan WillcoxArticle: 86893
http://wiki.openchip.org/index.php/Xilinx:Spartan3e we are testing ISE 7.1 for 'spartan-3E readiness' in SP3 the support is slighlty better, now 500e is also recognized in JTAG chain, but there still isnt full support for the all family. The testing is done by using 'emulated' JTAG chain, - all the 7 Xilinx FPGA's are actually living inside one S3-1500 the JTAG IDcodes are correct as ChipScope recognized them, so it must be the problem# of impact 7.1 SP3 what means that for full S3E SP4 is possible needed AnttiArticle: 86894
Austin Lesea <austin@xilinx.com> writes:
> Katherine,
>
> A properly designed link using any Xilinx MGT has 0 errors.
>
> That is how they are supposed to work.
>
> If you are running at some fixed, but small dribbling error rate, the
> link is broken, or not designed properly.
>
> As soon as you near the edge of the error rate curve ('waterfall
> curve', anything can then cause you to fall over into the 1E-3 region:
> inoperable (temperature, voltage, etc.)
>
> Again, properly designed and implemented links have NO errors.
>
Until somone fires up an arc welder in the vicinity :-) Anything that
can go wrong will - it depends on the requirements of the system as to
whether errors of that sort are acceptable. And then to come up with
whatever mitigation is required. For example a directly-life-and-limb
threatening system will probably not use a single link of any sort
over any distance!
Sorry to sound tedious, but categoric statements with zeroes in them
tend to wind the pessimist-in-me up!
Or am I missing something in the MGT implementation - I have to admit
to only being aware of them, not having used them - our car
applications tend to stick around lower bitrates (well, apart from the
video cameras!)
Cheers,
Martin
--
martin.j.thompson@trw.com
TRW Conekt, Solihull, UK
http://www.trw.com/conekt
Article: 86895uups replied instead of making a new post :( "Antti Lukats" <antti@openchip.org> schrieb im Newsbeitrag news:dalk2v$f9a$02$1@news.t-online.com... > http://wiki.openchip.org/index.php/Xilinx:Spartan3e > > we are testing ISE 7.1 for 'spartan-3E readiness' > > in SP3 the support is slighlty better, now 500e is also recognized in JTAG > chain, > but there still isnt full support for the all family. The testing is done by > using > 'emulated' JTAG chain, - all the 7 Xilinx FPGA's are actually living inside > one S3-1500 > the JTAG IDcodes are correct as ChipScope recognized them, so it must be the > problem# > of impact 7.1 SP3 > > what means that for full S3E SP4 is possible needed > > Antti > uups replied instead of making a new post :(Article: 86896
The design is for the embedded market. I have no idea at all what firmware is going into the V2Pro nor at what frequency. The decoupling, for instance, is not matched to any particular frequency nor are the power supplies matched for any particular transient load. Had a hell of a time recently with a hotswap controller which was in full production and then a customer enables his clocks, the FPGA gulps current and down went the board untill the next power cycle. I also have no control over the backplane, nor the gigabit router that some of the MGTs are driving etc, etc, etc. Two years ago Xilinx were very very cagey and wanted to hold everyones hand through MGTs with very strict guidelines. Now with 10GBps MGTs woking on FR4 the tune seems to have changed!Article: 86897
What clock are you using to clock the data out? It should not be your reference clock because this will not be synchronous to the data and you will experience a glitch periodically. You could use the recovered clock. This is the clock recovered from the serial data stream so it will be synchronous with the data. On 7 Jul 2005 23:44:21 -0700, shuo.huang@fibre.com wrote: >I need to use Rocket-IO in Vertex-4 to receive data at the rate of >6.22Gbps. My reference clock input to the Rocket-IO is 155.5MHz. Data >rate is 40X of that clock. I need to have a parallel output in >40-bit-wide format and output at 155.5MHz rate. I do not need any other >process inside the Rocket-IO. I just need to do serial-to-parellel >conversion. I have followed the guide of Rocket-IO and also got some >help from Xilinx engineer to get a start. Now I have simulated with VCS >to see the Rocket-io output data as I intended to. > >However if I run the simulation longer I see the parallel output become >incorrect at every 40th parellel output word. The expected value is not >there. Instead the value in the previous clock cycle is repeated. This >goes on at every 40th word. All other output words are correct. > >I am wondering if any other V4 Rocket-IO user faces the same problem. >Could it be the simulation model's problem, Xilinx Rocket-IO's bug, or >something I did not set up correct? Unfortunately the same Xilinx >engineer keeps quite since I sent my question to him. Maybe too busy? > >Appreciated for any help. If needed I can send all the files including >instantiation to GT11 and testbench. These are verilog files.Article: 86898
> Hi Joey, > > if your programm don't fit in the BRAMs (i think you have plb/opb BRAM > in your PPC design) you have a problem. > It sounds like you use a Memex Eval board. Is this right? > > Best regards, > > Michael Hey Michael, you are great !! IT IS a Memec Eval board and my prog is defenitely much bigger than what 8 BRAM blocks could ever hold. Are you saying that there is no other possibility, other than running it with a debugger. Well thats all I know (I give in that I am new in this field :( ) JoeyArticle: 86899
"Ray Andraka" <ray@andraka.com> schrieb im Newsbeitrag news:YIgze.27303$FP2.14627@lakeread03... > and how well the feature set of that chip augment your design. Both are > good products, and > you won't go wrong with either as long as you pay attention to the > device architecture as you > develop your design. Amen. Hail to reverend Andraka SCNR. Regards Falk
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z