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Thanks for the info, Hans. BTW, I like your web site, but I'd like it even more if you didn't "trap" other web sites within your own frames. :-) ---JoelArticle: 86901
I used RXRECCLK to clock the output. Marko wrote: > What clock are you using to clock the data out? It should not be your > reference clock because this will not be synchronous to the data and > you will experience a glitch periodically. You could use the > recovered clock. This is the clock recovered from the serial data > stream so it will be synchronous with the data. >Article: 86902
Hello, My FPGA is running at 80Mhz and I've heard the max sample rate is 50Mhz, so I just wanted to see if it can go higher. joe Peter Sommerfeld wrote: > Hi Joe, > > Since SignalTap is just like any other circuit in your FPGA, the answer > would be the same as for, "How fast can a circuit run in my device?" > > It entirely depends on what else is part of the FPGA design, on what > embedded memory SignalTap uses for buffers, how many signals you are > watching, the device itself, and so on. SignalTap can slow down, or be > slowed down by, the circuit it is inspecting. > > Practically, I haven't had much problem with SignalTap not being fast > enough. Even in the cases where timing isn't met, I slow down the > design sufficiently so it's not a problem, since SignalTap is only used > in the debug phase for me. > > HTH > > -- Pete > > jjlindula@hotmail.com wrote: > > Hello, does anyone know what is the max Sample Rate used in the Signal > > Tap utility under Altera's Quartus? > > > > Thanks, > > joeArticle: 86903
Ray Andraka wrote: > Paul Leventis (at home) wrote: > > <basically, "mine is bigger"> > > *Sigh*, here we go again. Ray -- please don't take a job working for any of the FPGA vendors! Your vendor-independent voice of reason is sorely needed here. I'm sure I speak for many when I say that I'm bored of the A vs X pissing match. I don't care which FPGAs were the first ones built on a 90 nm process! I don't care that a part is going to be $2 each when purchased in quantities of a HALF MILLION in 2007. (Wish I did care, but that's a different story.) (Is the config PROM gonna be twenty cents?) Users want: a) tools that work b) parts we can buy in the quantities we need in the timeframe required by our schedules. I think the best thing about the availability of free tools is that if we're not pushing the envelope (read: using the latest/greatest), we can keep all vendor tools installed on our development machines and choose the parts that make the most sense. -a ----------------------- Andy Peters Tucson, AZ devel at latke dot netArticle: 86904
I will search the internet for more information and se if I can get that book. :-) "Ray Andraka" <ray@andraka.com> skrev i meddelandet news:BYfze.27300$FP2.4569@lakeread03... > Elektro wrote: > > >Hello > > > > > > > >I’m looking for some good book about bit serial programming. I’m interested > >in learning about it to implement functions bit serially in VHDL. > > > > > > > >The only book I have found is “VLSI Signal Processing: A Bit-Serial > > Approach”, but I don’t think it’s available any more. > > > > > > > >Or if you know of some page on the web that has some info on the subject. > > > > > > > >/Sweden > > > > > > > > > That is about the only book I've seen on bit serial. It is certainly the > only thing I've seen that has comprehensive coverage of the entire > topic. It is not really easy reading, but it does contain good > information. You can find it used if you look. It took me about 3 months > to find a copy, but when I did there were suddenly 4 or 5 available. > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 86905
interesting to know ... let us know when it is available? thanks <stud_lang_jap@yahoo.com> wrote in message news:1120797266.862323.46420@f14g2000cwb.googlegroups.com... > Thanks for the info, > Waiting for your book, > > James >Article: 86906
Hi everyone, I'm using all the four phase-out signals from a DCM (0, 90, 180 and 270 degrees offset) to each clock a single D-Flipflop. I want these flip-flops to be placed and routed as close (delay-wise) to the DCM outputs as possible. But I can't figure out how to set up a constraint for that: timing constraints only seem to work on pins, flipflops, pads and latches. Can anyone suggest how to get PAR to put the FFs as close to the DCM, with the delays for these 4 nets as close to each other as possible ? Regards, Paul Boven.Article: 86907
Hi Is it possible to set a relative path into <Macro Search Path> in translate properties (ngdbuild) ? I tried it on 7.1 and doesn't work. But I dont recall if relative path in <Macro Search Path> was working on ISE 6.x Thanks PierreArticle: 86908
"Paul Boven" <p.boven@chello.nl> schrieb im Newsbeitrag news:1120848554.716689@blaat.sara.nl... > Hi everyone, > > I'm using all the four phase-out signals from a DCM (0, 90, 180 and 270 > degrees offset) to each clock a single D-Flipflop. > I want these flip-flops to be placed and routed as close (delay-wise) to > the DCM outputs as possible. Just use a LOC constraint. Gives you maximum control with minimum trouble. But you can define a timing group for these four clocks and define a max. delay. Also a max skew constraint is probably a good idea. Have a look at the xapps, there a several ones discussing clock/data recovery at very high data rate by doing exactly what you want to do. Regards FalkArticle: 86909
<jjlindula@hotmail.com> schrieb im Newsbeitrag news:1120839025.730535.307150@g47g2000cwa.googlegroups.com... > Hello, > > My FPGA is running at 80Mhz and I've heard the max sample rate is > 50Mhz, so I just wanted to see if it can go higher. > > joe > If you have a "modern" FPGA, 80MHz should be no problem for SignalTap... ThomasArticle: 86910
PL wrote: > Hi > Is it possible to set a relative path into <Macro Search Path> in > translate properties (ngdbuild) ? > > I tried it on 7.1 and doesn't work. > > But I dont recall if relative path in <Macro Search Path> was > working on ISE 6.x > Sure, I use relative paths for everything, including the Macro Search Path, in 6.3. I would be very surprised if it did not work in 7.1. Did you click the browse button and navigate to the directory?Article: 86911
Is there a simple tutorial or reference design available that implements the ethernet IP from Xilinx? I have stepped through the "Creating a Linux BSP and System Image for the Base Design" tutorial provided by Xilinx and would now like to incorporate ethernet support as a step closer to building something closer to the MontaVista Linux reference system provided with the board. Any advice or pointers? Thanks in advance, JoeyArticle: 86912
Paul, One alternative is: Lock each clock output to a pre-defined BUFGMUX location. Then, describing each FFs in a different block (per different clock domain), assign area constraints as to place it as close as possible. Another: After you define a TNM group, specify the maximum delay (never tried this one, but it should be ok in terms of contraints) And another: Application-dependent, i.e. if you are trying to implement a QDR or somth. like this, then there is some very nice xapp for that. But what exactly is your application? Vladislav "Paul Boven" <p.boven@chello.nl> wrote in message news:1120848554.716689@blaat.sara.nl... > Hi everyone, > > I'm using all the four phase-out signals from a DCM (0, 90, 180 and 270 > degrees offset) to each clock a single D-Flipflop. > I want these flip-flops to be placed and routed as close (delay-wise) to > the DCM outputs as possible. > But I can't figure out how to set up a constraint for that: timing > constraints only seem to work on pins, flipflops, pads and latches. Can > anyone suggest how to get PAR to put the FFs as close to the DCM, with the > delays for these 4 nets as close to each other as possible ? > > Regards, Paul Boven.Article: 86913
Ray, The settings package idea is a good one. Thanks for the tip. I guess there's always a workaround. -aArticle: 86914
Hi Falk, Falk Brunner wrote: > "Paul Boven" <p.boven@chello.nl> schrieb im Newsbeitrag >>I'm using all the four phase-out signals from a DCM (0, 90, 180 and 270 >>degrees offset) to each clock a single D-Flipflop. >>I want these flip-flops to be placed and routed as close (delay-wise) to >>the DCM outputs as possible. > Just use a LOC constraint. Gives you maximum control with minimum trouble. I've been doing LOC so far. But there are 4 FFs to place around the DCM, probably 10 or more locations that might qualify depending on what routing resources are available from DCM to CLBs. The number of permutations gets a bit big, especially when scaling up to 4 DCMs and 16 flipflops. So, being lazy, I was hoping to use the software to figure out the best placement for me. > But you can define a timing group for these four clocks and define a max. > delay. Also a max skew constraint is probably a good idea. Yes, that's what I'm trying to do. Just don't know the proper syntax/commands yet. > Have a look at the xapps, there a several ones discussing clock/data > recovery at very high data rate by doing exactly what you want to do. Ah, good one that I should have thought of myself. Xapp 225 seems a good place to start. Regards, Paul Boven.Article: 86915
After looking more closely at the block diagram of the ML310: http://direct.xilinx.com/products/boards/ml310/current/images/ml310_block.jpg It looks like what I really want is to add a pci bridge on the opb bus. Given a functional bridge, it should recognize NIC on the board as a PCI device, right? Can anyone verify that I am on the right track? ThanksArticle: 86916
Hi Vladislav, everyone, Vladislav Muravin wrote: > One alternative is: > Lock each clock output to a pre-defined BUFGMUX location. That wouldn't work: I have 4 DCMs with 4 outputs each, which would require 16 BUFGMUX, but there are only 8 of them. And using a BUFGMUX seems a bit overkill for a net that only connects to one flipflop. > Then, describing each FFs in a different block (per different clock domain), > assign area constraints as to place it as close as possible. > > Another: > After you define a TNM group, specify the maximum delay (never tried this > one, but it should be ok in terms of contraints) I've figured out how to define TNM or TIMEGRP entities, but not how to apply constraints like maxdelay or maxskew to them. Any hints? > But what exactly is your application? My application is a reciprocal frequency counter. There will be two input signals: a 100MHz reference clock, and an unknown input. I want to measure the time between two rising edges of the input signal as accurately as possible. The input signal is used as the data input to 16 D-flipflops. Each flip flop is clocked from a different DCM. The first DCM provides 0, 90, 180 and 270 degrees of my original 100MHz reference. Hence, it quadruples my resolution. The second DCM has a fixed phase offset of 32 (45 degrees) and produces clock signals at 45, 135, 225 and 315 degrees, doubling my resolution once more: Using all four DCMs gives me the ability to determine where the rising edge of the input signal falls in relationship to the 100MHz input with a resolution of 22.5 degrees or 1/16th of a full phase. This corresponds to a resolution of 625ps, or an equivalent reference of 1.6 GHz. For this to work, I need to make sure that the delay from the DCM outputs to all the clock inputs on the flipflops are as equal and as low as possible. All the (single wire) nets that connect a DCM output to its flipflop, I've named "net_DCMx_y" where x = the number of the DCM (0 - 3) and Y the phase-shift of the signal. I've tried setting "net net_DCM* maxdelay=1ns;" in my UCF. I'm not sure whether it does very much: Mostly it just happily reports that it violated 6 out of 8 timing constraints. Maxskew is related to a single net, and is without meaning on nets that consist of a single wire. If I could somehow constrain the differences in delay of all the net_DCM* to be small, that would be very helpfull. Perhaps this should be possible with TNM or TIMEGRP, but I haven't been able to figure out how to use those. Any suggestions are very much appreciated. Regards, Paul Boven.Article: 86917
In the system I work on, we use Rocket IO to communication between the different boards. I see some Rocket IO failures after power up, so I wrote some scripts to do power cycle testing to charaterize the problem. I see Rocket IO communication failures after power cycle in about 3-5% of time. On some system the failures rate can be as high as 40% of time. With this particular system, the failures seem to related to how long I power down the system. When I power down the system for 1, 5 seconds between bootup, I see very few failures 3-5%. When I set the power down->up time to 20, 60 seconds, I see the failure rate go up to 40% to 50% very consistently. Once the Rocket IO enters this failurs state, the only way to recover is to power cycle the system. Reload the FPGA bit file from the sysace did not help at all. When it fails, the serial/parallel loopback on the failure board works fine, our HW engineer probe the RX of the failed channel and the signal looks ok (signals are clean and no issue.) Anyone see this kind of problem before? Any pointers on what direction to look and any idea on how one might recover from it. Thanks in advance. -TonyArticle: 86918
On Sat, 09 Jul 2005 02:06:23 +0200, Paul Boven <p.boven@chello.nl> wrote: >For this to work, I need to make sure that the delay from the DCM >outputs to all the clock inputs on the flipflops are as equal and as low >as possible. > >All the (single wire) nets that connect a DCM output to its flipflop, >I've named "net_DCMx_y" where x = the number of the DCM (0 - 3) and Y >the phase-shift of the signal. >I've tried setting "net net_DCM* maxdelay=1ns;" in my UCF. I'm not sure >whether it does very much: Mostly it just happily reports that it >violated 6 out of 8 timing constraints. > >Maxskew is related to a single net, and is without meaning on nets that >consist of a single wire. If I could somehow constrain the differences >in delay of all the net_DCM* to be small, that would be very helpfull. >Perhaps this should be possible with TNM or TIMEGRP, but I haven't been >able to figure out how to use those. > >Any suggestions are very much appreciated. > >Regards, Paul Boven. I have no idea how reliably the software handles this, but there is an attribute that tags a net's source as the starting point for time specs, TPSYNC . Maybe with this (documented in Xilinx's Constraints guide) you can spec a path that starts at the DCM, and ends at each FF. You may want to assign each FF to its own group, and have 16 separate time specs, to help you isolate problems. Regards, Philip Philip Freidin FliptronicsArticle: 86919
So, you are getting more clocks output than you are inputting? This must be the case if you are repeating codes. I guess the other possibility is that you are inadvertently sending the same code twice and your receiver is working properly. On 8 Jul 2005 08:29:21 -0700, shuo.huang@fibre.com wrote: >I used RXRECCLK to clock the output. > >Marko wrote: >> What clock are you using to clock the data out? It should not be your >> reference clock because this will not be synchronous to the data and >> you will experience a glitch periodically. You could use the >> recovered clock. This is the clock recovered from the serial data >> stream so it will be synchronous with the data. >>Article: 86920
Could this be a DCM initialization problem? You might want to bring out your various clocks and see how they look in the failure mode. On 8 Jul 2005 20:43:44 -0700, "tony.p.lee@gmail.com" <tony.p.lee@gmail.com> wrote: > >In the system I work on, we use Rocket IO to communication >between the different boards. I see some >Rocket IO failures after power up, so I wrote some >scripts to do power cycle testing to charaterize the problem. >I see Rocket IO communication failures after power cycle in about >3-5% of time. On some system the failures rate can be >as high as 40% of time. With this particular system, the >failures seem to related to how long I power down the system. > >When I power down the system for 1, 5 seconds between bootup, >I see very few failures 3-5%. When I set the power down->up time >to 20, 60 seconds, I see the failure rate go up to 40% >to 50% very consistently. > >Once the Rocket IO enters this failurs state, the only >way to recover is to power cycle the system. Reload the >FPGA bit file from the sysace did not help at all. > > >When it fails, the serial/parallel loopback on the failure >board works fine, our HW engineer probe the RX of the failed >channel and the signal looks ok (signals are clean and >no issue.) > > >Anyone see this kind of problem before? Any pointers on >what direction to look and any idea on how one might >recover from it. > > > >Thanks in advance. > >-TonyArticle: 86921
ISE Service Pack - Service Pack #3 is the latest Service Pack for Xilinx ISE 7.1i. Download the available file to ensure that your Xilinx software is up to date.Article: 86922
Marko napisał(a): > Could this be a DCM initialization problem? You might want to bring > out your various clocks and see how they look in the failure mode. > > On 8 Jul 2005 20:43:44 -0700, "tony.p.lee@gmail.com" > <tony.p.lee@gmail.com> wrote: > > >>In the system I work on, we use Rocket IO to communication >>between the different boards. I see some >>Rocket IO failures after power up, so I wrote some >>scripts to do power cycle testing to charaterize the problem. >>I see Rocket IO communication failures after power cycle in about >>3-5% of time. On some system the failures rate can be >>as high as 40% of time. With this particular system, the >>failures seem to related to how long I power down the system. >> >>When I power down the system for 1, 5 seconds between bootup, >>I see very few failures 3-5%. When I set the power down->up time >>to 20, 60 seconds, I see the failure rate go up to 40% >>to 50% very consistently. Marko napisaĹ�(a): > Could this be a DCM initialization problem? You might want to bring > out your various clocks and see how they look in the failure mode. > And look at power supply voltage behavior on digital scope. -- furiaArticle: 86923
Elektro wrote: > I will search the internet for more information and se if I can get that > book. :-) Try also googling for '"digit serial"' I think that 'bit-serial' is the simplest case of 'digit-serial', so processing algorithms are likely shared. Minnesota uni has worked on fixed function math engines using digit serial processing, and did have a project for a general-purpose processor based on these techniques. Jan Cooombs -- murray-microft ltdArticle: 86924
"elcielo" <kyson@paran-dot-com.no-spam.invalid> schrieb im Newsbeitrag news:QeSdnWH_a6kpGlLfRVn_vg@giganews.com... > ISE Service Pack - Service Pack #3 is the latest Service Pack for > Xilinx ISE 7.1i. Download the available file to ensure that your > Xilinx software is up to date. > the issue was actually observable also with 7.1SP2 and spartan3, and Xilinx response was that the issue is most likely not addressed in SP3 as it was rather rare case: * 32 bit counters (n number of them) all clocked from different clocks, use n global clocks * JTAG BSCAN, some outputs auto promoted to use BUFG by 7.1 SP2 as ISE inserted BUFG on DRCK1 from BSCAN then total number of global clocks exceeded 8, and as the 32 bit counters as RPM do not fit into a quadrant then the resulting design did not route. (limitation of global clocks that can enter a single quadrant) to my surprise the issus has been solved in SP3, the designs do not fail any more on routing, but without manually setting 'buffer_type' the auto allocation of the BUFG is wrong, so I still need to manually 'disable' some of the BUFG insertion. in SP3 8 clocks are selected to be Global (at random?) the rest goes with local routing, when 'false' clocks as are set to buffer_type=none then the actual clocks are detected ok Antti
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