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Arash is correct that the Quartus built-in simulator doesn't support the file I/O you'll need to easily compare to Matlab, so you are better off using the ModelSim simulator. I assume your Matlab flow looks like: Filter input file -> Read filter inputs -> Filter -> Write Filter Outputs to File You can perform a simular flow in ModelSim with these steps: 1) Compile the design in Quartus 2) Select Modelsim (Verilog) as the simulation tool 3) Generate EDA Simulation Netlist 4) Design a testbench (similar to the Matlab flow) that instantiates this netlist in Modelsim: [Read Filter Inputs] => use fopen, fscanf, fclose commands Pass these filter inputs into the netlist (which is presumably the filter) Print the outputs to a file using the fopen, fprintf, fclose commands 5) Run the testbench in Modelsim 6) Compare the output of the Matlab simulation with the output of the Modelsim simulation. If you got the format exactly the same, and you expect exactly equivalent output, you could use the diff command on the files. If you expect slight round-off etc. differences and just want to check the filter gives the correct spectral properties, you could read the filter output into Matlab now and Fourier transform it etc. to see if it is doing what you want. Hope this helps. Vaughn Altera [v b e t z (at) altera.com]Article: 87151
Hi Dan, Not sure if you've tried this one already, but in case you haven't, there is a good tutorial that ships with Quartus. Look in Help -> PDF Tutorials -> PDF Tutorial for VHDL (or the Verilog version if you prefer). You may also want to check out the on-line demos at www.altera.com/quartusdemos. Regards, Vaughn Altera [v b e t z (at) altera.com] "farnel" <d_tonkes@fanshaweonline.ca> wrote in message news:1120953276.245190.228410@f14g2000cwb.googlegroups.com... > Looking for some help/advice in using Altera QII-WE. I am an > electronics student working with MSI & SSI 7400LS chip sets.My current > school places no empahsis on PLD`s at all. I am changing schools to one > which uses the quartus system and would like to get up-to-speed before > starting. I would like some links or information to help bridge the gap > between the two styles of learning. I have looked at the Altera > tutorial, but I was hoping someone may have some other introductory > training material available. > Thanks, Dan. >Article: 87152
Can you clarify what is happening? Are you saying that when you simulate a subdesign, or the whole design, all its outputs look OK, but when you run the entire design in hardware it doesn't work? Or are you saying that when you simulate the whole design the simulation does not pass, even though the components worked? The likely problems are different in those two cases. Vaughn Altera [v b e t z (at) altera.com] "tns" <tns1@cox.net> wrote in message news:de3Be.8730$Eo.918@fed1read04... > This is useful, but not what I need right now. I am now faced with the > problem of having a good timing sim, but a non-functioning design. > Essential signals that appear OK in the sub-project sim are being removed > somehow when I compile the whole project. What would cause the sim results > to be incorrect? > > I have a verilog top module which contains both verilog and vhdl modules. > Is there some strange rule about connecting ports when mixing language > modules? I am only having problems with the vhdl outputs. > > > > Vaughn Betz wrote: > >> See http://www.altera.com/support/kdb/2003/05/rd05142003_7103.html >> >> It describes how to use the "keep" attribute to preserve a combinational >> node, and the "preserve" attribute to preserve a register. If you set >> the appropriate attribute on a node, it will prevent the optimization >> algorithms from removing it, even if that would result in a more >> efficient circuit. Hence you can select and view it in a simulator after >> compilation (either functional or timing simulation). As some other >> posters have pointed out, you can also bring the signal out to a pin, >> which is an indirect way of forcing it to be preserved -- this is often >> less convenient in a large design, however. >> >> See the Quartus online help for examples of the precise syntax to use to >> set these attributes. >> >> Regards, >> >> Vaughn >> Altera >> [v b e t z (at) altera.com] >> >> "tns1" <tns1@cox.net> wrote in message >> news:wWEAe.8412$Eo.7045@fed1read04... >> >>>Many of the nodes I want to probe seem unavailable in the simulation. >>>They are either optimized away, or refuse to show up in the simulation >>>window even when selected in the vwf. >>> >>>Is there a way to prevent this from happening such as a setting an >>>optimization level or marking registers so they will be available? >>> >>>thanks >>> >> >> >> >Article: 87153
I'm interested in knowing if there are any currently in-production
FPGAs (ie not EOL'ed or as-yet-unreleased) that support any degree of
partial reconfiguration, even if not supported by the vendor.
Atmel's chips have awesome, incredible partial reconfiguration
abilities. Pretty much everything you could want.
Xilinx' more recent chips support partial reconfiguration at
column-level granularity, although if you read-modify-write you can
get glitchless updates at logic-block granularity. Reconfiguring
routing this way is officially disavowed by Xilinx except under a
highly constrained set of conditions (bus macros, modules must be as
tall as the device, etc). Better partial reconfig is probably
possible, but not advertised by the vendor.
I'm not terribly familiar with anybody else's chips aside from
Altera's (which definately do not have any useful degree of partial
reconfig ability whatsoever [*]), so I'd like to know if there are any
other vendors I should know about who offer some degree of partial
reconfigurability.
[*] for the record, I consider "useful" to mean without clearing the
state of the device (ie flip-flops).
Article: 87154I've heard this rumor many times from different sources: that Virtex4 TBUFs don't actually have tri-state buffers in them, and that they're actually implemented as a set of wires and muxes which is logically (though not electrically) equivalent to everything you could do if they were. Has Xilinx ever gone on-record with any complete or partial answer to this question? I can't find anything in the app notes. If this is true, I'm pretty baffled as to how you could have long lines. To implement an equivalent structure without tri-state buffers, you'd need to replace each long line with N wires where N is the number of "possible drivers" -- a pretty large number. Isn't that rather inefficient?Article: 87155
"Jack Falk" <falkjack@yahoo.com> schrieb im Newsbeitrag news:1121670459.198454.152210@g43g2000cwa.googlegroups.com... > I've heard this rumor many times from different sources: that Virtex4 > TBUFs don't actually have tri-state buffers in them, and that they're > actually implemented as a set of wires and muxes which is logically > (though not electrically) equivalent to everything you could do if > they were. > > Has Xilinx ever gone on-record with any complete or partial answer to > this question? I can't find anything in the app notes. > > If this is true, I'm pretty baffled as to how you could have long > lines. To implement an equivalent structure without tri-state > buffers, you'd need to replace each long line with N wires where N is > the number of "possible drivers" -- a pretty large number. Isn't that > rather inefficient? > how official do you need to have it? There are NO TBUFs in any of the new Xilinx FPGAs !! Spartan-3, 3E, V4 : NO TBUFs (all other older familes are not to be used anyway) so the TBUFs are gone forever :( in S2 it was possible to get huge savings in some designs by using TBUFs, those designs will not fit into the S3 of same slice count. So not everything gets better in new familes. AnttiArticle: 87156
"Jack Falk" <falkjack@yahoo.com> schrieb im Newsbeitrag news:1121670209.513678.206420@g14g2000cwa.googlegroups.com... > I'm interested in knowing if there are any currently in-production > FPGAs (ie not EOL'ed or as-yet-unreleased) that support any degree of > partial reconfiguration, even if not supported by the vendor. > > Atmel's chips have awesome, incredible partial reconfiguration > abilities. Pretty much everything you could want. > > Xilinx' more recent chips support partial reconfiguration at > column-level granularity, although if you read-modify-write you can > get glitchless updates at logic-block granularity. Reconfiguring > routing this way is officially disavowed by Xilinx except under a > highly constrained set of conditions (bus macros, modules must be as > tall as the device, etc). Better partial reconfig is probably > possible, but not advertised by the vendor. > > I'm not terribly familiar with anybody else's chips aside from > Altera's (which definately do not have any useful degree of partial > reconfig ability whatsoever [*]), so I'd like to know if there are any > other vendors I should know about who offer some degree of partial > reconfigurability. > > [*] for the record, I consider "useful" to mean without clearing the > state of the device (ie flip-flops). > not known as any publicly available information :( Atmel reconfig is nice, I even have the secret docu about all the bits :) Xilinx is a bit more problematic as they dont have that degree of flexibility and docu is partially missing and the tool flow is not supported well. as only unknown is the new beastie from ST, I would be not surprised if that can be partially configured, but there is no info about that yet. AnttiArticle: 87157
Hi - On Mon, 18 Jul 2005 09:16:28 +0200, "Antti Lukats" <antti@openchip.org> wrote: >"Jack Falk" <falkjack@yahoo.com> schrieb im Newsbeitrag >news:1121670459.198454.152210@g43g2000cwa.googlegroups.com... >> I've heard this rumor many times from different sources: that Virtex4 >> TBUFs don't actually have tri-state buffers in them, and that they're >> actually implemented as a set of wires and muxes which is logically >> (though not electrically) equivalent to everything you could do if >> they were. >> >> Has Xilinx ever gone on-record with any complete or partial answer to >> this question? I can't find anything in the app notes. >> >> If this is true, I'm pretty baffled as to how you could have long >> lines. To implement an equivalent structure without tri-state >> buffers, you'd need to replace each long line with N wires where N is >> the number of "possible drivers" -- a pretty large number. Isn't that >> rather inefficient? >> > >how official do you need to have it? > >There are NO TBUFs in any of the new Xilinx FPGAs !! > >Spartan-3, 3E, V4 : NO TBUFs > >(all other older familes are not to be used anyway) so the TBUFs are gone >forever :( > >in S2 it was possible to get huge savings in some designs by using TBUFs, >those designs will not fit into the S3 of same slice count. So not >everything gets better in new familes. > >Antti > Hold the phone there, kids. You're talking about two different things: 1) Some of the earlier Virtex devices, e.g., Virtex II, had internal TriState buffers that were actually implemented with AND/OR logic. So there were things called TriState buffers that were TriState in name only. Not that there's anything wrong with that. 2) Internally, parts like Virtex 4 have neither real TriState buffers nor pseudo-TriState buffers. Of course, all Virtex parts have TriStateable I/O drivers. Personally, I liked the internal TriState buffers, real or pseudo; they were useful for building things like slow processor readback paths. And as best I can recall, they were free of errata. Those were the days. Bob Perlman Cambrian Design WorksArticle: 87158
Dear Sir, Thanks a lot for your kind reply and also for clearing my doubts. Expecting your help in future and also requesting you sir to contribute more and more towards this direction, I stops hereArticle: 87159
Hi not so long time Xilinx projected 'general customer' availabily of S3E 500 devices mid-july (2005), any update on that? AnttiArticle: 87160
Andy Peters wrote: > The trick is that you need a reset signal, but helpful the FPGA > families have power-on global resets that are asserted as part of the > configuration process. > > -a You don't really need a reset signal, just a reset process. The flip-flop you designed could be instantiated with rst_l tied high at a higher level of hierarchy, but the initialization value after download would still match the value from the reset process.Article: 87161
"Heiko Kalte" <kalte@csse.uwa.edu.au> schrieb im Newsbeitrag news:db7djq$eb5$1@enyo.uwa.edu.au... > Hi, > is there any difference between Virtex-II and Virtex-4 5V tolerence? I did > not find any information about that. I want to connect 5V outputs to > Virtex-4 inputs. I read all the articles about 174ohm resistors and > QuickSwitch. Does all that apply to Virtex-4, too? > Regards > Heiko > you can assume pretty much the same applies, yes. AnttiArticle: 87162
Hi all, I've a trouble with creating libraries of object code using the powerpc-eabi tools from EDK. I have to file one.c and two.c They are compiled with powerpc-eabi-gcc -c one.c two.c It produces the files one.o and two.o To create a library, I do : powerpc-eabi-ar crus libMylib.a one.o two.o Then I compile the application test.c powerpc-eabi-gcc -L. -Lppc405_0/lib -lMylib -Wl,-T -Wl,./MyLinkerScript test.c This FAILS : symbols from libMylib.a are said missing. If I add the option -Wl,--verbose, I get the message ld:attempt to open ./libMylib.a succeeded but the files one.o and two.o are not listed. It's very strange because powerpc-eabi-ar t libMylib.a list the two files. The point is that the following command works nice powerpc-eabi-gcc -L. -Lppc405_0/lib -lMylib -Wl,-T -Wl,./MyLinkerScript one.o two.o test.c so the symbols are in the two .o files. Please, can someone tell me what's wrong with the library creation ? Is there a conflict with the linker script ? thanks a lot for your help StéphaneArticle: 87163
Hi there, I've been using EDK/ISE on my desktop machine to build a design, and now want to download that design on using a spare machine in our test lab (rather than just using dev boards on my desktop). ISE comes with a "Lab PC" install CD with impact on it, which is good, but I need a sort of EDK equivelent - my design uses program code held in the dev board's SDRAM, and I've been using xmd/gdb frontend to download this part of the design. >From what I can see, there's not "lab install" equiv for EDK - does this mean I need to get yet another license just to sit on the lab machine that'll be used for downloading my designs? Or is there some other solution? Thanks in advance for any advice, -- MichaelArticle: 87164
Hi Here purchased a XUP VIIpro board (Digilent) today and trying a test with no success :) I am using EDK / ISE 6.3i with latest software update, Windows XP laptop PC. It seems to have two problems. First, when I first power-on, 'SYSTEM ACE' LED blinks in red, meaning something is wrong. According to the hardware manual ug069, " JTAG configuration is by default from the Compact Flash. If a JTAG-based configuration is selected and a valid configuartion file is not found on the Comppact Flash card, the SYSTEM ACE ERROR LED flashes. " One thing is that I do not have a Flash card !! -: It seems that I need to change jumpers or switches (i am not sure), but no idea how to manage this. Second, when I first USB-connected between PC and the board, Windows machine automatically tried to find a device driver. Then something popped up saying " Hi speed USB device plugged into non-hi speed USB hub. ....will function at reduced speed ". Still I am not sure if those 2 problems are really problems -: Anyway when I run 'hyperterminal' (with correct setting - 9600baud, 8data bits, No Parity, 1 Stop bit and No flow control), nothing appears in hyperterminal. So it should be something wrong. My goal is to configure using USB cable without Flash card and run 'hello world' with microblaze :) If someone has this experience (especially with XUP board), let me know how to shoot trouble. Thankyou in advanceArticle: 87165
What might be of use to you is to remotely run your programming cable. A relatively new facility (came in 7.1 I believe) it uses a utility "cableserver" locally so that you can access the programming cable remotely. I have only used this for programming platform flash remotely but I believe that it's use can also be with chipscope and the other EDK tools. "Cableserver" comes in the webpack version of tools so you don't need to purchase a license for the lab machine if you don't need any other tools. John Adair Enterpoint Ltd. - Home of PROG1, The cheap CoolRunner-2 and Spartan-3 programming cable. http://www.enterpoint.co.uk "Michael Dales" <mdales@gmail.com> wrote in message news:1121691449.856192.99150@o13g2000cwo.googlegroups.com... > Hi there, > > I've been using EDK/ISE on my desktop machine to build a design, and > now want to download that design on using a spare machine in our test > lab (rather than just using dev boards on my desktop). ISE comes with a > "Lab PC" install CD with impact on it, which is good, but I need a sort > of EDK equivelent - my design uses program code held in the dev board's > SDRAM, and I've been using xmd/gdb frontend to download this part of > the design. > >>From what I can see, there's not "lab install" equiv for EDK - does > this mean I need to get yet another license just to sit on the lab > machine that'll be used for downloading my designs? Or is there some > other solution? > > Thanks in advance for any advice, > > -- Michael >Article: 87166
Finally launched! additional features (what I did not know) 1) standby 2) 20MHz on chip oscillator 3) distributed memory in all devices and first devices should be available already !! WAU!! AnttiArticle: 87167
Try this code. > --------------- test code (start) --------------------- > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.STD_LOGIC_ARITH.ALL; > use IEEE.STD_LOGIC_UNSIGNED.ALL; > > entity test1 is > Port ( rst : in std_logic; > clk : in std_logic; > a : in std_logic_vector(7 downto 0); > b : in std_logic_vector(7 downto 0); > sum : out std_logic_vector(7 downto 0); > prod : out std_logic_vector(15 downto 0)); > end test1; > > architecture Behavioral of test1 is > signal a1, b1 : std_logic_vector(7 downto 0); signal sum1 : std_logic_vector(7 downto 0); signal prod1 : std_logic_vector(15 downto 0); > begin > > process (rst, clk) > begin > if rst='1' then > a1 <= (sum'range=>'0'); > b1 <= (prod'range=>'0'); > elsif clk'event and clk='1' then > a1 <= a ; > b1 <= b; > end if; > end process; > sum1 <= a1 + b1; > prod1 <= a1 * b1; > process (rst, clk) > begin > if rst='1' then > sum <= (sum'range=>'0'); > prod <= (prod'range=>'0'); > elsif clk'event and clk='1' then > sum <= sum1; > prod <= prod1; > end if; > end process; > > end Behavioral; > --------------- test code (end) ----------------------- > > > Testbench of test1.vhd that i use. > > --------------- testbench for test code (start) ------- > LIBRARY ieee; > USE ieee.std_logic_1164.ALL; > USE ieee.std_logic_arith.all; > use ieee.std_logic_unsigned.all; > > ENTITY test1_tb_test1_vhd_tb IS > END test1_tb_test1_vhd_tb; > > ARCHITECTURE behavior OF test1_tb_test1_vhd_tb IS > > COMPONENT test1 > PORT( > rst : IN std_logic; > clk : IN std_logic; > a : IN std_logic_vector(7 downto 0); > b : IN std_logic_vector(7 downto 0); > sum : OUT std_logic_vector(7 downto 0); > prod : OUT std_logic_vector(15 downto 0) > ); > END COMPONENT; > > SIGNAL rst : std_logic; > SIGNAL clk : std_logic; > SIGNAL a : std_logic_vector(7 downto 0); > SIGNAL b : std_logic_vector(7 downto 0); > SIGNAL sum : std_logic_vector(7 downto 0); > SIGNAL prod : std_logic_vector(15 downto 0); > > BEGIN > > uut: test1 PORT MAP( > rst => rst, > clk => clk, > a => a, > b => b, > sum => sum, > prod => prod > ); > > clk_gen : PROCESS > BEGIN > if clk='0' then > clk <= '1'; > else > clk <= '0'; > end if; > wait for 100 ns; > END PROCESS; > > tb : PROCESS > BEGIN > wait for 100 ns; > > rst <= '1'; > a <= conv_std_logic_vector (0, 8); > b <= conv_std_logic_vector (0, 8); > for i in 1 to 10 loop > wait until clk'event and clk='1'; > end loop; > wait for 1 ns; > > rst <= '0'; > for i in 1 to 10 loop > wait until clk'event and clk='1'; > end loop; I think the main problem is here. You were voilating setup and hold times. Changing the data at the falling edge of the clock should slove the problem for your older code too. > wait until clk'event and clk='0'; > > a <= conv_std_logic_vector (11, 8); > b <= conv_std_logic_vector (13, 8); > wait until clk'event and clk='0'; > wait for 1 ns; > > a <= conv_std_logic_vector (77, 8); > b <= conv_std_logic_vector (19, 8); > wait until clk'event and clk='1'; > wait for 1 ns; > > wait; -- will wait forever > END PROCESS; > > END; > --------------- testbench for test code (end) ---------Article: 87168
Will need to prod our sys-admin to get the lab machine put on the network, but that certainly sounds like an option. Cheers for that, that might be the solution we need, assuming EDK will play ball. Ta, -- Michael John Adair wrote: > What might be of use to you is to remotely run your programming cable. A > relatively new facility (came in 7.1 I believe) it uses a utility > "cableserver" locally so that you can access the programming cable remotely. > I have only used this for programming platform flash remotely but I believe > that it's use can also be with chipscope and the other EDK tools. > "Cableserver" comes in the webpack version of tools so you don't need to > purchase a license for the lab machine if you don't need any other tools. > > John Adair > Enterpoint Ltd. - Home of PROG1, The cheap CoolRunner-2 and Spartan-3 > programming cable. > http://www.enterpoint.co.uk > > "Michael Dales" <mdales@gmail.com> wrote in message > news:1121691449.856192.99150@o13g2000cwo.googlegroups.com... > > Hi there, > > > > I've been using EDK/ISE on my desktop machine to build a design, and > > now want to download that design on using a spare machine in our test > > lab (rather than just using dev boards on my desktop). ISE comes with a > > "Lab PC" install CD with impact on it, which is good, but I need a sort > > of EDK equivelent - my design uses program code held in the dev board's > > SDRAM, and I've been using xmd/gdb frontend to download this part of > > the design. > > > >>From what I can see, there's not "lab install" equiv for EDK - does > > this mean I need to get yet another license just to sit on the lab > > machine that'll be used for downloading my designs? Or is there some > > other solution? > > > > Thanks in advance for any advice, > > > > -- Michael > >Article: 87169
I'm planning to buy WS edition. There is someone which has tried Webpack with that operating system? Thanks MarcoArticle: 87170
Hello, Can anybody give me an estimate price range of the two smallest Virtex-4 devices, namely LX15 and LX25? I am interested in the lowest speed grade and SF363 package. I have been trying to get it from distributor for the past few weeks and ... Thank you all for your time and attention. Sincerely, VladislavArticle: 87171
yes, xilinx gives a reference design for ml403 board which has virtex 4 fx12 on it. visit www.xilinx.com/gsrd, I have already used hard TEMAC with this. regards RajeshArticle: 87172
"Vladislav Muravin" <muravinv@advantech.ca> schrieb im Newsbeitrag news:QwQCe.922$Qi4.217439@news20.bellglobal.com... > Hello, > > Can anybody give me an estimate price range of the two smallest Virtex-4 > devices, namely LX15 and LX25? > I am interested in the lowest speed grade and SF363 package. > I have been trying to get it from distributor for the past few weeks and ... > > Thank you all for your time and attention. > > Sincerely, > Vladislav > this has been asked here many times: small qty about 100$, LX25 a bit more there isnt much in V4 that goes below 100 in small qty AnttiArticle: 87173
Antti, Despite that I am trying to, I am not able to read every single posting in this newsgroup. But thanks for the answer, appreciate it. Vladislav "Antti Lukats" <antti@openchip.org> wrote in message news:dbgli3$t3r$02$1@news.t-online.com... > "Vladislav Muravin" <muravinv@advantech.ca> schrieb im Newsbeitrag > news:QwQCe.922$Qi4.217439@news20.bellglobal.com... >> Hello, >> >> Can anybody give me an estimate price range of the two smallest Virtex-4 >> devices, namely LX15 and LX25? >> I am interested in the lowest speed grade and SF363 package. >> I have been trying to get it from distributor for the past few weeks and > ... >> >> Thank you all for your time and attention. >> >> Sincerely, >> Vladislav >> > this has been asked here many times: small qty about 100$, LX25 a bit more > > there isnt much in V4 that goes below 100 in small qty > > Antti > > > > >Article: 87174
Correlious wrote: > Are you looking for bi directional I/O, or a one way? > it would be one way
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