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Hi, is there any difference between Virtex-II and Virtex-4 5V tolerence? I did not find any information about that. I want to connect 5V outputs to Virtex-4 inputs. I read all the articles about 174ohm resistors and QuickSwitch. Does all that apply to Virtex-4, too? Regards HeikoArticle: 87101
<bjskill@rocketmail.com> schrieb im Newsbeitrag news:1121398768.643168.106640@o13g2000cwo.googlegroups.com... > Hi, > > We will soon be using the Nios II as embedded controller and we would > like to add a High Speed (HS) USB 2.0 hosting feature that is capable > or providing a sustained transfer rate of 20 MBytes/sec. to an external > HS USB 2.0 device. > > I realize that there are a limited number of HS USB 2.0 hosts > devices/IP cores currently available. The Phillips ISP1761 is the only > HS USB 2.0 component I was able to locate so far and it's not clear to > me if this part is readily available. Also, the FPGA-based HS USB 2.0 > host IP cores look like they are just now becoming available > (www.asics.ws) but they may be cost-prohibitive. > > Can anyone share their experiences in implementing either a HS USB 2.0 > or Full Speed (FS) USB 1.1 host? Is a sustained transfer speed of 20 > MBytes/sec. achievable with the assumptions that there are no major > transfer bottlenecks in the HS USB 2.0 host component or the associated > HS USB 2.0 device (e.g. USB Hard Disk). If not, what is a more > reasonable transfer speed goal that has a high probability of success? > > The choice of which OS with Nios II (or no OS at all) may also be > influenced by the max. sustained HS USB 2.0 transfer speed that can be > achieved. However, it's also possible that in order to meet the 20 > MBytes/sec. goal, the Nios II will have to be "removed" from the data > I/O path so that custom FPGA circuitry can handle the transfers > directly with the external HS USB 2.0 host transceiver or the IP core. > > Any information and/or opinions would be helpful. > > Sincerely, > Brad. > ISP1761 is readily available, the proove is there http://www.hydraxc.com ISP1761 (in BGA) is on lower side of the PCB. non BGA version has been available for some time already, the BGA version (0.5mm pitch!) did become available April/June 2005. and yes, you are about correct for max sustained dataflow the high speed traffic should bypass the processor, that could be done by dedicated DMA and ISP1761 AnttiArticle: 87102
Hi! I have downloaded the MPEG-packages from Xilinx (Application notes 610,615,616 and 621) and I have trouble compiling the VHDL-code. In the Huffman encoder, several cases in one of the case segments have the same condition. And the eob signal in the run-length encoder is declared OUT, but read twice in the code. Has anyone used these files successfully and would like to share the necessary adjustments? Regards Johan RiesbeckArticle: 87103
Cogradulations..........Plz send C compiler for picoblaze with manual at fahadislam2002@hotmail.com .......thanksArticle: 87104
Hi, There have been different claims of being faster and bigger from different sides. The best thing to know it for real is to perform actual testing of the silicon (and not to believe the marketing stuff), I can present some results of actual measurements: DUT: Spartan 3S1500-4C-fg676 ES, measured normal ambient temperature LUT propagation delay as measured (measured was a t_LUT+t_switchbox): 595 ps Xilinx datasheet says 610 max propagation delay what matches very well with the actual measurement, I would estiamate switcbox delay of 30-60ps so the resulting LUT delay is about 10% than the max in datasheet. Measured clock frequency where the logic in the FPGA fabric was operational: 420MHz Some notes: 420MHz is not the limit, we just did not do any tests at higher frequencies. the 420MHz clock was not derived from DCM (its above the recommended limits of DCM), measurements how high can DCMs actually go was not done, most likely way over 420MHz. fanout and/or routing of the high clock really is critical :) but that is to be expected, we did see some erratic behaviour when the 420MHz was travelling longer distances in the FPGA (1/3 of the length of the array). the test design was run with ABSOLUTLY NO timing constraints applied, all the critical path components where locked down directly to FPGA slices. Please use the test results with care, the actual perfomance that can be achived is totally desing dependant. Our measurement just shows that using signal as high as 420MHz is defenetly possible in the lowest speed Spartan-3. So the fabric can go really high if the tools do the their job correct. All the results are from actual measurements with real silicon, so not biased from any marketing claims or based on unverified data. antti@truedream.org PS I could do some measurements to compare the competitor parts as well. All I need are DUTs hardware for measurements. The test designs and measurement appliction software can be used for any FPGA/PLD.Article: 87105
praetorian wrote: > To my understanding, bus macros are tri-state buffers at relative fixed > positions according to XAPP290. I'd like to implement my own bus macros > to be used for a small detacheable module (run-time reconfiguration), > but I cannot find a way to instantiate the tristate primitives in CLBs > in my VHDL. I could only get tristates by specifying this: > > output <= input when t = '1' else 'Z'; > > is there anyway to specifically instantiate a tristate primitive, > preferably with location constraint? You can instantiate BUFT. See the libraries guide in the online documentation. By the way, a BUFT actually implements: output <= input when t = '0' else 'Z';Article: 87106
"jeff murphy" <jeff.murphy@gmail.com> writes: > thanks, that was, ofcourse, exactly the problem. is there a faq on why > i should use std.all instead of arith.all unsigned.all? ISE inserts the > use statements for me... so i was just trusting that it put in the > appropriate statements. > See here http://tech-www.informatik.uni-hamburg.de/vhdl/doc/faq/FAQ1.html#4.8 I wish Xilinx would get themselves up-to-date on this front. Numeric_std has been around a hell of a long time! Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 87107
"Antti Lukats" <antti@openchip.org> wrote in message news:db86sg$ued$00$1@news.t-online.com... > Hi, > > There have been different claims of being faster and bigger from different > sides. The best thing to know it for real is to perform actual testing of > the silicon (and not to believe the marketing stuff), I can present some > results of actual measurements: > > DUT: Spartan 3S1500-4C-fg676 ES, measured normal ambient temperature > > LUT propagation delay as measured (measured was a t_LUT+t_switchbox): 595 ps > > Xilinx datasheet says 610 max propagation delay what matches very well with > the actual measurement, I would estiamate switcbox delay of 30-60ps so the > resulting LUT delay is about 10% than the max in datasheet. > > Measured clock frequency where the logic in the FPGA fabric was operational: > 420MHz AND theres a -5 Cheers, AlfArticle: 87108
What will be the status of F/F and internal block RAMs of VirtexE FPGA if i do not specify any initial condition. Can i assume that it is zero ?Article: 87109
What will be the conditions of the F/F and internal block RAM if i didnt specified any initial value. Can i assume that its zero ??Article: 87110
Hallo, I would use webpack on linux. I would know if ISE Webpack 7.1 for Red Hat enterprise functions on Fedora. If I download Fedora 64 bit version, Webpack ISE 32 bit function in any case? May I upgrade in future webpack to foundation without installing it and inserting the key registered with Xilinx site? Which Simulator should I use? ModelSim XE? Many Thanks Maco ToschiArticle: 87111
I used the syn_preserve synplify attribute in my VHDL code as below. attribute syn_preserve of sign1: signal is true; Modelsim gives compilation error for this? Any help to rid of this would be appreciated. Thanks, MuthuArticle: 87112
On Thu, 14 Jul 2005 15:04:53 -0700, Mike Treseler <mike_treseler@comcast.net> wrote: >jjohnson@cs.ucf.edu wrote: >> Does anyone know where I can find a public domain / open source tool >> that will read a bunch of VHDL and/or Verilog files, and generate a >> block diagram from them? > >I don't think there is one. >Quartus/Mentor/Synplicity have an hdl viewer >that can do entity boxes and wires. >Modelsim has a data flow viewer that shows >processes and signals. > >What would you do with this diagram >if you had it? I have found the Quartus RTL Viewer a tremendous help in developing a feel for what logic would be generated by what code. It is also immediately obvious if one has left out a default value for a case structure and other simple errors that make a huge difference in the generated logic. >If the aim were to learn a design by others, >I would write a testbench and watch >it run on a simulator. > >If the aim were to document the >design, I would do it as comments >in the source and testbench code. It has also been useful where clients have insisted that they want a schematic version of the EPLD code. Regards Anton ErasmusArticle: 87113
Internal BlockRAMs will initialize to zero unless you specify other values. Some BlockRAM outputs (but not on Virtex-E) have an initial state for the synchronous output specifiable. The initial state of the registers is a little less obvious. If a register is preset without a clear or set without a reset (using the S/R input) the register will initialize high. If a register isn't preset or set, it will initialize low. This includes registers that are reset, cleared, or have no S/R control. I use the terms "preset" and "clear" for asynchronous events and "set" and "reset" for synchronous. "vssumesh" <vssumesh_asic@yahoo.com> wrote in message news:1121435487.213730.287320@z14g2000cwz.googlegroups.com... > What will be the status of F/F and internal block RAMs of VirtexE FPGA > if i do not specify any initial condition. Can i assume that it is zero > ?Article: 87114
Coments at end:
"Paul Solomon" <psolomon@tpg.com.au> wrote in message
news:42d721a9$1@dnews.tpgi.com.au...
> Hi John,
>
> I have done some further ingestigation this morning, found out a few other
> things, albeit frustrating things.
>
> 1. You are right in that the modulo operation is not occuring in 12.5ns,
> this section of the design is in the order of 43ns.
> 2. The design that simulated perfectly in Modelsim, does not actually
work.
>
> I have synthesised, fitted, and written a netlist out (to a vo file) and
> simulated this in modelsim and it does not work.
> At first I thought it was the clock going to fast, but I have slowed the
> clock right down (to 200ns) and it is still not making any sense.
>
> I have also tried the same simulation in Quartus and I appear to be
getting
> garbage out.
>
> Do you know what I should be looking for, what kind of things could cause
a
> discrepancy between the simulated verilog code and the
> simulated vo output?
>
> both the simulators and the synthesis tool is set for verilog-2001.
>
> btw to answer your other questions the bus width is 16bit and the mod is
> always 12868.
>
> Regards,
>
> Paul Solomon
Good news: the remainder won't be too hard to develop.
First, simulation versus synthesis:
There are some things that just don't synthesize or won't synthesize well.
Consider the wait operator (e.g., #12); it won't synthesize. Consider
division. It can be synthesized but the results are too area-intensive and
the nuances on the input/output ranges too great to come up with a solution
that will apply to every application. The modulus you seek is division.
Since the 16 bits have a maximum of 65535 and the modulus is fixed at 12868
gives a maximum integer divide of 5. Three bits of integer result means you
need only three stages of compare with conditional subtract.
stage1 = value-(14'd12868<<2);
result1 = stage1<0 ? value : stage1;
stage2 = result1-(14'd12868<<1);
result2 = stage2<0 ? value : stage2;
stage3 = result2-14'd12868;
finalResult = stage3<0 ? value : stage3;
It should be quicker to implement a little different than the long division
equivalent above, specifically
newStage1 = value-(14'd12868<<2);
newStage2 = newStage1 + (newStage1<0 ? 14'd12868<<1 : -14'd12868<<1);
newStage3 = newStage2 + (newStage2<0 ? 14'd12868 : -14'd12868);
finalResult = newStage3<0 ? newStage2 : newStage3;
where I *think* I have my flow accurate. Check it before implementing.
You could also do 4 subtracts and choose the first non-negative value
compare5 = value - (14'd12868*5);
compare4 = value - (14'd12868*4);
compare3 = value - (14'd12868*3);
compare2 = value - (14'd12868*2);
compare1 = value - 14'd12868;
finalResult = compare3<0 ? compare1<0 ? value : compare2<0 ? compare1 :
compare2
: compare4<0 ? compare3 :
compare5<0 ?compare4 : compare5;
I'm a Xilinx guy so my coding style (this last finalResult version fits nice
in a MUXF6 structure, for instance) might be skewed a little from Altera but
the idea should carry through.
Happy coding!
Article: 87115Gabor wrote: > > praetorian wrote: > >>To my understanding, bus macros are tri-state buffers at relative fixed >>positions according to XAPP290. I'd like to implement my own bus macros >>to be used for a small detacheable module (run-time reconfiguration), >>but I cannot find a way to instantiate the tristate primitives in CLBs >>in my VHDL. I could only get tristates by specifying this: >> >>output <= input when t = '1' else 'Z'; >> >>is there anyway to specifically instantiate a tristate primitive, >>preferably with location constraint? > > > You can instantiate BUFT. See the libraries guide in the online > documentation. By the way, a BUFT actually implements: > > output <= input when t = '0' else 'Z'; > I was looking through the Virtex 2/Virtex 2Pro User Guide (ug012.pdf). The guide does not have anything regarding the BUFT inside a CLB. Could you give me a link to the libraries guide you are talking about? Thank youArticle: 87116
i couldn't even get webpack to install on RH. i did a plain vanilla install of RHWS3, but the webpack installer crashes (seg fault) after you do all the click-thrus and just as it starts unpacking files. i then patched up WS3 with up2date, hoping that it was just some bug in a library, but webpack's installer still crashed. anyone know how to successfully install webpack on linux?Article: 87117
FPGA 2006: Call for Papers
Fourteenth ACM/SIGDA International Symposium
on Field-Programmable Gate Arrays
Hyatt Regency Hotel
Monterey, California
February 22-24, 2006
----------------------------------------------------------------
The ACM/SIGDA International Symposium on Field-Programmable Gate
Arrays is the premier conference for presentation of advances in
all areas related to FPGA technology. For FPGA 2006, we are
soliciting submissions describing novel research and developments
in the following (and related) areas of interest:
FPGA Architecture:
Novel logic block and routing architectures, combination of
FPGA fabric and system blocks (processors, memories, etc.),
new commercial architectures, impact of modern and future
technologies (including ultra-deep submicron and nanometer
scale) on the design of FPGA's (e.g. soft errors, leakage,
power density, fabrication defects).
Circuit Design for FPGAs:
Novel FPGA circuits and circuit-level techniques.
CAD for FPGAs:
Placement, routing, retiming, logic optimization, technology
mapping, system-level partitioning, logic generators, testing
and verification, CAD for FPGA-based accelerators, CAD for
incremental FPGA design and on-line design mapping and
optimization.
High-level abstractions, tools, and systems for FPGAs:
General-purpose and domain-specific models, languages, tools,
and techniques that facilitate the design, development,
debugging, verification, and deployment of large-scale and
high-performance FPGA-based applications and systems.
FPGA-based and FPGA-like computing engines:
Compiled accelerators, reconfigurable computing, adaptive
computing devices, systems and software.
Rapid-prototyping:
Fast prototyping for system-level design and logic emulation.
Applications:
Innovative use of FPGAs, exploitation of FPGA features and
architectures, uses of FPGAs to achieve high-performance,
low-power, or high-reliability, FPGA-optimized DSP techniques,
novel uses of reconfiguration, FPGA-based cores.
Authors are invited to submit English language PDF of their
paper (10 pages maximum) and panel proposals by:
September 23, 2005.
Notification of acceptance will be sent by:
November 21, 2004.
The authors of accepted papers will be required to submit the
final camera-ready copy by
December 19, 2004.
A proceedings of the accepted papers will be published by ACM,
and included in the Annual ACM/SIGDA CD-ROM Compendium
publication.
Address questions to:
Andre' DeHon, Program Chair FPGA 2006
Dept. of CS, 256-80, CALTECH
Pasadena, CA 91125
Phone : (626) 395-6569
Email : andre@cs.caltech.edu
Organizing Committee
General Chair: Steve Wilton, University of British Columbia
Program Chair: Andre' DeHon, California Institute of Technology
Finance Chair: Herman Schmit, Tabula
Publicity Chair: Guy Lemieux, University of British Columbia
http://www.isfpga.org
Article: 87118Antti, why this is not clearly stated in the datasheet ? To me, it seems a big plus of that little board! Has stack support been implemented on ucLinux ? "Antti Lukats" <antti@openchip.org> ha scritto nel messaggio news:db7i87$92a$01$1@news.t-online.com... > > <bjskill@rocketmail.com> schrieb im Newsbeitrag > news:1121398768.643168.106640@o13g2000cwo.googlegroups.com... >> Hi, >> >> We will soon be using the Nios II as embedded controller and we would >> like to add a High Speed (HS) USB 2.0 hosting feature that is capable >> or providing a sustained transfer rate of 20 MBytes/sec. to an external >> HS USB 2.0 device. >> >> I realize that there are a limited number of HS USB 2.0 hosts >> devices/IP cores currently available. The Phillips ISP1761 is the only >> HS USB 2.0 component I was able to locate so far and it's not clear to >> me if this part is readily available. Also, the FPGA-based HS USB 2.0 >> host IP cores look like they are just now becoming available >> (www.asics.ws) but they may be cost-prohibitive. >> >> Can anyone share their experiences in implementing either a HS USB 2.0 >> or Full Speed (FS) USB 1.1 host? Is a sustained transfer speed of 20 >> MBytes/sec. achievable with the assumptions that there are no major >> transfer bottlenecks in the HS USB 2.0 host component or the associated >> HS USB 2.0 device (e.g. USB Hard Disk). If not, what is a more >> reasonable transfer speed goal that has a high probability of success? >> >> The choice of which OS with Nios II (or no OS at all) may also be >> influenced by the max. sustained HS USB 2.0 transfer speed that can be >> achieved. However, it's also possible that in order to meet the 20 >> MBytes/sec. goal, the Nios II will have to be "removed" from the data >> I/O path so that custom FPGA circuitry can handle the transfers >> directly with the external HS USB 2.0 host transceiver or the IP core. >> >> Any information and/or opinions would be helpful. >> >> Sincerely, >> Brad. >> > > ISP1761 is readily available, the proove is there > http://www.hydraxc.com > > ISP1761 (in BGA) is on lower side of the PCB. non BGA version has been > available for some time already, the BGA version (0.5mm pitch!) did become > available April/June 2005. > > and yes, you are about correct for max sustained dataflow the high speed > traffic should bypass the processor, that could be done by dedicated DMA > and > ISP1761 > > Antti > > > > > > > > > > > > > >Article: 87119
"Antonio Pasini" <NOSPAM_pasini.a@tin.it> schrieb im Newsbeitrag news:MNSBe.73716$h5.3030923@news3.tin.it... > Antti, > > why this is not clearly stated in the datasheet ? To me, it seems a big plus > of that little board! > > Has stack support been implemented on ucLinux ? > there is some linux code available for the isp1671 but it has to be adapted and thats not completed. But the goal is to support the isp1671 from uClinux of course Antti > "Antti Lukats" <antti@openchip.org> ha scritto nel messaggio > news:db7i87$92a$01$1@news.t-online.com... > > > > <bjskill@rocketmail.com> schrieb im Newsbeitrag > > news:1121398768.643168.106640@o13g2000cwo.googlegroups.com... > >> Hi, > >> > >> We will soon be using the Nios II as embedded controller and we would > >> like to add a High Speed (HS) USB 2.0 hosting feature that is capable > >> or providing a sustained transfer rate of 20 MBytes/sec. to an external > >> HS USB 2.0 device. > >> > >> I realize that there are a limited number of HS USB 2.0 hosts > >> devices/IP cores currently available. The Phillips ISP1761 is the only > >> HS USB 2.0 component I was able to locate so far and it's not clear to > >> me if this part is readily available. Also, the FPGA-based HS USB 2.0 > >> host IP cores look like they are just now becoming available > >> (www.asics.ws) but they may be cost-prohibitive. > >> > >> Can anyone share their experiences in implementing either a HS USB 2.0 > >> or Full Speed (FS) USB 1.1 host? Is a sustained transfer speed of 20 > >> MBytes/sec. achievable with the assumptions that there are no major > >> transfer bottlenecks in the HS USB 2.0 host component or the associated > >> HS USB 2.0 device (e.g. USB Hard Disk). If not, what is a more > >> reasonable transfer speed goal that has a high probability of success? > >> > >> The choice of which OS with Nios II (or no OS at all) may also be > >> influenced by the max. sustained HS USB 2.0 transfer speed that can be > >> achieved. However, it's also possible that in order to meet the 20 > >> MBytes/sec. goal, the Nios II will have to be "removed" from the data > >> I/O path so that custom FPGA circuitry can handle the transfers > >> directly with the external HS USB 2.0 host transceiver or the IP core. > >> > >> Any information and/or opinions would be helpful. > >> > >> Sincerely, > >> Brad. > >> > > > > ISP1761 is readily available, the proove is there > > http://www.hydraxc.com > > > > ISP1761 (in BGA) is on lower side of the PCB. non BGA version has been > > available for some time already, the BGA version (0.5mm pitch!) did become > > available April/June 2005. > > > > and yes, you are about correct for max sustained dataflow the high speed > > traffic should bypass the processor, that could be done by dedicated DMA > > and > > ISP1761 > > > > AnttiArticle: 87120
if you have installed ISE you can get there from the Project Navigator Help menu under "online documentation". It's also on the web at: http://toolbox.xilinx.com/docsan/xilinx7/books/docs/lib/lib.pdf This link is for the 6.3 version, but the libraries haven't changed much unless you're using Virtex 4 (which doesn't have BUFT anyway). praetorian wrote: > Gabor wrote: > > > > praetorian wrote: > > > >>To my understanding, bus macros are tri-state buffers at relative fixed > >>positions according to XAPP290. I'd like to implement my own bus macros > >>to be used for a small detacheable module (run-time reconfiguration), > >>but I cannot find a way to instantiate the tristate primitives in CLBs > >>in my VHDL. I could only get tristates by specifying this: > >> > >>output <= input when t = '1' else 'Z'; > >> > >>is there anyway to specifically instantiate a tristate primitive, > >>preferably with location constraint? > > > > > > You can instantiate BUFT. See the libraries guide in the online > > documentation. By the way, a BUFT actually implements: > > > > output <= input when t = '0' else 'Z'; > > > I was looking through the Virtex 2/Virtex 2Pro User Guide (ug012.pdf). > The guide does not have anything regarding the BUFT inside a CLB. Could > you give me a link to the libraries guide you are talking about? > > Thank youArticle: 87121
Hi, I've made a lot of research recently on the best way to integrate a wi-fi connection to my FPGA system. I've identified a few possibilities: 1) Wi-Fi single-chip solution (e.g.: www.csr.com; www.broadcom.com) 2) Wi-Fi embedded module (e.g.: www.sychip.com) 3) Wi-Fi SDIO or CF card (e.g.: www.sychip.com; www.sandisk.com www.socket.com) Manufacturers for two first options have been reluctant to share datasheets as well as information on how to acquire chips/evaluation boards. Therefore the third option is my best bet so far since I can buy a Wi-Fi card anywhere. However, I still need to figure out how the device works! Again, manufacturers don't release that kind of information. Anyone had success adding Wi-Fi connectivity to your FPGA design? Your inputs please. Regards, GabrielArticle: 87122
"Unbeliever" <alfkatz@remove.the.bleedin.obvious.ieee.org> schrieb im Newsbeitrag news:42d7bee4$0$13477$afc38c87@news.optusnet.com.au... > > "Antti Lukats" <antti@openchip.org> wrote in message > news:db86sg$ued$00$1@news.t-online.com... > > Hi, > > > > There have been different claims of being faster and bigger from different > > sides. The best thing to know it for real is to perform actual testing of > > the silicon (and not to believe the marketing stuff), I can present some > > results of actual measurements: > > > > DUT: Spartan 3S1500-4C-fg676 ES, measured normal ambient temperature > > > > LUT propagation delay as measured (measured was a t_LUT+t_switchbox): 595 > ps > > > > Xilinx datasheet says 610 max propagation delay what matches very well > with > > the actual measurement, I would estiamate switcbox delay of 30-60ps so the > > resulting LUT delay is about 10% than the max in datasheet. > > > > Measured clock frequency where the logic in the FPGA fabric was > operational: > > 420MHz > > AND theres a -5 > > Cheers, > Alf > > Hi Alf, well the -5 would cut the LUT delay by some 12% maybe. there is one important correction to my original report, I assumed the DCM can go eveb higher than 420MHz, thats totally wrong!!! Datasheet says max FX out is 280MHz, actual measured max useable DCM output (in DFS mdoe) is 250MHz, at 275MHz the DCM output was some random trash, 275MHz appears in output also once in a blue moon, but there is no stable output clock, testing was done with 75MHz input clock and 11/3 multiplier/divisor. this is a little weird as to my question about the DCM with V4 Xilinx answer was that the DCM actually works way beyound the settings that are possible in the coregen (same as in datasheet), I assumed the same statement to apply for S3 as well, but that isnt the case. Even the datasheet max is not working, well I am measuring early ES silicon, the DCM characteristics may be better for production silicon. AnttiArticle: 87123
And a Red Hat Enterprise server basic edition is 100% compatible with ISE webpack? "Marco" <marcotoschi@_no_spam_email.it> wrote in message news:db8gv6$9jn$1@news.ngi.it... > Hallo, > I would use webpack on linux. > > I would know if ISE Webpack 7.1 for Red Hat enterprise functions on > Fedora. > > If I download Fedora 64 bit version, Webpack ISE 32 bit function in any > case? > > May I upgrade in future webpack to foundation without installing it and > inserting the key registered with Xilinx site? > > Which Simulator should I use? ModelSim XE? > > Many Thanks > Maco Toschi >Article: 87124
Antti, Thanks for the great feedback. The HydraXC looks like a powerful module that could be incorporated into several types of embedded sytems. Too bad it doesn't incorporate a NIOS II soft-core processor on a Stratix I/II ;-) Other than the indication that the HydraXC has a USB OTG mini-A/B connector, there is nothing else on the datasheet to indicate that this board contains the ISP1761, or any other component(s), that supports HS USB 2.0 hosting. How can you know from the information on the website/datasheet that a USB 2.0 hosting capability if provided? Based on the assumption that a HS USB 2.0 OTG capability is provided, do you know of any HS USB 2.0 transfer speed benchmarks available for the HydraXC using the dedicated DMA channel? I didn't see any benchmark information on their datasheet. I know uClinux for Nios II currently only supports the Full Speed ISP1161A1 and not the ISP1761 components from Philips Do you know which of the listed operating systems that run on the HydraXC support the ISP1761? Since the ISP1761 looks like it is readily available, I start looking into obtaining an evaluation board/kit. Have you done any work with the ISP1761 yourself? The mounting of a 0.5 mm pitch BGA component is non-trivial. We have successfully mounted BGA components with a 0.8 mm pitch so making the jump to a0.5 mm pitch component should be achievable. Brad.
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