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I'm trying to find out what could cause a pin in a Virtex 300 part to short out. It's happened more than once, within a week's time frame. I can't really find any material on Xilinx's support web site about this situation (and what to look for). Work-around for the first one was to lift the pin off of the board and re-route the signal to another pin (used one adjacent to the bad one). May end up doing the same thing for the second pin now. Any suggestions welcomed... -bobArticle: 87051
Be more specific: short to gnd or Vcc ? What is the remaining impedance? If it is really low ( <1Ohm, ) then something has melted together. If it is >5 Ohm, then it might be the drive transistor permanently turned on. You might also test it for impedance when Vcc = 0 This is not an explanation or a cure, but a way to categorize and thus clasify the problem. Peter AlfkeArticle: 87052
Bob Myers wrote: > I'm trying to find out what could cause a pin in a Virtex 300 > part to short out. It's happened more than once, within a > week's time frame. I can't really find any material on Xilinx's > support web site about this situation (and what to look for). > > Work-around for the first one was to lift the pin off of the > board and re-route the signal to another pin (used one adjacent > to the bad one). May end up doing the same thing for the second > pin now. > > Any suggestions welcomed... > > -bob Bob, In addition to Peter's questions, make sure your pins are assigned per your intentions. Check the pin report after you run PAR. Pins that aren't assigned (constrained) could end up anywhere, so, for example, an output could get assigned to a pin you'd expect to be an input. MarcArticle: 87053
Andy Peters wrote: > tns1 wrote: > >>GMM50 wrote: >> >> >>>The approach I've taken is to add pins to get the desired signals to >>>appear as module ports. This works great if I'm simulating sub sets of >>>the final design. And in the total design these pins will eventually >>>get optomized away. >>> >>>If you get to the top level and need to see pins then you need to get >>>then to output pins on the device. If you're out of pins I put them >>>into a mux and this will keep the signals available for viewing. >>> >>>This all works great for functional simulatins. >>> >>>Good Luck. >>>george >>> >> >>OK, but what about when the signal looks OK in the sim, but it does not >>appear on the chip? > > > Maybe it got optimized away for a reason? > > -a Maybe so, but why does the sim say otherwise? I thought the whole point of doing a timing simulation was to know exactly how it would behave. Of course my test vectors might not reflect real life.Article: 87054
I have some source codes that should be able to read a mouse through the PS/2 port on the Xilinx fpga board; it sends $F4 to the mouse and then wait for data from the mouse. However, I probed the ps/2 port of the mouse and found that the mouse is not sending signals (clk & data), both signals constantly stay at around 4V (Vcc = 5V). (I attach the mouse to the PC & probe the same port, and there are signals responding.) What would be the possiblities of such failure?Article: 87055
Hi Ben, Can you give me the pointer for that link. Regards, Praveen Ben Twijnstra wrote: > Hi praveen, > > > Hi all, > > > > I want to implement a clock extraction circuit from data at 300 Mbps. > > What i wanted to know is that is it really feasible in FPGA's( CYCLONE > > II). > > > > Is any reference design available on clock extraction circiuit. > > Altera has two reference designs for Cyclone I that do clock/data recovery > at 270MHz for DVB/ASI and SDI. It may be possible to crank this up to > 300MHz when using the fastest speed grade Cyclone but it's going to be > tricky. > > Best regards, > > > BenArticle: 87056
<linq936@hotmail.com> schrieb im Newsbeitrag news:1121287062.568826.315390@g49g2000cwa.googlegroups.com... > Hi, > I know virtex-4 has 32 global clock lines and there is a requirement > that from any clock region, I can use up to 8 glock lines. > > Is there any visualized way so that I can see what is the coverage of > each clock region for a particular chip? Or some table kind of listing > each clock region covering which IO pins? > > Thanks. > I was referring to pagr 49 in DS312.pdf s3e complete datasheet, i assume similar figure should be in v4 ds as well anttiArticle: 87057
Shai wrote: > I am having problems programming the FPGAs I have on board. Well I have > two FPGAs on board a XC3s400 (Spartan 3) and xc2s200e (Spartan 2e) on > board. I have no problems creating the .mcs form the 2 bit files and > then using the impact to program......Its just that the FPGAs are not > getting programmed.The Done pin remains low.... > > What could be the reason behind this... > > Prompt reply appreciated.... The programming pins as well as the usual IOpins do have rather thight powerup specifications. For the families, I'm working with, TMS and TDI require a pullup, TCLK requires a pulldown. One open input (before configuration) can dramatically increase power consumption beyond the abailty of your powersupply if it was designed a bit thight. Have a long look at the datasheet. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 87058
Hi, I've tried inferring RAMs, but it doesn't seem to work well, so I want to just instantiate the Actel RAM primitives. Does anyone have a 4kx9 or 512x18 RAM model that uses instantiated ProAsic RAM primitives? Thanks, Scott scd -at- teleport -dot- comArticle: 87059
Why don't you use ACTGEN? If you have access to Precision then the example
below will infer a synchronous memory block,
-------------------------------------------------------------------------------
-- Actel Synchronous Memory
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all; -- yes I know, shouldn't use it :-)
entity ssram is
port(
clk : in std_logic;
din128 : in std_logic_vector (127 downto 0);
addr : in std_logic_vector (3 downto 0);
we : in std_logic;
dout128 : out std_logic_vector (127 downto 0)
);
end ssram ;
architecture rtl of ssram is
type mem_type is array (15 downto 0) of std_logic_vector(127 downto 0) ;
signal mem : mem_type;
begin
singleport : process (clk)
begin
if (clk'event and clk = '1') then
if (we = '1') then
mem(conv_integer(addr)) <= din128;
else
dout128 <= mem(conv_integer(addr));
end if ;
end if;
end process singleport;
end architecture rtl;
Hans.
www.ht-lab.com
"scd" <scd@nospam.com> wrote in message
news:ugoBe.7896$8f7.6493@newsread1.news.pas.earthlink.net...
> Hi,
>
> I've tried inferring RAMs, but it doesn't seem to work well, so I want
> to just instantiate the Actel RAM primitives.
>
> Does anyone have a 4kx9 or 512x18 RAM model that uses
> instantiated ProAsic RAM primitives?
>
> Thanks,
> Scott scd -at- teleport -dot- com
>
>
>
Article: 87060
Hi Guys,
I have run into a problem that I was not expecting, I need to calculate the
remainder after division (modulo) of a number preferebly in combinational
logic or a single clock cycle, and I need it to behave in the same fashion
as matlab does (as you would expect).
So i essentially need to calculate:
x = mod(y, 6434);
I did this in verilog as follows
reg signed [15:0] y;
wire signed [14:0] x;
assign x = y % 6434;
However this does not do what I am after. I assumed that % would perform a
modulo operation however, when my input is y = -6310, x = -6310.
This seems to be doing some kind of singed mod.. I would be expecting 124 as
the answer as matlab produced.
Can you give me any clues as to where I am going wrong??
Regards,
Paul Solomon
Article: 87061Hi, Since the Actel RAM modules cannot be preloaded a program time, I need a module that will read data from an I2C serial EPROM and load up the block RAM. Actel has an ap note on doing this, but they did not include any VHDL code. I hate to re-invent the wheel.. does someone have a RAM pre-loader module to share? Thanks in Advance, Scott scd -at- teleport -dot- comArticle: 87062
On Thu, 14 Jul 2005 17:57:35 +1000, "Paul Solomon" <psolomon@tpg.com.au> wrote: >Hi Guys, > >I have run into a problem that I was not expecting, I need to calculate the >remainder after division (modulo) of a number preferebly in combinational >logic or a single clock cycle, and I need it to behave in the same fashion >as matlab does (as you would expect). > >So i essentially need to calculate: > x = mod(y, 6434); > >I did this in verilog as follows > >reg signed [15:0] y; >wire signed [14:0] x; > >assign x = y % 6434; > >However this does not do what I am after. I assumed that % would perform a >modulo operation however, when my input is y = -6310, x = -6310. >This seems to be doing some kind of singed mod.. I would be expecting 124 as >the answer as matlab produced. > >Can you give me any clues as to where I am going wrong?? You're not doing anything wrong. It's just that Verilog's definition of signed modulus doesn't agree with that of Matlab's. In Verilog remainder is that same sign as that of the dividend which is what some call the truncating division. Matlab apparently uses a different (albeit completely legitimate) definition. If you want the same result, you can just check the sign of the result and add 6434 if negative. HTH.Article: 87063
"mk" <kal*@dspia.*comdelete> wrote in message news:219cd1h93s89hkc5g5ovjqc0jjh036n6sk@4ax.com... > On Thu, 14 Jul 2005 17:57:35 +1000, "Paul Solomon" > <psolomon@tpg.com.au> wrote: > >>Hi Guys, >> >>I have run into a problem that I was not expecting, I need to calculate >>the >>remainder after division (modulo) of a number preferebly in combinational >>logic or a single clock cycle, and I need it to behave in the same fashion >>as matlab does (as you would expect). >> >>So i essentially need to calculate: >> x = mod(y, 6434); >> >>I did this in verilog as follows >> >>reg signed [15:0] y; >>wire signed [14:0] x; >> >>assign x = y % 6434; >> >>However this does not do what I am after. I assumed that % would perform a >>modulo operation however, when my input is y = -6310, x = -6310. >>This seems to be doing some kind of singed mod.. I would be expecting 124 >>as >>the answer as matlab produced. >> >>Can you give me any clues as to where I am going wrong?? > > You're not doing anything wrong. It's just that Verilog's definition > of signed modulus doesn't agree with that of Matlab's. In Verilog > remainder is that same sign as that of the dividend which is what some > call the truncating division. Matlab apparently uses a different > (albeit completely legitimate) definition. If you want the same > result, you can just check the sign of the result and add 6434 if > negative. > HTH. > Fantastic, Thanks for that, this has fixed my prob. Regards, Paul SolomonArticle: 87064
I try to use some opb_bram to store data as SDRAM, so i add three
opb_bram_if_ctrl core when i create the project, and then i set the all
programm's sections into LMB_BRAM,the linker script is :
/*******************************************************************/
/* */
/* This file is automatically generated by linker script generator.*/
/* */
/* Version: Xilinx EDK 6.3EDK_Gmm.10
*/
/* */
/* Copyright (c) 2004 Xilinx, Inc. All rights reserved. */
/* */
/* Description : MicroBlaze Linker Script */
/* */
/*******************************************************************/
_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x400;
_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x400;
/* Define Memories in the system */
MEMORY
{
opb_bram_if_cntlr_3 : ORIGIN = 0x88000000, LENGTH = 0x0000FFFF
opb_bram_if_cntlr_2 : ORIGIN = 0x88010000, LENGTH = 0x0000FFFF
opb_bram_if_cntlr_1 : ORIGIN = 0x88020000, LENGTH = 0x0000FFFF
SDRAM_8Mx32_2 : ORIGIN = 0x8A000000, LENGTH = 0x01FFFFFF
SDRAM_8Mx32_1 : ORIGIN = 0x8C000000, LENGTH = 0x01FFFFFF
ilmb_cntlr_dlmb_cntlr : ORIGIN = 0x00000000, LENGTH = 0x0000FFFF
}
/* Specify the default entry point to the program */
ENTRY(_start)
/* Define the sections, and where they are mapped in memory */
SECTIONS
{
.text : {
__text_start = .;
*(.text)
*(.text.*)
*(.gnu.linkonce.t*)
__text_end = .;
} > ilmb_cntlr_dlmb_cntlr
.rodata : {
__rodata_start = .;
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r*)
__rodata_end = .;
} > ilmb_cntlr_dlmb_cntlr
.sdata2 : {
. = ALIGN(8);
__sdata2_start = .;
*(.sdata2)
. = ALIGN(8);
__sdata2_end = .;
} > ilmb_cntlr_dlmb_cntlr
.sbss2 : {
__sbss2_start = .;
*(.sbss2)
__sbss2_end = .;
} > ilmb_cntlr_dlmb_cntlr
.data : {
. = ALIGN(4);
__data_start = .;
*(.data)
*(.data.*)
*(.gnu.linkonce.d*)
__data_end = .;
} >ilmb_cntlr_dlmb_cntlr
.sdata : {
. = ALIGN(8);
__sdata_start = .;
*(.sdata)
__sdata_end = .;
} > ilmb_cntlr_dlmb_cntlr
.sbss : {
. = ALIGN(4);
__sbss_start = .;
*(.sbss)
. = ALIGN(8);
__sbss_end = .;
} > ilmb_cntlr_dlmb_cntlr
.bss : {
. = ALIGN(4);
__bss_start = .;
*(.bss)
*(COMMON)
. = ALIGN(4);
__bss_end = .;
} > ilmb_cntlr_dlmb_cntlr
PROVIDE (_SDA_BASE_ = __sdata_start + (__sbss_end - __sdata_start / 2
));
PROVIDE (_SDA2_BASE_ = __sdata2_start + (__sbss2_end - __sdata2_start /
2 ));
/* Generate Stack and Heap definitions */
bss_stack : {
. = ALIGN(8);
_heap = .;
_heap_start = _heap;
. += _HEAP_SIZE;
. += _STACK_SIZE;
. = ALIGN(8);
_stack = .;
__stack = _stack;
} > ilmb_cntlr_dlmb_cntlr
}
But my programm has not any response after i downloaded it into FPGA.
Can you tell me the reason?
How can i change it?
Any advice is appreciated!!!!!!
Article: 87065"scd" <scd@nospam.com> schrieb im Newsbeitrag news:RhpBe.4854$BK1.4156@newsread3.news.pas.earthlink.net... > Hi, > > Since the Actel RAM modules cannot be preloaded a program time, > I need a module that will read data from an I2C serial EPROM and > load up the block RAM. > > Actel has an ap note on doing this, but they did not include any > VHDL code. I hate to re-invent the wheel.. does someone have > a RAM pre-loader module to share? > > Thanks in Advance, > Scott scd -at- teleport -dot- com > > > dont be lazy and just download the vhdl source code from Actel website, its there! AnttiArticle: 87066
<mlpei279@gmail.com> schrieb im Newsbeitrag news:1121330904.928551.215820@g44g2000cwa.googlegroups.com... > I try to use some opb_bram to store data as SDRAM, so i add three > opb_bram_if_ctrl core when i create the project, and then i set the all > programm's sections into LMB_BRAM,the linker script is : [snip] > But my programm has not any response after i downloaded it into FPGA. > Can you tell me the reason? > How can i change it? > Any advice is appreciated!!!!!! > you are using a device with 256 KBYTE of available BRAMs `!? thats pretty huge FPGA, and doesnt cost peanuts! your linker script is not ok! just get the manuals for GNU linker and read them, and again and again. then fix the linker script its boring stuff, but there is no way around it, if you are modifying the linker scripts you need to know what you are doing, not just typing something into it hoping it will all work. it want. and verify that your design matches the fpga configuration, do really have all that 256 KBYTE of BRAMs there? its possible of course in real big V2 or V4, but usually its better idea to use the external memories and small bootloader in BRAM anttiArticle: 87067
HI Jeff, Your design has no outputs, so no circiut is needed.so the tool has not implemented your design.If u bring out 'i'(std_logic) it will be synthesized. Regards, Raghavendra jeff murphy wrote: > i'm just starting out with fpgas and i'm having what's probably a basic > newbie problem. i have the following simple entity: > > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.STD_LOGIC_ARITH.ALL; > use IEEE.STD_LOGIC_UNSIGNED.ALL; > > entity test1 is > Port ( clk : in std_logic); > end test1; > > architecture Behavioral of test1 is > begin process (clk) is > variable i : integer := 0; > begin > if clk = '1' and clk'event then > i := i + 1; > end if; > end process; > end Behavioral; > > and i have ISE webpack set to xc2vp2-6ff672 and in the ucf file i have: > > NET "clk" LOC = "g14" ; > > which i believe is the correct clock pin. when i synthesize that code, > i get the following warning: > > Synthesizing Unit <test1>. Related source file is > "C:/temp/test1/test1.vhd". WARNING:Xst:647 - Input <clk> is never used. > Unit <test1> synthesized. > > what am i doing wrong? > > thanks!Article: 87068
Will that have any effect on a pre placed macro? Andy Peters wrote: > Ian wrote: > > Hi Everyone, > > > > I would be really for any help or advice you can offer me on the > > following. > > > > I have created a simple tri-state bus as a macro using xdl. The design > > consists of two TBUFs driving a single long line. > > > > (Diagram at http://www.comms.scitech.susx.ac.uk/~ian/files/tbuf.gif) > > > > <img src="http://www.comms.scitech.susx.ac.uk/~ian/files/tbuf.gif"> > > > > I attach external macro pins to Out, Enable and In of each TBUF. > > However, when I try to include the macro in a design, the DRC in the > > map phase complains that the Out pin is being driven by two sources. > > MAP Error Message: > > > > > > ERROR:MapLib:22 - Bus M0_DATA_LEFT_O_OBUF driven by bm_instance and > > bm_instance has multiple active drivers. > > > > > > This is not correct, as the O pins are external macro outputs! Is there > > anyway to prevent this? > > There's a fitter option somewhere that tells the tools to converter > internal tristates to muxes. Find that option and tell it not to do > so. > > -aArticle: 87069
I create a module then synthesize it.Everything goes well. But when I call it in upper block,my synthesis tool tell me there is some logic cannot be synthesized. I do all my work in ISE6.3i. Why does this happen? And how should I deal with it thxArticle: 87070
Can you tell us what modules are you talking about ? What is the entity and port declaration of the sub module ? How is the port map in the top level module ? RgdsArticle: 87071
No output defined so everything is "optimized" away. Please use ieee.numeric_std.all; instead of ieee.std_logic_arith.all; ieee.std_logic_unsigned.all; Rgds Andr=E9Article: 87072
>> I need a module that will read data from an I2C serial EPROM and >> load up the block RAM. >> >> Actel has an app. note on doing this, but they did not include any >> VHDL code. I hate to re-invent the wheel.. does someone have >> a RAM pre-loader module to share? I'm a big I2C fan but in this case I'd go for SPI. The SPI is simpler and faster. Some people have made very large serial memories and I note that they have chosen SPI. When transferring a lot of bytes, a few microseconds on each soon adds up...Article: 87073
Seems like there is problem initializing the mouse. The host pulls the clk down to start initializing; however, the mouse clock doesn't start after the host releases the clk.Article: 87074
Hello all, Is there any way i can initialise values into the Xilinx FPGA FF. I am working on the Virtex E FPGA. Please tell me how can i achive that through verilog. Thank you
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z