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skatoulas@hotmail.com wrote:
> use WORK.ALL.;
>
> well that dot should obviously not be there... Any ideas?
Other than left-click, backspace, save?
I might consider a different text editor.
-- Mike Treseler
Article: 87601Steve Underwood <steveu@dis.org> writes: > [...] > My experience with completely up front designs is they always produce > something obsolete by its shipping date. I think anything more > adaptive than that has to be of huge benefit, whatever drawbacks it > has. I'll see you and Peter in the marketplace. -- % Randy Yates % "Ticket to the moon, flight leaves here today %% Fuquay-Varina, NC % from Satellite 2" %%% 919-577-9882 % 'Ticket To The Moon' %%%% <yates@ieee.org> % *Time*, Electric Light Orchestra http://home.earthlink.net/~yatescrArticle: 87602
Randy Yates <yates@ieee.org> wrote in news:3bq1jcy4.fsf@ieee.org: > Steve Underwood <steveu@dis.org> writes: >> [...] >> My experience with completely up front designs is they always produce >> something obsolete by its shipping date. I think anything more >> adaptive than that has to be of huge benefit, whatever drawbacks it >> has. > This is my view as well. > I'll see you and Peter in the marketplace. I love that last line. -- Al Clark Danville Signal Processing, Inc. -------------------------------------------------------------------- Purveyors of Fine DSP Hardware and other Cool Stuff Available at http://www.danvillesignal.comArticle: 87603
"Al Clark" <dsp@danvillesignal.com> wrote in message news:Xns969FCA9BA4900aclarkdanvillesignal@66.133.129.71... > Randy Yates <yates@ieee.org> wrote in news:3bq1jcy4.fsf@ieee.org: > >> Steve Underwood <steveu@dis.org> writes: >>> [...] >>> My experience with completely up front designs is they always produce >>> something obsolete by its shipping date. I think anything more >>> adaptive than that has to be of huge benefit, whatever drawbacks it >>> has. >> > > This is my view as well. > > >> I'll see you and Peter in the marketplace. > > > I love that last line. > Me too Al. An awful lot has to do with product cycle time. I worked at a place where the cycle time was quite short. There was lots of re-use of "infrastructure parts". So, the idea of making many changes after the initial design was pretty remote. There wasn't time if we were going to get to market. The products weren't obsolete with a cycle time that could be under 1 year. We also relied on field programmable FPGA designs. So, changes weren't out of the question but were "soft" in that sense and didn't necessarily count in the "few changes" sense of things. FredArticle: 87604
how often does an external clock fail? what king of the clock is it? how much useful to have an FPGA to backup? -FranklinArticle: 87605
Just curious, does Foundation ISE support XP/64? Is the program capable of addressing more than 2GB of RAM?Article: 87606
hpg wrote: > Just curious, does Foundation ISE support XP/64? Is the program > capable of addressing more than 2GB of RAM? > > Hi hpg, I've used it for synthesising rather large designs on XP. It is fine as long as you install some patch that fixes a windows issue with the 2GB limit. I've done it a while ago now, but can't remember what exactly this patch is. Regards, KeithArticle: 87607
Hi all,
Can any one list me out the various steps that need to be carried
out to convert ASIC RTL Code to FPGA RTL Code. In what way the ASIC RTL
Code differs from FPGA RTL Code. Can you also list me the various tools
that are available to perform them.
Thanks in Advance,
Sarath
Article: 87608hi I need to measure "number of clock cycles" or "execution time", after mapping the VHDL code into Vertex II pro. In Modelsim simulation, it took 350 cycles with 20 MHz clock frequency. I hope the performance after the mapping will be same as the performance in simulation. In ISE 6.3 (or EDK 6.3) , how can we measure the amount of clock cycles? Maybe I can use "big" counter along with my design. Are there any efficient way to do so? ThanxArticle: 87609
Look at the Xilinx Answer 20813. "Input Delay Element Not Programmed Correctly In some rare cases, the input delay elements for synchronous and asynchronous inputs on the bottom edge of the XC3S500E are programmed with the incorrect delay. This problem will be fixed in ISE 7.i Service Pack 4. For more information on this issue, see (Xilinx Answer 21721)." Best regards, Daniel George Mercury schrieb: > Hi guys, > Has anyone tried instantiating IOBUF in a Spartan-3E device? The IOBUF > primitive for S3E has two new attributes namely IBUF_DELAY_VALUE and > IFD_DELAY_VALUE: > > IOBUF_inst : IOBUF > generic map ( > DRIVE => 12, > IBUF_DELAY_VALUE => "0", > IFD_DELAY_VALUE => "AUTO", > IOSTANDARD => "DEFAULT", > SLEW => "SLOW") > port map ( > O => output, > IO => input_output, > I => input, > T => enable > ); > > These two new attributes don't seem to be recognised by PAR, since > translate generates these warnings: > > WARNING:NgdBuild:486 - Attribute "IBUF_DELAY_VALUE" is not allowed on > symbol > "IOBUF_inst" of type "IOBUF". This attribute will be ignored. > WARNING:NgdBuild:486 - Attribute "IFD_DELAY_VALUE" is not allowed on > symbol > "IOBUF_inst" of type "IOBUF". This attribute will be ignored. > > Thus, signals don't get routed. I am using ISE 7.1.03 which as far as I > am aware is the latest release. Any ideas what is wrong? > > Best regards > George >Article: 87610
Hi all, It seems the WEB Pack 7.1 SP3 needs to write into registry after every start in order to work properly. If registry access is prohibitet WEB Pack 7.1 don't create the testbench. The WEB Pack 6.3 don't do it and works properly if write to registry is forbidden. I use Windows 2000. Is it right? Does anyone know why is it changed? ThanksArticle: 87611
Hi, sarath schrieb: > Hi all, > Can any one list me out the various steps that need to be carried > out to convert ASIC RTL Code to FPGA RTL Code. In what way the ASIC RTL > Code differs from FPGA RTL Code. Can you also list me the various tools > that are available to perform them. Good ASIC rtl is good FPGA rtl, so you need only a tool allowing you to change the filenames *veg*. In general you need to replace any technologie-dependecies like IO-buffer, PLL, memory,.. to fit your new target technology. In some cases you might find it necessary to do some greater changes to reach the same performance, but there can be no general advice without knowing exactly all sides of the problem. bye ThomasArticle: 87612
"Franklin" <fsun998@gmail.com> schrieb im Newsbeitrag news:1122442983.166617.223200@f14g2000cwb.googlegroups.com... > how often does an external clock fail? what king of the clock is it? > how much useful to have an FPGA to backup? > > -Franklin > You are asking questions I dont have answers for, some possible uses I could have figured out for OCO use are: 1 External is not supposed to fail, but if as example the external clock was not soldered to PCB at all, then OCO could deliver backup clock for selfdiagnastic. 2 If external clock is coming from external programmable clock IC/PLL, then reprogramming it from FPGA may disable the output, and those making it impossible to recover (without backup clock) 3 for some initialization procedure it may be required to used clocked processes in FPGA before the external clock starts or DCMs lock 4 a Watchdog shoud generically not be clocked from main system clock 5 die temperature measurement, can be also done to measure temp in different places accross the die 6 fpga speed grade measurements, vcc and temp degration measurements I think there are many more uses. Besides - Lattice has FPGA onchip oscillator user accessible in all FPGA's, Altera has it available in MAX2, Xilinx had it available in XC4K, so I am just making it again available in new Xilinx FPGA's. Its not me who needs to figure out what todo it - I only provide the IP Cores and some characterization data. Its up to to ultimate user to find out it is useable and useful. Just one example - I think Ray Andraka is one person who keeps saying 'do not use F5 mux' - its slowing down the performance. But how many people know how much the F5MUX penalty really is? This can be measuered easily with our IP Cores and tools with very high precision, without any special equipment, only special Software and JTAG cable is required. You can calc it yourself - a OCO with '2 logic delays' runs 210MHz, an OCO with 2 logic delays + F5 delay runs at 170MHz. This data is for S3 speedgrade -4. I havent calculated the F5 delay myself, but from the % of change I would say it is pretty significant. And that Ray is VERY right (as always) about the F5mux to be an evil when it goes high speed design optimization. To my knowledge Xilinx tools to not count the F5 delay in 'LUT logic levels' so knowing the penalty and carefully checking the F5 use and redesigning/constraininig a design better may give the needed performance boost for some designs. Antti PS one very funny sample application is no components touch sensor - a plastic packaged FPGA can sense what side of the FPGA package you touch with your finger. So you can as example build an code-lock by using FPGA package as finger touch sensor. It is possible.Article: 87613
Peter K. wrote: > Steve Underwood wrote: > > > The key problem with anything that produces an early prototype is > > managers tend to mistake the prototype for something near to market > > ready, however emphatically they are told it isn't. Without the pressure > > that brings I doubt people like Randy would be criticising more adaptive > > methodologies. > > I agree that this is an issue. Well, I did see -- from a safe distance, thankfully -- a software project in progress, that did "produce results" extremely quickly. Somebody was making some sort of data processing tool. The department (perhaps even the people) involved in this particular project, had at a previous time been involved in developing a production analysis tool of similar nature. What had happened in the mean time, was that both matlab and IDL had provided GUI development tools as part of the programming system. So these guys were capable of producing a GUI where the data was visualized, manipulated and handled, along with some simple IO etc, in a matter of hours. Previously, they had used weeks or months for design, analysis etc, before starting coding, let alone have a demo ready to show. People were flabbergasted by the "results". The nice, fancy images on the screen. "This proves that those guys from the other department, who ran the previous project and insisted on all that bueracracy, had no idea whatsoever what they wre doing." Sure, the demo was impressive enough. But could it handle production- type data sets, that could be tens of gigabytes? I don't know. Could it be maintained in a decent way? I don't know. Could it be extended with further functions? I don't know. Could the GUI be changed easily, if the intended users had remarks on the operation? I don't know. Could it be modified to accomodate slightly different analysis tasks? I don't know. In this case, the demo was percieved as "a product", right here and then. No one who asked for time or resources to "get it right" would get anything; there was no need for it. The program was already there, running, "working". And the serious long-term effect (which I got to know first-hand) was that there was no need to allocate neither time nor other resources in future programming projects: These guys had produced "a product" in a matter of hours, using the site lisence of either matlab or IDL. Everybody else was expected to do the same. All my efforts to get the department to make decisions on data formats, analysis tools, establish procedures for QC, data validation, storage formats, reporting standards etc (I thought that getting/making a software tool for these kinds of jobs might force people to make decisions of this nature) were met with "It generates too much bueracracy, people do what they want anyway, and it takes no time to make a system for the scarcely few instances it might be useful." > It's a matter of "training" your > stakeholders, though, and I've had more success with incremental > involvement of stakeholders (in parallel with the incremental > implementation), than trying to get their whole-hearted attention for > the times when a big design needs it. Sure, that's the only way to train people. Still, I have yet to meet somebody who don't have hands-on experience with coding and implementations, who do understand the difference between "demo GUI" and "product", to paraphrase the example above. > The phrase "attention span of a gnat" springs to mind. I don't think it is the full explanation. Lack of hands-on experience with system analysis and programming, is more likely. RuneArticle: 87614
> > I've used it for synthesising rather large designs on XP. It is fine as > long as you install some patch that fixes a windows issue with the 2GB > limit. I've done it a while ago now, but can't remember what exactly > this patch is. I guess you're refering to the AR 14932: http://tinyurl.com/9xl4w HTH, JimArticle: 87615
After having mailed Altera which forwarded the mail to whoever... BTW it was rather hard to find an email adress at all to send such a question to. There is a pin error in the footprint of the EP2C8F256. The F5, LVDS13p is alone, there is no LVDS13n, which has to be for a true LVDS channel. Can anyone confirm this ? It basically means there is no LVDS13. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 87616
Antti Lukats wrote: > "Franklin" <fsun998@gmail.com> schrieb im Newsbeitrag > news:1122442983.166617.223200@f14g2000cwb.googlegroups.com... > >>how often does an external clock fail? what king of the clock is it? >>how much useful to have an FPGA to backup? >> >>-Franklin >> > > > You are asking questions I dont have answers for, some possible uses I could > have figured out for OCO use are: > > 1 External is not supposed to fail, but if as example the external clock was > not soldered to PCB at all, then OCO could deliver backup clock for > selfdiagnastic. > 2 If external clock is coming from external programmable clock IC/PLL, then > reprogramming it from FPGA may disable the output, and those making it > impossible to recover (without backup clock) > 3 for some initialization procedure it may be required to used clocked > processes in FPGA before the external clock starts or DCMs lock > 4 a Watchdog shoud generically not be clocked from main system clock > 5 die temperature measurement, can be also done to measure temp in different > places accross the die > 6 fpga speed grade measurements, vcc and temp degration measurements > > I think there are many more uses. <snip> External clock elimination is another clear usage area. There are many apps that do not care too greatly about the internal clock speed, so they can eliminate the external clock. Others might use a (eg) 32Khz low power external Timebase, and run the FPGA as fast as possible, before re-idle. Still others can AutoBAUD, or self calibrate to incomming data streams. The LIN bus specs such a preamble, designed for low performance oscillators. -jgArticle: 87617
Hello, We are using Altera QuartusII 4.2 software and we have a problem when we create symbols and use the symbols on top level.when we compile the design we are getting an error saying that it cannot find the design file,we have also observed the same error when we double click the symbol. Can anyone give me some suggestions or pointers to any documentation to be read? Thanks in advance, Monica, GermanyArticle: 87618
"Monica" <monica_dsz@yahoo.com> wrote in message news:1122463804.740522.207780@g49g2000cwa.googlegroups.com... > Hello, > > We are using Altera QuartusII 4.2 software and we have a problem when > we create symbols and use the symbols on top level.when we compile the > design we are getting an error saying that it cannot find the design > file,we have also observed the same error when we double click the > symbol. > > Can anyone give me some suggestions or pointers to any documentation to > be read? > > Thanks in advance, > Monica, > Germany > Hi Monica, I think that I know the answer to this one.. I believe that the symbols and design files either have to reside in the project directory or the directory containing them has to be in the list of included directories (or libraries I cant remember) that is set up in the project settings. If you are working between multiple projects and then use the mega-wizards and the like, they sometimes default to save the files in the wrong projects directories.. then you get this problem. I hope that helps. Regards, PaulArticle: 87619
> There is a pin error in the footprint of the EP2C8F256. > The F5, LVDS13p is alone, there is no LVDS13n, > which has to be for a true LVDS channel. > > Can anyone confirm this ? It basically means there > is no LVDS13. There is a LVDS13n on the Q208 package (which also has a LVDS13p).Article: 87620
Jon Harris wrote: > "Fred Marshall" <fmarshallx@remove_the_x.acm.org> wrote in message > news:roCdnQY0lNkxynjfRVn-uA@centurytel.net... > > > > "scottfrye" <scottf3095@aol.com> wrote in message > > news:1122308450.491025.165850@g14g2000cwa.googlegroups.com... > >> >... For some > >>>reason, managers and customers seem to think that software can be > >>>changed much more easily than mechanical systems... so they do. > >> > >> Do you think that software is as hard to change as mechanical systems? > >> > >> or is it possible that, even though software is easier to change than a > >> mechnical system, it still requires some work and many > >> managers/customers assume easier change = free change? > >> > > > > I depends. It's pretty easy to change the diameter of a hole in AutoCAD. So, > > if that's the context of a change to a mechanical system then it's just as > > easy as changing a line of code. In fact, it's equivalent to changing the > > value of a constant and that's how it's done. Now, if the next step is to > > reprogram an NC machine, then that's something additional. But isn't that > > similar to linking the new compiled code...? Maybe. > > At least in my company, after you change the diameter of the hold in AutoCAD, > you have to update required documentation, notify the vendor, possibly pay a > change fee, figure out how to deal with the existing units with the "wrong" > whole size (see through, throw away, return for correction), verify the fix has > been implemented, etc.. The software is more like change the code, test it, and > post it on the web site. It still takes work, but it's all in house, requires > less time and management, and usually less cost. But for a manufacturing > company that out-sourced its software, it could be the opposite! Making the change can be as easy as yawning, and still be a nightmare. We had just bought some new data acquisition system, and was preparing to take it to sea for the first time. The system both controlled the ADC and stored the data to files, and it was up to us to sort the files out, rename and archive them according to the project, survey, run, etc. The system was, as far as I know, one of the first of this make and model to be sold. I would expect the supplier to be interested in getting customer feedback, and make those small changes the users would like, to make it easier to operate. So the engineer in my department who was responsible for the kit, came up with the very sensible idea that the raw data files as generated by the acquisition system, should be named according to the time they were started. The files would get a name as a numerical value according to filename = YearMonthDayHourMin which would yield a unique file name for each file. All we had to do, then, was to make a script that compared the file name to the survey log we anyway would have to write elsewhere. Whoever wanted to use the data files after the survey, would have to relate to the survey log anyway. The supplier of the system had no objections to doing the change, but our engineer had not been very precise in writing the requirements. She had indicated the change much like I did above, but when we tested the code (at sea, on our way out to the first survey this piece of kit would be used...) we got a result like Year: 2006 Month: 7 Day: 7 Hour: 14 Min: 42 filename = 2006771442.data The problem? No leading zeros to identify single-digit months, days, hours or minutes, making the file name ambiguous with respect to when it was generated. For instance, was the file 2006112130.data generated at 2006 January 12th 0130 hours, 2006 January 1st 2130 hours, or 2006 November 2nd, 0130 hours? There is no way of telling, unless the time stamps in the file systems are preserved, which they are not guaranteed to be. The required spec ought to have been filename = yyyymmddhhMM As far as I am concerned, getting it right once the error was discovered ought not to take more than 2 minutes. For some reason, the second request did throw a serious spanner in the works, what the relationship to the supplier was concerned. I have no idea why, although it might be that a controversy over some adjustable gain settings had something to do with it. I frequently changed the gain settings of the ADC during the survey, to make up for the somewhat limited dynamics of the fixed-point ADC. For some reason, the gain settings were never stored in the data files, so I could not use the data files for my purposes when we got back to the lab. I don't know if the time-coded file names ever were generated correctly. RuneArticle: 87621
Hi Rene Tschaggelar, > After having mailed Altera which forwarded the mail to > whoever... BTW it was rather hard to find an email > adress at all to send such a question to. > > There is a pin error in the footprint of the EP2C8F256. > The F5, LVDS13p is alone, there is no LVDS13n, > which has to be for a true LVDS channel. > > Can anyone confirm this ? It basically means there > is no LVDS13. Well, Quartus says: Error: Can't place node positive with differential I/O zort2 in location (0,17,2) -- location does not support differential pin pair functionality Error: Can't place I/O pin zort2(n) in non-bonded location PAD_7 Error: Can't fit design in device So I guess something is indeed wrong. Rene, will you file the SR or shall I do it? Best regards, BenArticle: 87622
Randy Yates wrote: > > I'll see you and Peter in the marketplace. > Is that a threat or a promise? Or both? :-) Ciao, Peter K.Article: 87623
Rune Allnor wrote: > Well, I did see -- from a safe distance, thankfully -- a software > project in progress, that did "produce results" extremely quickly. [SNIP] > All my efforts to get the department to make decisions on data > formats, analysis tools, establish procedures for QC, data validation, > storage formats, reporting standards etc (I thought that getting/making > a software tool for these kinds of jobs might force people to make > decisions of this nature) were met with "It generates too much > bueracracy, people do what they want anyway, and it takes no time to > make a system for the scarcely few instances it might be useful." If it could be truly demonstrated that, for this particular company, that approach worked... why not? It certainly sounds like a pretty retrograde step they way you describe it, but if the company could survive by doing things that way (even if it goes against all the good ISO-9001:2000 / CMMI stuff), then it might be a valid way to go. I certainly have come across people who insist on taking an hour to do something... and every time they do it it takes them an hour. Whereas the I try to figure out how to automate it so that, the first time, it might take me an hour and a half... but the second time takes my 20 minutes, and subsequent times 5 minutes. The people who don't do the hard hour every time don't appear to understand the tools at their disposal, or can't systematize their thinking about the problem enough to use them effectively. > > It's a matter of "training" your > > stakeholders, though, and I've had more success with incremental > > involvement of stakeholders (in parallel with the incremental > > implementation), than trying to get their whole-hearted attention for > > the times when a big design needs it. > > Sure, that's the only way to train people. Still, I have yet to meet > somebody who don't have hands-on experience with coding and > implementations, who do understand the difference between "demo GUI" > and "product", to paraphrase the example above. Maybe. I've been fortunate enough to be able to convince my higher-ups to go along to some of the technology training courses so they understand (at a high level) what we're trying to do and how we're trying to do it. > > The phrase "attention span of a gnat" springs to mind. > > I don't think it is the full explanation. Lack of hands-on experience > with system analysis and programming, is more likely. And them not taking the time to get that experience is, IMHO, indicative of the attention span of a gnat. Ciao, Peter K.Article: 87624
Ben Twijnstra wrote: > Hi Rene Tschaggelar, > > >>After having mailed Altera which forwarded the mail to >>whoever... BTW it was rather hard to find an email >>adress at all to send such a question to. >> >>There is a pin error in the footprint of the EP2C8F256. >>The F5, LVDS13p is alone, there is no LVDS13n, >>which has to be for a true LVDS channel. >> >>Can anyone confirm this ? It basically means there >>is no LVDS13. > > > Well, Quartus says: > > Error: Can't place node positive with differential I/O zort2 in location > (0,17,2) -- location does not support differential pin pair functionality > Error: Can't place I/O pin zort2(n) in non-bonded location PAD_7 > Error: Can't fit design in device > > So I guess something is indeed wrong. > > Rene, will you file the SR or shall I do it? file what & where ? Ah, support request ? That is this personal login stuff ? A black hole, IMO. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.net
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