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I have a board with three Spartan3s on it. Right now, under sources in project, I have the project name, then xc3s400-4pq208, and under that top1-behavioral(top1.vhd), top2-behavioral(top2.vhd), top3-behavioral(top3.vhd) and stuf under those like the top1.ucf, etc. So what happens if one of the Xilinx parts gets upgraded or downgrade in speed or size? Can I assign the xc3s400 spec to each top level design? BradArticle: 87801
Telenochek wrote:
> I am trying to design with state machines.
Don't try to make your design look like
a text book state machine. Make your
design look like a VHDL synchronous process
with local variables (or signals).
Let synthesis worry about the details
after your simulation testbench is working.
> For example there is a master FSM (finite state machine), which
> calls slave state-machines along the way, waits for them to end (via
> slave-busy signals) etc...
> Unfortunately this approach becomes very messy very quickly.
I agree. Focus on describing your design in terms
of vhdl entity inputs and vhdl process variables.
> So, I decided to look at the professional code,
> such as PicoBlaze soft processor code, and some video application
> examples on Xilinx website
You are designing a simple controller, not a cpu.
> and although there are certainly state machines here and there,
> it seems that most of the code is kind of .......... architectural.
> In other words there are many components and control signals.
You can complete your design in a single entity.
> I understand the breakdown into components when somebody else writes
> it, and I understand the code, and how everything is connected.
> The problem arises when I need to come up with all the control signals
> myself, and make sure the dynamics of the system is working ok.
This is what your vhdl simulator is for.
> I think thats a digital design problem, rather than a coding problem.
> Coding is *relatively* easy when you have a clear design.
You need to run some simple testbench examples through
a vhdl simulator to learn how to *describe* a controller
in terms of a synchronous vhdl process.
> Thats why I was wondering how the more experienced folks come up with
> their designs.
while not done loop
sketch_in_notebook;
simulate;
edit;
end loop;
-- Mike Treseler
Article: 87802
Brad Smallridge wrote:
> Up to now, I have been doing much of my work with ModelSim and
> a BMP file reader and writer. Most of my VHDL designs have clk
> and reset. I know where to attach the clk but what do I use for
> reset. An external pin? The Done pin? Or a DCM lock signal?
I drive reset from a cpu running on
the fpga clock. Pulse it after the
binary image is loaded.
This is vendor independent
and synchronous.
-- Mike Treseler
Article: 87803Humm... Why wouldn't Xilinx support this cable (I thought Digilent and Xilinx have a close relationship) and if not Why wouldn't Xilinx publish the protocols used by Chipscope server. Are they trying to make money by selling their own expensive USB cable ? SumitArticle: 87804
Brad Smallridge wrote:
> Up to now, I have been doing much of my work with ModelSim and
> a BMP file reader and writer. Most of my VHDL designs have clk
> and reset. I know where to attach the clk but what do I use for
> reset. An external pin? The Done pin? Or a DCM lock signal?
>
Is this an asynchronous (power-on) reset you are talking about? In that
case, for Xilinx parts, instantiate a ROC component:
component roc
port (
O : out std_logic
);
end component;
begin
-- model of the Xilinx POR
roc_e: roc
port map(
O => RESET
);
The model for the ROC is in the Xilinx unisim library. The Xilinx tools
know to assign the RESET net to the internal POR structure. You don't
need to connect it to any pins.
Article: 87805praetorian wrote: > I'm trying to create a customized BRAM module (memory redundancy, > checkbits) However, the BRAM included in the EDK cannot be simply > modified (no hdl in the ip core directory). Does anyone know of anyways > to modify it? The opb_bram is for use with the block ram inside the FPGA. Are you really planning to add redundancy and checkbits to that? If so, I would wonder why. If the BRAM can be corrupted, then so can the rest of the FPGA, so are you also adding error detection and correction to the rest of the FPGA? My EDK does come with source for the opb_bram, assuming you are referring to EDK6.3/hw/XilinxProcessorIPLib/pcores/opb_bram_if_cntlr_v1_00_a/hdl/vhdl So I cannot imagine why you wouldn't have it.Article: 87806
I'm talking about the actual bram, ot the controller. Duane Clark wrote: > praetorian wrote: > >> I'm trying to create a customized BRAM module (memory redundancy, >> checkbits) However, the BRAM included in the EDK cannot be simply >> modified (no hdl in the ip core directory). Does anyone know of >> anyways to modify it? > > > The opb_bram is for use with the block ram inside the FPGA. Are you > really planning to add redundancy and checkbits to that? If so, I would > wonder why. If the BRAM can be corrupted, then so can the rest of the > FPGA, so are you also adding error detection and correction to the rest > of the FPGA? > > My EDK does come with source for the opb_bram, assuming you are > referring to > EDK6.3/hw/XilinxProcessorIPLib/pcores/opb_bram_if_cntlr_v1_00_a/hdl/vhdl > So I cannot imagine why you wouldn't have it.Article: 87807
Telenochek wrote: > Hello everyone! > I am having a problem in ModelSim XE 5.8c with a very simple > bidirectional bus. > ModelSim outputs a bunch of XXXX's where its supposed to output data. > I am using test bench waveforms with Xilinx ISE 6.303i. > > Basically there are only 3 signals: the bidir. bus, wr_enable and clk. > The idea behind this simple code is: > if WR_EN is HIGH -> store bus data into a flip-flop on next clock edge. > > else WR_EN is LOW -> output a constant value on the bus (in practice, I > want to output something more useful, of course.) > > Unfortunately, ModelSim outputs X's (don't cares) for every bit where > the data in flip-flop conflicts with the constant. > Let's say that 11110000 was stored in the flip-flop when WR_EN was > high. > And suppose that the constant to put on the bus is 00110000, when WR_EN > goes low. > When WR_EN actually does go low, ModelSim will output XX110000 instead > of 00110000. > > I think the problem might be with the way I designed the bus with VHDL. > But I can't figure out where the problem is, and the code is VERY > simple. You are going to have several problems with the code. The fundamental problem is that the data is registered, but the wr_en is not. So what will happen is you set wr_en and the data, but the FPGA does not tristate the bus until one clock later. So you write junk on the first clock, and then valid data one clock later. Watch "a" during a wrote to see this happen. The second problem is that when you pull wr_en low, you are apparently forgetting to tristate bus from the testbench you are using. So the testbench is driving the bus at the same time as the FPGA, resulting in X's on the bits that do not match.Article: 87808
hi,
i m doing project on image processing.For that i need to store pixel
value of any frame in memory. I read from one journal that there is
one circular read address generator which is used to generate physical
address from logical address this help to reduce the size of memory.
I have to store 30*32 pixel in memory.NOW for
that i have to generate physical address for those memory
location.THey suggest circular read address generator for this.
But i never read about circular read address generato.So please
anybody tell me about this generator.
Is it possible to reduce memory size using yhis method.
Article: 87809praetorian wrote: > I'm talking about the actual bram, ot the controller. > The code for this is generated on the fly in an EDK project. It should end up being located in project_dir/hdl/elaborate/... So I guess in your case, create a simple project with the desired block ram, then copy and modify the generated file.Article: 87810
Andrew FPGA wrote:
>I am trying understand how a distributed arithmetic design can achieve
>a density of 1 LUT(4 input) per four taps per input data bit. I have
>read the www.andraka.com tutorial and a lot of the many previous posts
>on distributed arithmetic but still cannot see it....
>
>I understand how the scaling accumulator implements a bit serial
>multiply and I see how the partial product summation is moved to be in
>fornt of the scaling accumulator. What I can't see is how the partial
>products for four taps can be implemented in a single 4 input LUT? (I
>realise that a LUT = 16x1 RAM, in Xilinx anyway)
>
>To caculate the partial product for four taps and a single bit position
>of our input data then we need to add four bits? If all four bits are
>1's then our sum results in 3 bits (or 2bits and a carry out). How can
>a single LUT4 represent that? A single LUT has only 1 output bit....
>
>
>
Ok, consider the case where you have a single tap. You'd need to
compute a 1 bit by n-bit partial product
for each bit in the serial input, and then you sum those partial
products with a scaling accumulator. In
that case, the one bit input is gating the coefficient, so that if it is
'1' you get the coefficient out
(1x coefficient=coefficient). If it is '0' then you get '0' out in all
the bits. To do this you have a 1 input,
n output logic function (n outputs to handle the n bits in the
coefficient). This is equivalent to n AND
gates.
Now onto the 4 tap version. In this case you have the sum of 4 of these
1xN functions. If a tap input
bit is '1', then the corresponding coefficient is added to the output.,
if '0' then the coefficient is not added
(ie, you add either 1x or 0x the coefficient for each of the inputs).
If all 4 input bits are '0's, then
you have 0*c0 + 0*c1 + 0*c2 + 0*c3=0. If only one input bit is a '1',
then the n bit output is equal
to the corresponding coefficient. If you have two input bits '1', then
the n output bits are the sum of
the two coefficients corresponding to those inputs. Do you see then,
that there are 16 possible combinations
of inputs, and that the 4 input bits form a 4 bit address into the LUT?
I'm guessing what you were missing is that the DA-LUT is n bits wide, ie
it is comprised of n 4-LUTs.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 87811
You can make a ring oscillator in the FPGA with little trouble. No
guarantees on the frequency, but
you can nail it down to a frequency range that isn't going to vary by
more than maybe +/-50% or so.
That is quite useful in cases where you don't care much about frequency
accuracy or stability. One
application for a ring oscillator is the NBTI prevention circuit for the
DCMs to keep them from
degrading the performance when powered up without a clock. The fact
that your frequency apparently
shifts in the presence of a finger tells me you are just using a ring
oscillator, possibly with a divider.
BTW, I don't believe I said don't use F5MUXs, I said I generally don't
use them in high speed designs.
I also don't use a second layer of LUTs without a flip-flop in between
when I am worried about
performance. Given the choice between going to two layers of 4LUTs or
using an F5MUX, assuming
for some reason I can't rearrange the logic or pipelining to knock the
logic down to 4LUTs, I'll use the
F5MUX because it has shorter and more predictable timing than a second
layer of logic has. One of the
beefs I have with the F5MUX is that it messes up the bit pitch in the
layout. The 5 input logic takes up
a slice, which is normally used for 2 bits, so you need to get a little
more clever in the layout.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 87812Does anyone know of a tool that actually converts a schematic entry design to Verilog/VHDL. I know tools like Quartus can do it but the conversion is at the device level(correct me if I'm wrong). I need conversion to maybe behavioural level(I know I might be dreaming). I work in the avionics industry and certification of the design is critical. Any clues will be appreciated cheers y'all MORPHEUSArticle: 87813
Brad Smallridge wrote: > I have a board with three Spartan3s on it. > Right now, under sources in project, I have > the project name, then xc3s400-4pq208, > and under that > top1-behavioral(top1.vhd), > top2-behavioral(top2.vhd), > top3-behavioral(top3.vhd) > > and stuf under those like the top1.ucf, etc. > > So what happens if one of the Xilinx parts > gets upgraded or downgrade in speed or > size? Can I assign the xc3s400 spec to > each top level design? > > Brad I think when you download programming file (.bit file) that implement with one speed grade to other speed grade fpga, you found an error about id number of device on iMPACT.Article: 87814
Chris Carlen wrote: > Hi: > > I am reading the FAQ on Spartan3 here: > > http://www.xilinx.com/products/spartan3/faq105_s3.pdf > > which says only XC3S50 is supported by WebPack 5.2i. I realize this is > an old version (though the one I am still using since I had trouble with > 6.1i). Now we are at 7.1i, which indicates support for Spartan3 of > course here: > > http://www.xilinx.com/ise/logic_design_prod/webpack.htm > > but doesn't indicate the details about whether it supports larger > Spartan3 devices or not. > > Specifically, I am considering XC3S400. > > Does WebPack 7.1i support that or do I need to start spending $$$ ? > > > Thanks for input. > > > Good day! > > I'm using a XC3S200 with the 7.1i webpack, and the list of devices indicates that up to XC3S1500 is supported. -- BrianArticle: 87815
You can probably find an older version of webpack that still supports xcs10. <googlinggoogler@hotmail.com> wrote in message news:1122729382.393080.195750@g14g2000cwa.googlegroups.com... > Hiya, > > Foolishly I developed a board for a spartan 3 xcs10, without finding > suitable development enviroment, assuming that the free ISE Webpack > would be suitable - just found out now i've gone to fire my board up > and program it that I can't... > > Can anyone suggest a free solution to this? I'm a newbie and would like > to use VHDL on this board, Ive built a JTAG cable to use with the > parrallel port that is to Xilinx specification. > > Yours gratefully > > Dave >Article: 87816
"Telenochek" <interpasha@hotmail.com> wrote in message news:1122921800.476690.247230@f14g2000cwb.googlegroups.com... > I am trying to design with state machines. > For example there is a master FSM (finite state machine), which > calls slave state-machines along the way, waits for them to end (via > slave-busy signals) etc... > Unfortunately this approach becomes very messy very quickly. I think you should be able to fit it into a single, relatively simple, state machine. > I understand the breakdown into components when somebody else writes > it, and I understand the code, and how everything is connected. > The problem arises when I need to come up with all the control signals > myself, and make sure the dynamics of the system is working ok. > > I think thats a digital design problem, rather than a coding problem. > Coding is *relatively* easy when you have a clear design. You should try thinking in terms of hardware. In other words your code should be describing hardware rather than its abstract behaviour. The only exception in my view is a state machine. When I write state machines I usually think in behavioural terms first and then add details later. Which FPGA are you designing for? If you are using Xilinx, I suggest that you use their Core Generator and generate a simple dual port memory buffer. It will create a VHDL component declaration and an instantiation template. Look at the interface and read the data sheet to understand what each of the signals is for. If you are still confused, I can probably share some code with you as I do have some similar designs... /MikhailArticle: 87817
Hi Morpheus, The Mentor FPGA Advantage Tools do what you want. e.g. you can build Schematics with embedded blocks. Embedded block can have one or more processes (or other Statements and comments)inside, and look in the schematic similar (but not equal) to components. Furthermore it works the other way around too. So you can read in existing designs and convert them into schematics for structural analysis (and modification of course). Not to mention that State Diagrams and Flowcharts are also supported in both directions. As you mention that you are working in the avionics industry you surely can afford the price of these tools ;-) Hope this is helpful to you Eilert morpheus schrieb: > Does anyone know of a tool that actually converts a schematic entry > design to Verilog/VHDL. I know tools like Quartus can do it but the > conversion is at the device level(correct me if I'm wrong). I need > conversion to maybe behavioural level(I know I might be dreaming). > I work in the avionics industry and certification of the design is > critical. > Any clues will be appreciated > cheers y'all > MORPHEUS >Article: 87818
Hi Vish, In VHDL you can use the IF-ELSIF Statement. IF A = B THEN --do something ELSIF B = C THEN -- do something else, but only if a=b didnt match before ... ELSE -- do some default stuff if nothing else fits END IF; Depending on the deepth of this structure your design will become quite big and slow though. But the structure creates the priority dependance and if your compares are kept simple (only = and /=) and need only a small ammount of bits it may fit to your needs. have a nice synthesis eilert llabakdas@gmail.com schrieb: > +HI, > Is it possible to create a comparator structure that has a priority > structure eg My system has more than 65% cases where the winner is > determined by the msb(matlab simulations).I am trying to create an > asynchronous system, so early completion would be beneficial for my > system. > > > Essenatially i need a completion detection comparator. > > > THanks > Vish >Article: 87819
<do_not_reply_to_this_addr@yahoo.com> schrieb im Newsbeitrag news:1122935399.899122.35350@o13g2000cwo.googlegroups.com... > Humm... Why wouldn't Xilinx support this cable (I thought Digilent and > Xilinx have a close relationship) and if not Why wouldn't Xilinx > publish the protocols used by Chipscope server. Are they trying to make > money by selling their own expensive USB cable ? > > Sumit > The Xilinx - Digilent co-oper is not so close. Xilinx is NOT publishing the ChipScope server protocol and Xilinx is NOT publishing the Impact server protocol because they may change those with every service pack and the do not want additional hassle from 3rd parties. Maybe some other issues as well. Yes, it looks like Xilinx is trying to make money on the over priced USB Cable, that doesnt work very good. The PCs with LPT port are coming to be 'hard to get' items, so the only official cable is Xilinx USB cable, what is very EXPENSIVE, it only contains Cypress 68013 and Coolrunner, but cost 495$. AnttiArticle: 87820
<coshzz@gmail.com> schrieb im Newsbeitrag news:1122951428.768138.172480@g14g2000cwa.googlegroups.com... > > Brad Smallridge wrote: > > I have a board with three Spartan3s on it. > > Right now, under sources in project, I have > > the project name, then xc3s400-4pq208, > > and under that > > top1-behavioral(top1.vhd), > > top2-behavioral(top2.vhd), > > top3-behavioral(top3.vhd) > > > > and stuf under those like the top1.ucf, etc. > > > > So what happens if one of the Xilinx parts > > gets upgraded or downgrade in speed or > > size? Can I assign the xc3s400 spec to > > each top level design? > > > > Brad > > I think when you download programming file (.bit file) > that implement with one speed grade to other speed grade fpga, > you found an error about id number of device on iMPACT. > you can not use one project for different (size/family) FPGAs. the speed grade only matter for timing analyzer, there is no diff in .bit file. what you need is to setup up commandline scripts to run the synth in batch AnttiArticle: 87821
Hi, I've used circular buffers in DSP programming, everytime you read a value from RAM, the address pointer increments so you don't have to pay attention to addressing. "Circular" means that at the end of the memory, the address pointer makes a wrap around and starts at the beginning of the memory, again. This is usefull for signal processing, e.g. FFT or something. Stefan > hi, > > i m doing project on image processing.For that i need to store pixel > value of any frame in memory. I read from one journal that there is > one circular read address generator which is used to generate physical > address from logical address this help to reduce the size of memory. > > I have to store 30*32 pixel in memory.NOW for > that i have to generate physical address for those memory > location.THey suggest circular read address generator for this. > > But i never read about circular read address generato.So please > anybody tell me about this generator. > Is it possible to reduce memory size using yhis method. >Article: 87822
Hi all, I am Monica from Germany,I am new to FPGA programming.I have very little experience with Altera cyclone FPGA development and Quartus software.I dont have any experience with Xilinx tools.Now our company want to try Xilinx because xilinx offers J.83 Annex A/C Modulator QAM IP core. We have received a AVNET Xilinx Spartan3 board with xc3s1500 FPGA.Our company wants me to test the board with a sample program.But I am having hard time to test the board.The examples(Hello World!) are for EDK software.But we dont have EDK software.We just want to download a sample project and see "Hello World!" on screen. So I tried to use impact software which came with free ISE webpack and tried to download "download.bit",it says that "download.msk" doesnt exist. then I tried to download "system.bit" it says that "programmed sucessfully" but I dont observe any "hello world" on console. Am I missing something?Is this approach not correct?Do we really need EDK software? Please help me regarding this problem.If I have to read any documentation please provide pointers. Thanks in advance. Monica DSouza, GermanyArticle: 87823
Hi. I would need to begin a new fpga design intefacing with external SODIMM at a rate of 400 Mbit/sec/pin. I have 2 alternatives DDR-SODIMM and DDR2-SODIMM. >From fpga interface prespective, which of them is advantagious ? ThankXXXXX NAHUMMMMArticle: 87824
hi
when i make timing simulation with MODELSIM SE after the synthesis and
place and route in XST Tool of Xilinx i never met the data in the
output i dont know why...please help me
this is my lut description:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity lut_mod is
generic(DEEP: integer := 8;
WIDTH: integer := 8
);
port( ready : in std_logic;
add33: in std_logic_vector(DEEP downto 1);
data_lut33: out std_logic_vector(WIDTH downto 1)
);
end lut_mod;
architecture archi_lut_mod of lut_mod is
subtype WORD is std_logic_vector(WIDTH downto 1);
type ROM is array (127 downto -128) of WORD;
constant ROM_array : ROM := ( "11111000",
"11111000",
"11111000",
etc.
"00000111",
"00000111",
"00000111"
);
begin
process(add33, ready)
begin
if ready = '1' then
data_lut33 <= ROM_array(CONV_INTEGER(add33));
else
data_lut33 <= (others => '0');
end if;
end process;
end;
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