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hi stefen,
can we use circular ram in such way that it help to reduce
memory size i.e. suppose if we don't need some of memory space in the
begenning than we rewrite that space with some other data and the use
them
Article: 87901<jjlindula@hotmail.com> schreef in bericht news:1123080462.346149.178820@o13g2000cwo.googlegroups.com... > Hello, I couldn't find a single newsgroup to post my question, but I > needed a good group of people to post my question to. So let me This is stuff you want to discuss with Guy Macon. He hangs around in misc.business.product-dev And of cource it is 100% waste of time, only invented by 'managers' to hide their incompetence. -- Thanks, Frank. (remove 'q' and 'invalid' when replying by email)Article: 87902
<jjlindula@hotmail.com> wrote in message news:1123080462.346149.178820@o13g2000cwo.googlegroups.com... > Hello, [snip] > thanks, > joe > I think I can gaurantee that when you try to define and analyse it you will lose it having not found it in the first place. DNAArticle: 87903
Baxter wrote:
>>The designer software is available as silver edition for free. This
>>edition is OK for smaller devices.
>
> Well, how small? I'm using the eX64 (64 dedicated flip-flops, 3000 system
> gates)
You can't get much smaller than that.
> No "outing" about it - I'm a raw beginner at embedded programming.
Make that, a raw beginner at digital hardware design.
> I've got the book "VDHL Programming by example". I don't know if any of the
> book's tools would be useable.
I've yet to find a CD attached to a book
that is worth trouble to unwrap.
>>[1] Buying a good support from Actel
> As I indicated, the ROI is VERY bad at this point.
Most vendors have "web" editions of their
software that you can download for free.
-- Mike Treseler
Article: 87904
Nial Stewart wrote:
> Do you then code that reset signal using the normal asynchronous reset
> at the start of a clocked process model, or do you code it as a synchronous
> reset?
I use the asynchronous reset template.
As others have noted, this saves gates.
Here is a benchmark of three templates
on the same design:
http://home.comcast.net/%7Emike_treseler/uart.vhd
-- Mike Treseler
Article: 87905What?Article: 87906
Martin Eisenberg wrote: > Tim Wescott wrote: > > >>In most places where it needs to be done the design tradeoffs >>between disciplines that I'm speaking of tend to be done by the >>project manager, or they happen by committee, with electrical, >>software and mechanical engineers getting together and hashing >>things out. If the project manager is smart and/or if the >>committee gets together well then this can make for some very >>good systems designs. Unfortunately it's a chain that's weaker >>than its weakest link, so you have to be careful. > > > What do you mean by that, "weaker than its weakest link"? > It's just a cynical observation that the stupidity of a group can be equal to the sum of the stupidities of the participants. I have seen this sort of design by committee go both ways, so I shouldn't be cynical. If the group is aware of the pitfalls and not afraid of constructively criticizing each other's work then the results can be superior to what any individual could do by him/herself. If, however, the group has even a few jealous empire-builders then the effort tends to collapse upon itself. Similarly, if an insecure project manager does the systems engineering then the system design will often be bounded by the project manager's limitations plus the limitations of the group. If the project manager isn't afraid of other people in the group knowing more than he then the system design will be strong everywhere that anyone in the group is strong; if the team's _really_ good they'll recognize their weaknesses and either change the design to avoid them or get external help in those areas. I've been named "system architect" on more than one project, and I've always been profoundly grateful to the folks that have caught out my errors. I always let folks know this, too -- and not just the folks finding my errors, but their managers as well. At worst the equation goes like this: I do something stupid, you notice and don't say anything; we both look bad. Alternately: I do something stupid, you point it out, we both fix it; we both look good. The best thing about this attitude is that it is one of the areas where, with the right PR, ethical behavior and selfish behavior march hand in hand. When I can say "Ralph found an error in my system design, I did some analysis and found out that my integrator wasn't nearly deep enough for the modified filter" then the project wins because an error has been fixed, Ralph wins because he's gotten credit for finding a problem, I win because I found a solution, _and_ I win because an embarrassing problem with my design was found at an early stage instead of in front of some Major in procurement who really wanted to buy the competitor's product instead. -- Tim Wescott Wescott Design Services http://www.wescottdesign.comArticle: 87907
On 3 Aug 2005 08:41:27 -0700, "jjlindula@hotmail.com" <jjlindula@hotmail.com> wrote: >Hello, to be brief SE involves requirements analysis, risk managment, >controlling your design processes, interface control, supportability, >realiability, maintainability, reproducability, peer reviews and >technical reviews, test planning, integration planning. SE is used to >manage a project to control costs, schedule, and performance. I"m still >learning all the areas and probablity left out a ton of stuff. >Although, I'm more interested in the technical side of SE, rather than >counting the money stuff. So where does the systems engineer fit into the organization? Who does he report to, who reports to him, and how much authority does he have? Does he have to sign off on stuff? JohnArticle: 87908
On Wed, 03 Aug 2005 10:26:56 -0700, John Larkin
<jjlarkin@highNOTlandTHIStechnologyPART.com> wrote:
>On 3 Aug 2005 08:41:27 -0700, "jjlindula@hotmail.com"
><jjlindula@hotmail.com> wrote:
>
>>Hello, to be brief SE involves requirements analysis, risk managment,
>>controlling your design processes, interface control, supportability,
>>realiability, maintainability, reproducability, peer reviews and
>>technical reviews, test planning, integration planning. SE is used to
>>manage a project to control costs, schedule, and performance. I"m still
>>learning all the areas and probablity left out a ton of stuff.
>>Although, I'm more interested in the technical side of SE, rather than
>>counting the money stuff.
>
>So where does the systems engineer fit into the organization? Who does
>he report to, who reports to him, and how much authority does he have?
>Does he have to sign off on stuff?
>
>John
My experience has been that the best systems are architected by a
single person, not by committee.
The EARLY Pentiums were architected by a single person. Need I say
more ?:-)
...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice:(480)460-2350 | |
| E-mail Address at Website Fax:(480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.
Article: 87909jjlindula@hotmail.com wrote: > Hello, to be brief SE involves requirements analysis, risk managment, > controlling your design processes, interface control, supportability, > realiability, maintainability, reproducability, peer reviews and > technical reviews, test planning, integration planning. SE is used to > manage a project to control costs, schedule, and performance. I"m > still learning all the areas and probablity left out a ton of stuff. > Although, I'm more interested in the technical side of SE, rather than > counting the money stuff. At least you can get some job when you somehow do plan these things, it would probably more useful with new people or an unexperienced work group. Many of the procedures fall now into different peoples responsibility, not everyone will react delightful when you take his tasks away. For the NASA it will be more beneficial than for a specialized nice-market company, that has simply not the money to pay another engineer sitting in his office. OTOH this is the ideal function for outsourcing to a consultant. -- ciao Ban Bordighera, ItalyArticle: 87910
hi ravinda, I did't get your point exactly; you always have to use something like adress decoders in order to use the whole memory space for different IPs or something. With circular buffers you just define the length and this is the space that is used. The other memory is free and can be used! There is no difference in need of memory space between circular generated adresses or just adressing your data yourself. rgds, Stefan "ravindra kalla" <ravindra28d@rediffmail-dot-com.no-spam.invalid> schrieb im Newsbeitrag news:aZOdncuWT4qXc23fRVn_vA@giganews.com... > hi stefen, > > > can we use circular ram in such way that it help to reduce > memory size i.e. suppose if we don't need some of memory space in the > begenning than we rewrite that space with some other data and the use > them >Article: 87911
"Jim Thompson" <thegreatone@example.com> wrote in message news:tqv1f19en0pj7rclndiq6r8uvn0mbg3uho@4ax.com... > On Wed, 03 Aug 2005 10:26:56 -0700, John Larkin > <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote: > >>On 3 Aug 2005 08:41:27 -0700, "jjlindula@hotmail.com" >><jjlindula@hotmail.com> wrote: >> >>>Hello, to be brief SE involves requirements analysis, risk managment, >>>controlling your design processes, interface control, supportability, >>>realiability, maintainability, reproducability, peer reviews and >>>technical reviews, test planning, integration planning. SE is used to >>>manage a project to control costs, schedule, and performance. I"m still >>>learning all the areas and probablity left out a ton of stuff. >>>Although, I'm more interested in the technical side of SE, rather than >>>counting the money stuff. >> >>So where does the systems engineer fit into the organization? Who does >>he report to, who reports to him, and how much authority does he have? >>Does he have to sign off on stuff? >> >>John > > My experience has been that the best systems are architected by a > single person, not by committee. > > The EARLY Pentiums were architected by a single person. Need I say > more ?:-) > > ...Jim Thompson System engineering is not need if the design group all pee in the same urinal. Information flow is perfectly terminated with no reflected waves. Notice I did not say design team, they have leaders that don't comprehend the task. Oh, don't get me started! HarryArticle: 87912
hi there, i am new in these thing as well, so i might not be correct. i would recomend to try to set the global clock to jtag clk. right click on "Generate Programming File" -> properties -> startup options and then set FPGA startup clock to JTAG cheersArticle: 87913
You could use FPGA Editor to look at the slice or IOB with the register in question. There are boxes to indicate power-up high or low and S/R high or low. You could also look at your edif output produced by Synplify to make sure the INIT=S property is attached to your instance. If you're *not* using Synplicity tools, the "synthesis xc_props" directive would probably be ignored by the synthesizer. No error, no effect. "vssumesh" <vssumesh_asic@yahoo.com> wrote in message news:1122903343.414347.24370@g43g2000cwa.googlegroups.com... > Hi john... > I tried the first way but it did gave an error. But the second method > did not gave an error but i dont know whether it is initialised > prperly. The set pin is still tied to the ground. Can we assume that > the stet is '1' ? > Sorry for this late replay.... > regards Sumesh >Article: 87914
John, Hello, I didn't say that one project needs to assign a System Engineer. I'm only concerned that the individuals or project lead follow System Engineering practices. What I have seen where I am working, is that the engineer will get the requirements from the customer, then go off into his/her cubical, design the widget, and then deliver. Many times the widget doesn't meet the customer's requirements or a nightmare to program due to hardware limitations. Many of my co-workers say, we don't follow SE practices because our designs are small (their opinion). I'm trying to encourage them that you can apply some of the principles of SE, for me to achieve this I need to see what people in the R/D world are doing, are they using SE? joeArticle: 87915
jjlindula@hotmail.com wrote: > John, > > Hello, I didn't say that one project needs to assign a System Engineer. > I'm only concerned that the individuals or project lead follow System > Engineering practices. What I have seen where I am working, is that the > engineer will get the requirements from the customer, then go off into > his/her cubical, design the widget, and then deliver. Many times the > widget doesn't meet the customer's requirements or a nightmare to > program due to hardware limitations. Many of my co-workers say, we > don't follow SE practices because our designs are small (their > opinion). I'm trying to encourage them that you can apply some of the > principles of SE, for me to achieve this I need to see what people in > the R/D world are doing, are they using SE? > > joe > In my experience, folks who do R&D (which can mean differerent things to different people) tend to be messy desk types who prefer to live that way. SE tends to put some discipline in the process which can be good. There are things out there like being able to integrate matlab with tools like CVS that can help smallish groups.Article: 87916
<jjlindula@hotmail.com> wrote in message news:1123083687.394543.131660@g49g2000cwa.googlegroups.com... > Hello, to be brief SE involves Here is a quick reaction to the list: requirements analysis - the system guru's job for the technical things which can be the whole thing - a marketing / engineering job to trade off feature cost / benefit. (Sales will want everything tomorrow). I've never seen the latter really work but it might in concept. risk managment - what kind of risk? Market risk? Technical risk? Financial risk? Schedule risk? etc. etc. I've seen engineering risk analysis presented that included likely cost/schedule impacts and mitigation actions for the biggies. Only for larger systems. Silly risks are avoided by good engineering - like not choosing to use weird parts, avoiding tricky calibration in the design, etc. controlling your design processes - isn't there a VP Engineering to set policy? Isn't there a way to communicate what's working and not working? It must be a really overdone project to need a *person* dedicated to this. interface control - yeah, on really big, diverse developments. Otherwise a pari of drawings / specs just need to be coordinated and kept in sync. (I once worked on a project as a young engineer ... gee maybe I was the "system engineer" ... I was responsible for an autopilot - which, as you can imagine, was a major system block / module. The system was being built down the street by a large aerospace company. I got a call from a fellow who wanted to better understand one of the components that was used in the autopilot - so I drove over to discuss it with him. Lo and behold, the guy had *no* idea about how the component was being used in the autopilot - none. It was really hard to have a cogent conversation and was really hard to help him). supportability - a worthy area of endeavor. Best done by someone who understands the infrastructure and the end-use needs where the product will live. Better be done up-front. Suggests the system guru again. realiability - when the "system" is a single FPGA you are kinda stuck aren't you? Post-design it's nice to keep track of what's breaking so you might actually fix something. I can remember a lot of times when a customer would have a problem and somebody inside our company would say: "oh yeah, I remember that came up about six months ago" (and nothing had been done). It's nice to be able to try to decide what to fix and what not to fix before some system comes crashing down in the middle of a critical situation. Rarely affordable to have a "person" except in aerospace. Not to say that you can't design for good or bad reliability .... but a statistician probably isn't going to have much of an impact in the design choices unless you're going to spend a whole lot of time in meetings and to hell with the schedule. maintainability - how is this different from supportability really? reproducability - I think you mean produceability. Just part of good engineering with adequate discussion with the manufacturing folks. Not a special discipline / position. peer reviews and technical reviews - part of process. No "person" needed. test planning - sometimes a specialist can be helpful - particularly in software. In hardware it requires someone who really knows what's being tested - as in the system guru or the senior designers? integration planning - the system guru takes the lead and, unless the guru does it all alone (which is common) then it's a group activity. manage a project to control costs, schedule, and performance - AKA the Project Manager who is best also the lead engineer or some other effective manager - but not necessarily the system guru. Sometimes there can be staff support (in aerospace again) but it's not all that helpful to the real manager / management in my opinion. I always do it myself so the planning work gets done when it's needed and not just automatically because it's someone's assignment. "Tracking" to an original plan is a guilt trip except on very large projects where BCWP, ACWP etc. are used as indicators where figuring things out otherwise would be difficult. Above all, figuring out how to get from *today* to the end most efficiently / quickly is useful. (Presumably there is somebody who can recognize the situation and take corrective action if there are weak players - without resorting too much to the "measures"). And you didn't mention "performance measures". I may have had a bad experience or two but I've never seen a situation where "performance measures" were anything but mostly mindless obedience exercises. I'm told that some have great success stories (ala Deming, Juran, Taguchi...) but not me! This could segue into a discussion of general QC which I'd rather not get into..... If there were something akin to "system engineering" that might actually be useful to put some energy into, it could be lurking there. To make a point: It is told that a Japanese company licensed the production of an American engine. They took the original drawings and began production. But they couldn't build engines with those drawings! Why? Because at that time, the Japanese built all the parts to exceptional tolerances so there could be virtually 100% interchangeability. And, because at that time, the Americans had built the parts to looser tolerances and were willing to do some mixing and matching of parts, they didn't recognize that the dimensions in the drawings were "wrong" - that is, a working engine could not be assembled out of a set of parts that were perfect according to the drawings. I don't know if the story is true but it's sure interesting..... FredArticle: 87917
IOB Ranges are supported directly, but depending on what you're trying to do, here are a few ideas: Use a LOC on each IO assigned to a list of sites: NET "name" LOC = "A2, A3, A4,"; Use a LOC on each IO assigned to wildcard site specification (not 100% sure this works): NET "name" LOC = "A*"; Use a LOC on each IO assigned to a Bank: NET "name" LOC = "BANK0"; NET "name" LOC = "TL"; //half-edge constraint NET "name" LOC = "T"; //edge constraint Range constrain your IO to a clock region: For a single region: AREA_GROUP "group_name" RANGE = CLOCKREGION_X#Y#; For a range of clock regions that form a rectangle: AREA_GROUP "group_name" RANGE = CLOCKREGION_X#Y#:CLOCKREGION_X#Y#; For a list of clock regions: AREA_GROUP "group_name" RANGE = CLOCKREGION_X#Y#,CLOCKREGION_X#Y#,...; BretArticle: 87918
bret.wade@gmail.com wrote: > > IOB Ranges are supported directly, but depending on what you're trying > to do, here are a few ideas: > > Use a LOC on each IO assigned to a list of sites: > NET "name" LOC = "A2, A3, A4,"; > > Use a LOC on each IO assigned to wildcard site specification (not 100% > sure this works): > NET "name" LOC = "A*"; > > Use a LOC on each IO assigned to a Bank: > NET "name" LOC = "BANK0"; > NET "name" LOC = "TL"; //half-edge constraint > NET "name" LOC = "T"; //edge constraint > > Range constrain your IO to a clock region: > For a single region: > AREA_GROUP "group_name" RANGE = CLOCKREGION_X#Y#; > > For a range of clock regions that form a rectangle: > AREA_GROUP "group_name" RANGE = CLOCKREGION_X#Y#:CLOCKREGION_X#Y#; > > For a list of clock regions: > AREA_GROUP "group_name" RANGE = CLOCKREGION_X#Y#,CLOCKREGION_X#Y#,...; > > Bret > I'm not trying to give LOC constrainst. If you read the constraints guide, the AREA_GROUP/RANGE pair has an IOB constraint. I just want to know how that is use.Article: 87919
Stan, You hit the nail right on the head. That is what my work environment is like. No discipline at all. I'm trying to add some process control and not having much success with the older more experienced engineers. But, the younger engineers are very excited because following SE practices allows them to help manage complexity, which is good. thanks again, joeArticle: 87920
Thanks Fred, you did a great job, I know it will help a lot of engineers, me too, who are still new to SE practices. joeArticle: 87921
I am looking for some help in regards to a 20 MHz modulation clock that needs to set the timing in the Virtex_II_Pro. I was investigating running the modulation clock into a DCM; However, the minimum input frecquency for CLKIN is 24MHz. The 20 MHz modulation clock needs to establish the timing in the FPGA for synchronizing the 80MHz ADC and for digital mixing of the modulation frequency. If I can not use a DCM, how do I create the synchronous timing for my subsystems 80MHz and digital mixing?Article: 87922
>you can not use one project for different (size/family) FPGAs It seems like one should be able to set up one project with multiple parts and be able to assign different packages. What do the big boys do? I've seen plenty of boards with more than one Xilinx on them. BradArticle: 87923
Hi Joe, You can find some definitions and nice opinions about sys engineering here: http://www.iee.org/oncomms/pn/systemseng/definition.cfm P.S. If I were you, I would use more specific terms when trying to convince my colleagues to do something, instead of ambiguities such as "system engineering practices". Take software projects for example, terms such as CMM are a lot more well-defined and therefore more powerful. KArticle: 87924
> http://home.comcast.net/%7Emike_treseler/uart.vhd Wow, that's an interesting use of procedures to automatically restructure a program. I brought the question of async vs. sync reset to the group awhile ago, and someone told me (they should harp in here to get credit), that with an async reset you may have metastable issues when your reset goes inactive, which sort of defeats the purpose of having a reset. So this sold me on sync resets, end of story. When does a CPU know when to reset the FPGA? PowerUp timing delay? I am using a Cypress USB chip which has some interesting PowerUp ennumeration and renumeration issues if anyone has any experience with this sort of thing. Brad
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