Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
sarath schrieb: > Hi all, > Can any one tell me what is RAPID PROTOTYPING and how will this > technology help us in faster designing of products in FPGA. > Can you please tell me some source where I can get basics of RAPID > PROTOTYPING. > Thanks in Advance, > Sarath > Hi Sarath, just think a moment: What can be more rapid(faster) than downloading your generated bitstream into silicon? There is no Rapid Prototyping technology for FPGAs, because FPGAs themselves are a rapid prototyping technology. Either to reduce the time to market (FPGA runs -> sell device immediately) or to test functional parts of a large ASIC design. In the second case you replace your ASIC with a number of FPGAs and connect this "breadboard" to the rest of your device (e.g Input and Output stuff). So you can actually work with the whole device without having the real ASIC (which takes time and lots of money to produce). have a nice synthesis EilertArticle: 88176
hi
i posted the following already in comp.lang.vhdl but perhaps somebody
can help me here:
i created a lookup Table:
type SBOX_TYPE is array ( 0 to 255) of std_logic_vector(7 downto 0);
constant SBOX_Table: SBOX_TYPE := ( ........ );
in my actual code i have a state machine with different states. i have
4 states (sub0 to sub3) in which i call SBOX_TABLE.these states can
never be acticve at the same time.
if s_State_Sub0 = '1' then
v_Word(0) <= SBOX_Table(conv_integer(v_Word(0)));
s_Next_State_Sub0 <= '0';
s_Next_State_Sub1 <= '1';
elsif s_State_Sub1 = '1' then
v_Word(1) <= SBOX_Table(conv_integer(v_Word(1)));
s_Next_State_Sub1 <= '0';
s_Next_State_Sub2 <= '1';
elsif s_State_Sub2 = '1' then
v_Word(2) <= SBOX_Table(conv_integer(v_Word(2)));
s_Next_State_Sub2 <= '0';
s_Next_State_Sub3 <= '1';
else s_State_Sub3 = '1' then
v_Word(3) <= SBOX_Table(conv_integer(v_Word(3)));
s_Next_State_Sub3 <= '0';
s_Next_State_RCON <= '1';
end if;
when i synthesize my code now (im using the xilinx web pack ise 7.3) it
generates 4 rom tables which use up a lot of space. how can i reduce
this
to one since i never access it at the same time?
thanks
Article: 88177Hi, I'm using the Xilinx Platform Studio and I'm tryng to connect the embedded tri-mode-MAC with the PowerPC405. reading the datasheet seems that the PPC and the MAC are already connected to the DCR bus, but is not evident at all how to "see" in the XPS tree the MAC. I tryed to use the application "import/create user peripherial" without success. Does anyone have any experience at all? Thanks, FrancescoArticle: 88178
Dear Dave, why not use a FPGA or a CPLD instead of an ASIC? the Spartan3 and coolrunner (from Xilinx) for example seems reasonable cheep. The advantage using FPGA are: 1. reduced risk (if you do a mistake you can fix it even after the production and distribution) 2. the costs in the design are lower (much lower) 3. the time to market is shorter If the application is so straight forward maybe a CPLD like coolrunner is enougth. Also another advantage iss that now you can download all the SW you need to program and simulate the CPLD and many FPGA from the Xilinx Website for free and in my experience the tool ISE7.1 is now very very stable. Regards, FrancescoArticle: 88179
Have read the answers with attention ? "Define SBOX as a separate entity with an address input port and a data output port. then in your state machine, assign values to the address variable. this way your tool will be able to generate a mux for the address and you'll need only one copy of the SBOX. " That is a possible solution. Rgds Andr=E9Article: 88180
yes i did but that answer was posted after my question here. sorry. thanks for the help!Article: 88181
"Antti Lukats" <antti@openchip.org> schrieb im Newsbeitrag news:ddd82c$emr$05$1@news.t-online.com... > hi > > anybody knows where did the download for Forge compiler evaluation disappear > at www.xilinx.com ??? > > there are still forums about Forge at Xilinx.com but the no links to the > product at all, whats happening ? > > Antti > > As of email dated yesterday Xilinx has confirmed that Forge is no longer available. eg FORGE is DEAD. Confirmed. Antti PS I wonder why Xilinx did purchase LavaLogic in the first place? just to kill their product? well there are questions I dont have answers for :(Article: 88182
In this case, 'not synthesisable' means the same thing as ignored - the value of the delay will be set to (nominally) zero for synthesis. The delay is needed for some simulation purpose, possibly because the block that is being fed by your signal load_r has some hold time requirement with respect to the clock. This is likely to be the case if the downstream block is a simulation model of something that actually requires hold time in real life.Article: 88183
u_stadler@yahoo.de schrieb:
> hi
--snip
> in my actual code i have a state machine with different states. i have
> 4 states (sub0 to sub3) in which i call SBOX_TABLE.these states can
> never be acticve at the same time.
>
--snip
>
> else s_State_Sub3 = '1' then
> v_Word(3) <= SBOX_Table(conv_integer(v_Word(3)));
> s_Next_State_Sub3 <= '0';
> s_Next_State_RCON <= '1';
> end if;
>
> when i synthesize my code now (im using the xilinx web pack ise 7.3) it
> generates 4 rom tables which use up a lot of space. how can i reduce
> this
> to one since i never access it at the same time?
>
>
> thanks
>
Hi,
since the sources and destinations of the 4 assignments are different
the synthesizer infers 4 S-Boxes. The synthesizer doesn't have the
intelligence to create a multiplexer demultiplexer around the sbox.
So try this:
in your States: Boxadress <= v_word(n);
v_word(n)<= Boxdata ;
outside your statemachine :
Boxdata <=SBOX_Table(conv_integer(Boxadress );
Now the synthesizer generates the mux/demux pair and connects it with
one ROM.
Have a nice synthesis
Eilert
Article: 88184alessandro.strazzero@gmail.com wrote: > Dear everybody, > > I have to design an ALTERA Cyclone FPGA based board which will be > used in a rugged environment in terms of operating temperature > (-40 to +85 =B0C) and strong EMI interference. > I have to provide for the clock to the FPGA and I would like to use > a 16 MHz oscillator which will be multiplicated by 8 by the Cyclone > internal PLL in order to obtain a 128 MHz clock for the NIOS II > processor. > > My doubts are the following: > - is a good choise to connect directly the oscillator output to the > FPGA pin or for this kind of environment is suggested to build a > more reliable circuit around the oscillator ? > - is a good choise using the internal PLL ? Is it reliable in a > rugged environment ? (I have chosen an external low frequency > oscillator to reduce EMI emissions) > - are there exist on the market any oscillator specifically designed > for rugged environment ? > > Hope someone of you have already experienced these kind of > problematics in order to suggest me the best way to run. > > Best Regards > > /Alessandro Strazzero I think the idea of using PLL to reduce EMI may not work to your advantage. Externally induced noise can add to the jitter at the input pin of the FPGA in a single-ended implementation (most low-frequency oscillators are single ended and have relatively slow rise and fall times). If you can find a 128 MHz oscillator meeting the environmental requirements and LVDS or PECL output, you'll get lower EMI (due to differential drive) and reduced jitter. Check out offerings by Suntsu at: http://www.suntsuinc.com Including 2.5V LVDS at up to 200 MHz and -40 to +85 temp.Article: 88185
Hello, Anybody knows when LatticeXP parts will be available over distributors in small quantities? Less than 25 pcs. Thanks, M. Veselic Sigma Lab.Article: 88186
"Maki" <veselic@eunet.yu> schrieb im Newsbeitrag news:1123766432.334453.218610@g43g2000cwa.googlegroups.com... > Hello, > > Anybody knows when LatticeXP parts will be available over distributors > in small quantities? Less than 25 pcs. > > Thanks, > M. Veselic > Sigma Lab. > someone from WBC said more than a month ago he can supply XP10 immediatly. I think the other members are still not available. AnttiArticle: 88187
Check out Gigabit System Reference Design (GSRD): http://www.xilinx.com/gsrd/ It uses the Virtex4 embedded TEMAC, is delievered as an EDK project, and runs PowerPC Linux. Paul francesco.poderico@trendcomms.com wrote: > > Hi, I'm using the Xilinx Platform Studio and I'm tryng to connect > the embedded tri-mode-MAC with the PowerPC405. > reading the datasheet seems that the PPC and the MAC are already > connected to the DCR bus, but is not evident at all how to "see" in the > XPS tree the MAC. > I tryed to use the application "import/create user peripherial" without > success. > Does anyone have any experience at all? > > Thanks, > FrancescoArticle: 88188
Hello, does anybody know about clock accuracy - I need a very stable clock to synchronize 2 devices via a RF connection. They must exactly have the same clock, at this time I'm using a 100 MHz clock generator and a Spartan-3 fpga. But for my intended purpose it's not accurate enough. That means, on a scope my generated data bursts of each device with a interval of 3 us are "running away" (that ones those aren't triggered). The 3 us intervals differ perhaps in half a ns or something. Is there a practicable solution for such a problem? Does a DLL with clock mirroring eliminate the problem? Thanks in advance, StefanArticle: 88189
Whoever said Kiwis and Aussies cannot work together? :-) My suggestion divides just by 2229, for minimum jitter, accepting a frequency error. The basic idea is to avoid decoding the counter ( 12-input AND gate!) and instead loading the counter (synchronously!) with the 2s complement, so that if overflows every 2229th clock tick. That technique goes back to the 74161 days of the 1970s: "Don't decode, load instead. It's faster, simpler, and cheaper". Any questions, send me an e-mail. Peter Alfke, from home, just woke up... peter@xilinx.comArticle: 88190
On Sat, 06 Aug 2005 23:22:44 -0500, hmurray@suespammers.org (Hal Murray) wrote: (snipped) > >Many years (10?) ago, my boss handed me a paper titled "Bugs are Good" by >Doug Clark. Scribbled on it was "must read". I haven't been able to >find it online, but it's easy to find references to it. (We were all >working for DEC/Digital at the time.) > (snipped) Hi, "DEC/Digital", huh? Didn't they used to make computers? [-Rick-]Article: 88191
Stefan, DLL with clock mirroring would eliminate a skew between the clocks, but if I understand you correctly, you are facing not a simple issue, especially because you have 100 MHz and you want to use RF connection as a link. That is, you have to embed certain information in the outgoing data, such as the information about your local clock. The common way to do this is to run, for example, 50-bit wide counter with 100 MHz clock in one end and transfer the value of the counter through the data to another end. In the another end, there is the same counter and this value is compared with the one embedded in the data traffic. The difference between the two gives you an estimation about the difference between the two clocks. The rest depends on the device that you are using for clock generation and its crystal pullability or frequency range that you can use. If your clock would have been much slower, there is a way to do this using very high-speed clock & phase shift technique. If you could give a few more details.......... Hope this helps. Vladislav "Stefan" <holzi_stefan@hotmaildotcom.nospam> wrote in message news:ddfm7g$fuf$1@wsc10.lrz-muenchen.de... > Hello, > > does anybody know about clock accuracy - I need a very stable clock to > synchronize 2 devices via a RF connection. They must exactly have the same > clock, at this time I'm using a 100 MHz clock generator and a Spartan-3 > fpga. But for my intended purpose it's not accurate enough. That means, on > a > scope my generated data bursts of each device with a interval of 3 us are > "running away" (that ones those aren't triggered). The 3 us intervals > differ > perhaps in half a ns or something. > Is there a practicable solution for such a problem? Does a DLL with clock > mirroring eliminate the problem? > > Thanks in advance, > > Stefan > >Article: 88192
Hello Vladislav, the problem is that I cannot transfer data via my RF link. (in the end this is the aim...) I just transmit bursts of a 200 Mbit signal with a interval of 3 us. These bursts contain data for a spread spectrum calculation, and are only used with a analog correlator. To transmit data, I invert the bits from this burst and after that on the correlator the output is -1 (instead of 1 before). And for this purpose, I have to synchronize these 2 bursts. I just tried to use a DCM for clock generation, with no effect. Really annoying... I got so far in this project and now this problem... Any suggestions? Regards, Stefan "Vladislav Muravin" <muravinv@advantech.ca> schrieb im Newsbeitrag news:8wJKe.8472$yH2.405404@news20.bellglobal.com... > Stefan, > > DLL with clock mirroring would eliminate a skew between the clocks, but if I > understand you correctly, you are facing not a simple issue, especially > because you have 100 MHz and you want to use RF connection as a link. That > is, you have to embed certain information in the outgoing data, such as the > information about your local clock. > > The common way to do this is to run, for example, 50-bit wide counter with > 100 MHz clock in one end and transfer the value of the counter through the > data to another end. In the another end, there is the same counter and this > value is compared with the one embedded in the data traffic. The difference > between the two gives you an estimation about the difference between the two > clocks. > > The rest depends on the device that you are using for clock generation and > its crystal pullability or frequency range that you can use. > If your clock would have been much slower, there is a way to do this using > very high-speed clock & phase shift technique. > > If you could give a few more details.......... > > Hope this helps. > Vladislav > > > "Stefan" <holzi_stefan@hotmaildotcom.nospam> wrote in message > news:ddfm7g$fuf$1@wsc10.lrz-muenchen.de... > > Hello, > > > > does anybody know about clock accuracy - I need a very stable clock to > > synchronize 2 devices via a RF connection. They must exactly have the same > > clock, at this time I'm using a 100 MHz clock generator and a Spartan-3 > > fpga. But for my intended purpose it's not accurate enough. That means, on > > a > > scope my generated data bursts of each device with a interval of 3 us are > > "running away" (that ones those aren't triggered). The 3 us intervals > > differ > > perhaps in half a ns or something. > > Is there a practicable solution for such a problem? Does a DLL with clock > > mirroring eliminate the problem? > > > > Thanks in advance, > > > > Stefan > > > > > >Article: 88193
Some people like to put the delay in as you've shown so that when they look at wavfeforms in their simulation they clearly see the clock transition, a delay, then the register changes. The delay is ignored by synthesis tools. Delays are also useful for modeling input/output delays in testbenches to mimic what happens in I/O buffers. I hope this helps. John ProvidenzaArticle: 88194
For a fast imaging system, we plan to use the LX60 together with x36 organized RLDRAM-II devices? Has someone else allready made successful realisation and implementation of such a system other than the ML461 board, and is willing to share the hints and tips with the community? Are (tested and verified) IP cores available for purchase other than the one from Xilinx, (VHDL preferred)? - Required Clk Speed ~ 250 Mhz - Required Chips per FPGA ~ 4 (x36 organized CIO interface) BTW it seems to be hard to get the RLDRAM-II devices such as the : MT49H32M9 ... Any tipps where to buy? Best Regards Markus ----== Posted via Newsfeeds.Com - Unlimited-Uncensored-Secure Usenet News==---- http://www.newsfeeds.com The #1 Newsgroup Service in the World! 120,000+ Newsgroups ----= East and West-Coast Server Farms - Total Privacy via Encryption =----Article: 88195
hi,
i made a architecture,in which i want to run 18 proccessing
elements parrallely.Each processing element is connect with one
memory module.every memory module should store 256 bytes.Is it
possible to implement it in XILINX.If yes , how can i do so.Please
help.
What is the maximum size i can store in memory of XILINX.
Article: 88196Thanks Klaus!Article: 88197
Hi I wonder if Xilinx does any testing of their releases at all - creating Hard Macros seems to be impossible in 7.1 as the FPGAeditor self terminates itself on any attemp to add extpin. Well it seems to be that 6.3 made hard macros are compatible and useable in 7.1 but its very awkward to keep a copy of 6.3 only for that purpose. Antti PS to Xilinx, yes I did open a WebCase. I have plenty of webcases open. So far NO HELP.Article: 88198
>>>From fpga interface prespective, which of them is advantagious ?
>
> Depends on what FPGA you want to use... If it's a Xilinx Virtex2Pro or
> Virtex-4, then you can use free, ready-to-use IP-cores from Xilinx for
> both DDR and DDR2, no need to design the controller yourself. And, trust
> me, you don't really want to design a DDR memory controller yourself if
> it isn't absolutely neccessary. Designs like that are usually a PITA
> with all the phase-shifting and data valid windows and crap like that...
It could be worth looking into the technology a bit more, and reading a
few application notes. DDR2 is newer and is designed to be able to go
faster - if (and I'm no expert) this allows for greater data valid
windows, then it may be better to go for DDR2 for the better margins.
It's also going to depend on which FPGA you use - V4s, for instance,
have better support for source-synchronous IO than some of early
{Xilinx} designs, which may make the job easier - not too much of a
problem if you use a core though, and don't actually have to do the
design yourself.
my 2c
Jeremy
Article: 88199Completely clear now Jim, many thanks. PeterC.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z