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Messages from 83875

Article: 83875
Subject: true dual port memory v/s simple dual port memory
From: praveen.kantharajapura@gmail.com
Date: 9 May 2005 02:54:48 -0700
Links: << >>  << T >>  << A >>
Hi all,

I wanted to know the differnce between a true dual port memory and a
simple dual port memory in FPGA context.

Thanks in advance,
Praveen


Article: 83876
Subject: 8051 IP core
From: "CODE_IS_BAD" <Puneetsingh81@gmail.com>
Date: 9 May 2005 03:40:32 -0700
Links: << >>  << T >>  << A >>
hi all...
  i would like to know wether anyone of you has used Oregano's free
8051 IP core. Also i read somewhere that this core cannot be
synthesized on the xilinx or Quartus software. Is it true? Please let
me know. 
Thanx in advance


Article: 83877
Subject: Xilinx VIIPro mixed configuration voltages
From: "Roger" <enquiries@rwconcepts.co.uk>
Date: Mon, 09 May 2005 10:46:29 GMT
Links: << >>  << T >>  << A >>
I'm using a VIIPro with Bank 4 Vcco set to 3.3V. The PROM is an XCF04S which 
has separate Vccint (must be 3.3V), Vccjtag and Vcco (can be 2.5 / 3.3V) 
connections. I'm a little confused as the FPGA has some configuration pins 
that are 2.5V (Vccaux) which apparently cannot be driven to 3.3V but in the 
datasheet it states that the configuration device Vcco and the FPGA Vcco 
need to be the same value. If I could use 2.5V I would but in this case it 
has to be 3.3V.

I might have figured this out OK but the datasheet information on the PROM 
and FPGA seem to contradict in some places. Does anyone have any experience 
of doing this and any advice that would be useful?

So far I've put a 4K7 pull-up to 3.3V on the OE/Reset to Init_B line, a 4K7 
pull-up to 2.5V on the CF to ProgB line and a 4K7 pull-up to 2.5V on the nCE 
to DONE line. On the PROM all Vccs are 3.3V. A screenshot of the diagram is 
available at the link:
http://www.rwconcepts.co.uk/pdfs/screen_shot.pdf if interested.

TIA for any help.

Rog.





Article: 83878
Subject: Re: Xilinx VIIPro mixed configuration voltages
From: "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk>
Date: Mon, 9 May 2005 12:15:12 +0100
Links: << >>  << T >>  << A >>
Given your are using the Platform Flash you are probably using slave serial 
mode programming. CCLK will be driven by the V2-Pro so what you need to be 
careful of is the data input voltage levels. Usually I wire the relevant 
bank voltage Vcco to the Platform Flash to solve this issue. Usually the DIN 
goes in on bank4 or 5 but check that for your given device.

John Adair
Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan-3 Development 
Board.
http://www.enterpoint.co.uk


"Roger" <enquiries@rwconcepts.co.uk> wrote in message 
news:9cHfe.19252$wu2.5906@newsfe1-gui.ntli.net...
> I'm using a VIIPro with Bank 4 Vcco set to 3.3V. The PROM is an XCF04S 
> which has separate Vccint (must be 3.3V), Vccjtag and Vcco (can be 2.5 / 
> 3.3V) connections. I'm a little confused as the FPGA has some 
> configuration pins that are 2.5V (Vccaux) which apparently cannot be 
> driven to 3.3V but in the datasheet it states that the configuration 
> device Vcco and the FPGA Vcco need to be the same value. If I could use 
> 2.5V I would but in this case it has to be 3.3V.
>
> I might have figured this out OK but the datasheet information on the PROM 
> and FPGA seem to contradict in some places. Does anyone have any 
> experience of doing this and any advice that would be useful?
>
> So far I've put a 4K7 pull-up to 3.3V on the OE/Reset to Init_B line, a 
> 4K7 pull-up to 2.5V on the CF to ProgB line and a 4K7 pull-up to 2.5V on 
> the nCE to DONE line. On the PROM all Vccs are 3.3V. A screenshot of the 
> diagram is available at the link:
> http://www.rwconcepts.co.uk/pdfs/screen_shot.pdf if interested.
>
> TIA for any help.
>
> Rog.
>
>
>
> 



Article: 83879
Subject: Quartus II - multicyle option
From: Laurent Gauch <laurent.gauch@DELETEALLCAPSamontec.com>
Date: Mon, 09 May 2005 13:45:07 +0200
Links: << >>  << T >>  << A >>
Hi,

I setup the multcyle constraint for a reg-to-reg path as :
set_instance_assignment -name MULTICYCLE 2 -from "dlatch_bus:I12|D[4]" 
-to "dlatch_bus:I18|Q[8]"

Also, I setup the global clk frequency as :
set_global_assignment -name FMAX_REQUIREMENT "100.0 MHz"

After synth. and P&R with Quartus-II, I still received the warning as:
-> -6.400 ns	60.98 MHz ( period = 16.400 ns )	dlatch_bus:I12|Q[4] 
dlatch_bus:I18|Q[8]	INCLK	INCLK	10.000 ns	7.600 ns	14.000 ns

DO YOU HOW TO SETUP CORRECTLY A MULTICYCLE PATH IN QUARTUS II ?

PS: I did the same with Xilinx ISE, and works fine !

Larry,
www.amontec.com

Article: 83880
Subject: Re: Quartus II - multicyle option
From: Laurent Gauch <laurent.gauch@DELETEALLCAPSamontec.com>
Date: Mon, 09 May 2005 14:07:01 +0200
Links: << >>  << T >>  << A >>
Laurent Gauch wrote:

> Hi,
> 
> I setup the multcyle constraint for a reg-to-reg path as :
> set_instance_assignment -name MULTICYCLE 2 -from "dlatch_bus:I12|D[4]" 
> -to "dlatch_bus:I18|Q[8]"
> 
> Also, I setup the global clk frequency as :
> set_global_assignment -name FMAX_REQUIREMENT "100.0 MHz"
> 
> After synth. and P&R with Quartus-II, I still received the warning as:
> -> -6.400 ns    60.98 MHz ( period = 16.400 ns )    dlatch_bus:I12|Q[4] 
> dlatch_bus:I18|Q[8]    INCLK    INCLK    10.000 ns    7.600 ns    14.000 ns
> 
> DO YOU HOW TO SETUP CORRECTLY A MULTICYCLE PATH IN QUARTUS II ?
> 
> PS: I did the same with Xilinx ISE, and works fine !
> 
> Larry,
> www.amontec.com


OOPs, I used
 > set_instance_assignment -name MULTICYCLE 2 -from "dlatch_bus:I12|D[4]"
 > -to "dlatch_bus:I18|Q[8]"

I have to use
 > set_instance_assignment -name MULTICYCLE 2 -from "dlatch_bus:I12|Q[4]"
 > -to "dlatch_bus:I18|Q[8]"

Stupid issue. ;-)

Article: 83881
Subject: Re: 8051 IP core
From: Markus Meng <meng.engineering@bluewin.ch>
Date: Mon, 09 May 2005 14:48:39 +0200
Links: << >>  << T >>  << A >>
CODE_IS_BAD schrieb:
> hi all...
>   i would like to know wether anyone of you has used Oregano's free
> 8051 IP core. Also i read somewhere that this core cannot be
> synthesized on the xilinx or Quartus software. Is it true? Please let
> me know. 
> Thanx in advance
> 
If this code is for free, download it, look at it, you will figure out
easily, if it can be used or not. Anyway in that area you should at 
least understand what the code is doing ... ;-)

----== Posted via Newsfeeds.Com - Unlimited-Uncensored-Secure Usenet News==----
http://www.newsfeeds.com The #1 Newsgroup Service in the World! 120,000+ Newsgroups
----= East and West-Coast Server Farms - Total Privacy via Encryption =----

Article: 83882
Subject: Re: DVI implementation
From: Martin Thompson <martin.j.thompson@trw.com>
Date: 09 May 2005 13:53:12 +0100
Links: << >>  << T >>  << A >>
Benjamin Menküc <benjamin@menkuec.de> writes:

> Hi,
> 
> sure it can be implemented. I am about to do it.
> 
> What concerns do You have exactly?
> 
> Serialization is no problem (I have done it for a LVDS LCD Interface).
> I/O cell, what do You mean? You have to use the OBUFDS Peripheral of
> the FPGA (in my case Xilinx Virtex II Pro), that does the electrical
> LVDS stuff.

Are you sure that the OBUFDS does the job - LVDS is different to TMDS,
which is what DVI specifies?  Last I spoke to Xilinx, they do not
support TMDS so far.

The TMDS drivers only drive an active-low via a current-source, with a
resistive termination pullup at the receiver.  Fig 4-1 in my DVI spec.

Cheers,
Martin

-- 
martin.j.thompson@trw.com
TRW Conekt, Solihull, UK
http://www.trw.com/conekt

Article: 83883
Subject: Re: true dual port memory v/s simple dual port memory
From: "Mike Lewis" <someone@micrsoft.com>
Date: Mon, 9 May 2005 09:22:32 -0400
Links: << >>  << T >>  << A >>

<praveen.kantharajapura@gmail.com> wrote in message 
news:1115632488.499339.74150@g14g2000cwa.googlegroups.com...
> Hi all,
>
> I wanted to know the differnce between a true dual port memory and a
> simple dual port memory in FPGA context.
>
> Thanks in advance,
> Praveen
>

Well ... I'll take a guess .. alot of people refer to dual port and two port 
memory ...
the difference being that a dual port memory has a read and write capability 
on both
ports whereas a two port has a read-only port and a write-only port.

I would bet that a true dual port is the dual port I have described above
and a simple dual port is the two port memory I have described above.

Mike 



Article: 83884
Subject: Uart16550 can't receive data over 16byte a time
From: ARRON <mlpei279@gmail.com>
Date: Mon, 9 May 2005 06:22:43 -0700
Links: << >>  << T >>  << A >>
I send 50 bytes character to serial port of UART1655 in FPGA Board,But only the first 16 bytes of received data is correct in turn, and the left is out of order,what is the matter?

thanks for your help!!!

Article: 83885
Subject: TRACE and Modelsim Timing Help
From: "GianniG" <galiero@unina.it>
Date: 9 May 2005 06:47:49 -0700
Links: << >>  << T >>  << A >>
Dear Gurus,

I hope that someone would help me on how to interpret the following
timing parameters. Thank You very much in advance.

I have to interface an ADC to a VirtexII-4 Board, 16 bit data + 1 clk;
both data and Clk are LVPECL. I have successfully implemented such
interface at a frequency of 300 MHz and now I would like to increase
the frequency at 500 MHz.
On each rising edge of the 500 MHz clk a new data sample is transmitted
out by the ADC; the Virtex II interface to such data consists basically
of a DDR registers in a single IOB and the 250MHz clock for these
registers is derived by the incoming 500 MHz by means of a DCM. I have
imposed the following OFFSET IN constraint in the UCF file:

TIMEGRP "InputData" OFFSET = IN 0 ps before "clk"  ;

The output of TRACE is :

- Data Input Delay 1.745 ns (that match with the IOB setup time +
LVPECL adjustment time as taken by VirtexII data sheet)

- Clock Delay 0.598 ns

Minimum OFFset In is 1.147 ns.

In this way by selecting a proper value for the initial phase of the
250 MHz clk I could met the IOB setup time.

Question: If I have well understood the minimum 250 clk arrival time I
should set is 1.147 ns (so that clk delay + clk arrival time should be
>= 1.745 ns); in this way the maximum clk arrival time I could set
should be 1.391 ns (in fact 0.598 + 1.391 = 1.989 ns) to avoid to go
beyond the 500 MHz clk period and have another data value at the pad
inputs. But I got right values with TRACE until the clk arrival time of
the 250 MHz clk is below 2 ns, in this way it seems to me that the clk
delay of 0.598 ns is not taken into account; what have I missed?
I run even a Post P&R simulation to verify the values given by TRACE
and I have  discovered that the clk arrival time of the 250 MHz clk is
not the expected value of 0.598 ns + 1.265 ns (supposing to have set
such value in the DCM Gui) but 0.847 ns (so it seems that the value
given by the simulator is 481 ps smaller than the value set in the DCM
Gui without taken into account the 0.598 ns clk delay); I am missing
something, but What?

Thank You very much for Your help.

GianniG


Article: 83886
Subject: Re: Uart16550 can't receive data over 16byte a time
From: John_H <johnhandwork@mail.com>
Date: Mon, 09 May 2005 13:48:01 GMT
Links: << >>  << T >>  << A >>
ARRON wrote:
> I send 50 bytes character to serial port of UART1655 in FPGA Board,But only the first 16 bytes of received data is correct in turn, and the left is out of order,what is the matter?
> 
> thanks for your help!!!

Do you read the characters as they're received or wait until all 50 are 
sent?

I'm assuming the UART1655 is a core in the FPGA; this is probably 
implemented with a simple 16 byte FIFO beacause the software is expected 
to service the characters as they're received without extreme latency; 
if nothing else, a high priority service when the FULL flag is set if 
the low priority service for partial fill (or single characters) haven't 
been serviced.

If you need a larger receive buffer, it can be done but I don't know if 
you have access to the UART1655 source code.  If you do, (assuming 
Xilinx:) the 16-byte SRL16 style FIFO can be changed to a 2 kByte 
BlockRAM to have more storage.

Article: 83887
Subject: Re: Using capacitor to slow the rise time.
From: Brijesh <brijesh_xyz@cfrsi_xyz.com>
Date: Mon, 09 May 2005 09:54:58 -0400
Links: << >>  << T >>  << A >>
> 8) Do you use pull up resistors on fast CMOS busses that require less 
> than 10ns/V rise / fall time?
I dont know the answer to this question. Never worked with CMOS devices. 
Does  it have anything to do with the fact that CMOS has lower rise time 
than fall time? In our VLSI class projects when were building the CMOS 
gates we would always make the P type gate twice as large as N type just 
to take care of this issue.

Brijesh

Article: 83888
Subject: Re: Uart16550 can't receive data over 16byte a time
From: Aurelian Lazarut <aurash@xilinx.com>
Date: Mon, 09 May 2005 15:02:45 +0100
Links: << >>  << T >>  << A >>
FIFO full?
Aurash

ARRON wrote:

>I send 50 bytes character to serial port of UART1655 in FPGA Board,But only the first 16 bytes of received data is correct in turn, and the left is out of order,what is the matter?
>
>thanks for your help!!!
>  
>


-- 
 __
/ /\/\ Aurelian Lazarut
\ \  / System Verification Engineer
/ /  \ Xilinx Ireland
\_\/\/
 
phone:	353 01 4032639
fax:	353 01 4640324
    
     


Article: 83889
Subject: Altera: Maxplus rules!
From: "Fred" <Fred@nospam.com>
Date: Mon, 9 May 2005 15:03:28 +0100
Links: << >>  << T >>  << A >>
I have a Maxplus design which is a year or more old which was compiled with 
Maxplus.  So far so good.  I am required to make a small alteration.

The licence has expired and Maxplus seems obsolete so my only option is to 
download Quartus.

Oh dear - I have never come across such a long winded process to convert 
things to Quartus.

After all the changes - Lo and behold it won't fit!

Is this called progress?

What on earth is wrong with allowing the use of "outdated" software for 
"outdated" designs? 



Article: 83890
Subject: Re: DVI implementation
From: =?ISO-8859-1?Q?Benjamin_Menk=FCc?= <benjamin@menkuec.de>
Date: Mon, 09 May 2005 16:26:25 +0200
Links: << >>  << T >>  << A >>
Hi,

I figured out so far, that I have to use a TFP401 from TI for the TMDS 
interface.

What DVI application are you developing?

regards,
Benjamin

Article: 83891
Subject: Re: true dual port memory v/s simple dual port memory
From: "Peter Alfke" <alfke@sbcglobal.net>
Date: 9 May 2005 07:32:43 -0700
Links: << >>  << T >>  << A >>
Well, let's not split hairs !
A dual-port memory has two independent access ports to a common storage
array.
Some dual-port memories can use one port only for write, the other one
only for read (sufficient for FIFOs),
Better designs have no such restriction, they allow read or write on
either or both ports. That's what all Xilinx BlockRAMs do. Such
memories are then referred to as "true dual-port memories".
Interestingly, Xilinx BlockRAMs perform a read operation even during a
write operation on the same port, and have a choice or
read-before-write or write-before-read. That just gives additional
flexibility.
Peter Alfke, Xilinx Applications.


Article: 83892
Subject: Re: Max7000ae and GCLRn
From: Mike Treseler <mike_treseler@comcast.net>
Date: Mon, 09 May 2005 07:51:55 -0700
Links: << >>  << T >>  << A >>
Laurent Gauch wrote:

> Can I re-route the GCLR signal (global signal) from an internal signal, 
> or is the GCLR really dedicated to the PIN GCLRn !

I had to use an external wire to
make such a connection.


          -- Mike Treseler

Article: 83893
Subject: Re: Multiple Virtex 2 Pro's, DCM and CLKIN_DIVIDE_BY_2
From: "johnp" <johnp3+nospam@probo.com>
Date: 9 May 2005 07:57:18 -0700
Links: << >>  << T >>  << A >>
Marc -

Thanks for your thoughts, I hope the Xilinx folks can add some more
insight on the topic.

John P


Article: 83894
Subject: dcm's for increasing clock speed
From: "geoffrey wall" <wallge@eng.fsu.edu>
Date: Mon, 9 May 2005 11:01:15 -0400
Links: << >>  << T >>  << A >>
when can dcm's be used (xilinx ise)
to improve clock speed of a given design?
suppose my design synthesizes at 75mhz
but i need my design to run at 150mhz
what can i do to improve performance
will dcm's work?
better pipelining?

any suggestions appreciated...

thanks

-- 
Geoffrey Wall
Masters Student in Electrical/Computer Engineering
Florida State University, FAMU/FSU College of Engineering
wallge@eng.fsu.edu
Cell Phone:
850.339.4157

ECE Machine Intelligence Lab
http://www.eng.fsu.edu/mil
MIL Office Phone:
850.410.6145

Center for Applied Vision and Imaging Science
http://cavis.fsu.edu/
CAVIS Office Phone:
850.645.2257 



Article: 83895
Subject: Re: dcm's for increasing clock speed
From: "John_H" <johnhandwork@mail.com>
Date: Mon, 09 May 2005 15:43:08 GMT
Links: << >>  << T >>  << A >>
The DCM can be used to change a clock frequency, not to alter the
synthesized speed of your design.  If your synthesizer suggests 75 MHz is
the best you can do even though you asked it for 150MHz, chances are your
place & route will give you something much closer to 75 MHz operation than
150.  Use the synthesis tools or - if they don't give good detail - the
place & route tools to tell you what your critical paths are.  It may be
that you have one congested part of your design that needs better pipelining
or a slightly different approach.  If the number of paths failing timing are
huge and mostly unrelated, you need to use a much faster speed grade part or
lower your expectations.

The DCM can be used as a clock doubler with input frequencies of 25 MHz or
better.  It can also be used in frequency synthesis mode with an input as
low as 1 MHz.

"geoffrey wall" <wallge@eng.fsu.edu> wrote in message
news:d5nu0a$kit$1@news.fsu.edu...
> when can dcm's be used (xilinx ise)
> to improve clock speed of a given design?
> suppose my design synthesizes at 75mhz
> but i need my design to run at 150mhz
> what can i do to improve performance
> will dcm's work?
> better pipelining?
>
> any suggestions appreciated...
>
> thanks
>
> -- 
> Geoffrey Wall
> Masters Student in Electrical/Computer Engineering
> Florida State University, FAMU/FSU College of Engineering
> wallge@eng.fsu.edu
> Cell Phone:
> 850.339.4157
>
> ECE Machine Intelligence Lab
> http://www.eng.fsu.edu/mil
> MIL Office Phone:
> 850.410.6145
>
> Center for Applied Vision and Imaging Science
> http://cavis.fsu.edu/
> CAVIS Office Phone:
> 850.645.2257
>
>



Article: 83896
Subject: Re: dcm's for increasing clock speed
From: "Peter Alfke" <peter@xilinx.com>
Date: 9 May 2005 09:25:37 -0700
Links: << >>  << T >>  << A >>
Geoffrey, the DCM just changes the clock frequency. It does not shorten
the delays in your design.
If you are limited to 75 MHz, there must be some strange excessively
long ( >12 ns) delays. Analyze your design, and see where these delays
originate. Pipelining is a good way to improve the max clock rate.
Once your design CAN run at 150 MHz, then it's time to double the clock
frequency, not before.
Peter Alfke


Article: 83897
Subject: Re: 8051 IP core
From: Ziggy <Ziggy@TheCentre.com>
Date: Mon, 09 May 2005 16:44:40 GMT
Links: << >>  << T >>  << A >>
CODE_IS_BAD wrote:
> hi all...
>   i would like to know wether anyone of you has used Oregano's free
> 8051 IP core. Also i read somewhere that this core cannot be
> synthesized on the xilinx or Quartus software. Is it true? Please let
> me know. 
> Thanx in advance
> 

Its VHDL so why couldnt it be?  Since it appears to be LGPL'd, just 
download it and try.. what do you have to lose?

Article: 83898
Subject: Altera Quartus Timing Models
From: alanmyler@yahoo.com
Date: 9 May 2005 10:03:06 -0700
Links: << >>  << T >>  << A >>
How do I perform a timing analysis using Quartus, with a worst case
temperature of less than the default for the device? For example, I
would like to check timing on a commercial grage-7 Cyclone part at 55C.


Many thanks,

Alan Myler


Article: 83899
Subject: Re: Simulating custom peripherals
From: "Joseph" <joeylrios@gmail.com>
Date: 9 May 2005 10:12:23 -0700
Links: << >>  << T >>  << A >>
Still unsure about those paths... can anyone offer some guidance?




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