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Peter Alfke wrote: > Geoffrey, the DCM just changes the clock frequency. It does not shorten > the delays in your design. > If you are limited to 75 MHz, there must be some strange excessively > long ( >12 ns) delays. Analyze your design, and see where these delays > originate. Pipelining is a good way to improve the max clock rate. > Once your design CAN run at 150 MHz, then it's time to double the clock > frequency, not before. > Peter Alfke Geoffrey, I think you are getting confused with the fact that a DCM can improve your I/O timing (but not frequency). By using a DCM you can phase shift to help meet Tco/Tsu requirements. As stated before, DCMs cannot increase max clock rate. If you don't know where to start, get a timing report and look at your critical paths. How many elements are in the path? Is your delay mostly IC delay or routing delay? If it is IC delay, you need to do some pipelining or redesign. If it is routing delay, you need to do some floorplanning. JohnArticle: 83901
Hi, I am doing stuff with Displays. The data rate is about 3 gigabits/s for the pixels. I am thinking about using the XUPV2P from digilent for this application. Since I would have to read and write at the same time, I would need a data rate of about 6 gigabits/s. Would it be possible with this board? http://www.digilentinc.com/info/XUPV2P.cfm regards, BenjaminArticle: 83902
GianniG, I know this doesn't really answer your question, but why are you dividing down a 500 MHz clock via the DCM to run at 250 MHz internal? Distributing a 500 MHz clock on the board wastes power not to mention the EMI issues. In addition, I would imagine the Xilinx DCM adds jitter via the divide? Why not use a 250 MHz reference, or better yet, multiply up a 125 MHz reference?. JohnArticle: 83903
Chapter 6: Simulation Model Generator of Embedded System Tools Reference Manual has all the info you need. http://www.xilinx.com/ise/embedded/est_rm.pdf Joseph wrote: > > Still unsure about those paths... can anyone offer some guidance?Article: 83904
Great! Thanks Paul. I am using EDK 6.3, so I will peruse the equivalent manual for that version (though at first glance, looks like 7.1 didn't change this section too much). I appreciate the response!Article: 83905
Piotr Wyderski wrote: > Rudolf Usselmann wrote: > >> check out the SN74TVC3010 from TI. It's a 10 channel voltage >> level converter. We use them to interface 5 Vdevices to 3.3V >> FPGAs. Works like a charm, and 133 MHz should be no sweat either ... >> >> DigiKey lists them for about $1.10 each (qtty 25) > > Thanks for this information, but these chips are very expensive > (relatively to their capabilities) -- LVC245 will do this task as well, > but its cost is 0.33$ (one unit quantity) or 0.25$ (25 units). > > Best regards > Piotr Wyderski I guess it all depends on your needs. If the 245 will do the trick than great ! If you need bidirectional signaling, than the 3010 might be a better option. The 3010 is more closer to a Quick-Switch architecture, the 245 is a buffer. I believe the 3010 does not add any delay (except for a tiny RC). Good Luck ! rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and SynthesisArticle: 83906
"John M" <statepenn99@gmail.com> wrote in message news:1115660749.715831.309210@o13g2000cwo.googlegroups.com... > GianniG, > > I know this doesn't really answer your question, but why are you > dividing down a 500 MHz clock via the DCM to run at 250 MHz internal? > Because that's what his ADC provides. 500MHz sampling rate. > > Distributing a 500 MHz clock on the board wastes power not to mention > the EMI issues. In addition, I would imagine the Xilinx DCM adds > jitter via the divide? Why not use a 250 MHz reference, or better yet, > multiply up a 125 MHz reference?. > Because he doesn't want a sampling rate of 125MHz, he wants 500MHz. He's doing exactly the right thing, maybe XAPP685 would help? Or XAPP268? Cheers, Syms.Article: 83907
Fred wrote: > I have a Maxplus design which is a year or more old which was compiled with > Maxplus. So far so good. I am required to make a small alteration. > > The licence has expired and Maxplus seems obsolete so my only option is to > download Quartus. Are you saying Altera cannot/willnot generate a non timebombed license for this ? I thought that nonsense was in the past, and that all tools vendors allowed changes to designs, if not whole new designs. Someone told me recently there was a legal precedent to this 'denial of design database' access aspect as well. > > Oh dear - I have never come across such a long winded process to convert > things to Quartus. > > After all the changes - Lo and behold it won't fit! and that is not as uncommon as we would hope. This, and other version control reasons, are the compelling reason for NOT timebombing EDA software. > > Is this called progress? > > What on earth is wrong with allowing the use of "outdated" software for > "outdated" designs? Nothing, and many do that. I thought Altera was one of them ? -jgArticle: 83908
Hendra wrote: > Hi folks, > Let's say I have a module with 2 inputs and 2 outputs > module1(input1, input2, output1, output2) > > Then I instantiate it like this > module1 my_module1 (.input1(input1), .input2(input2), > .output1(output1), .output2()); > > output2 is intentionally not used. How do I flag XST to suppress the > warning of not using output2? > > Hendra I'm not sure if this is one of the "low level" messages that XST will mute with the option, but I've found that turning on the environment variable XIL_XST_HIDEMESSAGES helps reduce warning messages considerably. Also if you're using the new software (7.1) there should be a "message manager" that lets you block specific messages by number. If you google this group for the environment variable mentioned above, you'll see a good reply on this. Good Luck, GaborArticle: 83909
Hi Fred, > The licence has expired and Maxplus seems obsolete so my only option is to > download Quartus. That's nonsense. If you have a valid subscription, Altera will still give you Maxplus features in the license. If the features were not in your latest license, you can simply request them. Best regards, BenArticle: 83910
> Clock delay is the time elapsed between sending the clock and its > arrival at a specific destination. So, this is outside the chip, that the clock is send? The delay is generated by the input buffer IBUFG? > Clock skew is the difference in arrival time at different destinations. Both internal and external - but if including an output-delay, this is both skew and delay? > Larger chips unavoidably have a longer clock delay. That's why DLLs, > DCMs and PLLs are so important, for they can reduce the clock delay to > zero, completely eliminating it. > Clock skew cannot be reduced by DLLs and PLLs, it can only be minimized > by careful clock routing structures and generous buffering. > Excessive clock skew can lead to hold-time problems or to reduced > performance, depending on the direction of the clock delay difference. > If the clock is delayed in the direction of the data flow, there is the > danger of hold-time violation. It the clock is delayed in the opposite > direction, max performance is reduced. > Modern FPGAs try to keep clock skew below a few hundred picoseconds. > Peter Alfke >Article: 83911
>From the FPGA point of view, everything is inside. If you want to talk about clock delay on the board, and clock skew on the board, the same rules apply. On the board, clocks are usually not re-buffered, and clock delay and skew are usually determined by the propagation velocity, which is roughly half the speed of light. Clock delay and skew are, therefore, of the same order od magnitude. On-chip, the clock goes through many buffering stages, which makes the delay long, but can keep the skew quite small, only a few % of the delay. IBUFG is just one contributor to clock delay, then there is the whole clock distribution network. Just remember: delay is from source to destination, skew is between destinations. Peter AlfkeArticle: 83912
Hi, In the datasheet I can find, that the board can run DDR ram at 133 MHz. Since the buswidth of the dimm-modules is 64 bit, my datarate is 2*133MHz*64Bit=17 gigabits/s. That would be enough. Am I right? regards, BenjaminArticle: 83913
Hello Dave--
The AccelChip DSP Synthesis product uses MATLAB M-files as its input
language. MATLAB in general can support multirate systems that are
integral fractions of a base rate -- alternatively you could say that
MATLAB can be used to model multi-rate systems with the restriction
that the clocks must be synchronous and integer multiples of each
other.
This can be accomplished with AccelChip using the streaming loop coding
style as shown below. In this example the design function
"design_func1" runs at the clock frequency, "design_func2" runs
at =BD the clock frequency, and "design_func2" runs at 1/3 the clock
frequency.
for n =3D 1:NUM_ITER
outdata3 =3D design_func1(indata); % freq
if mod(n,2) =3D 0
outdata2 =3D design_func2(indata); % freq / 2
end;
if mod(n,3) =3D 0
outdata1 =3D design_func3(indata); % freq / 3
end;
end;
With regard to Simulink -- it would be best to check with The MathWorks
but to my knowledge there is no need for any integral relationship
between rates in Simulink. If you have access to Simulink
documentation, just look for the section titled "Modeling and
Simulating Discrete Systems."
AccelChip can be used in combination with Xilinx System Generator for
DSP. Each subsystem can by synthesized with AccelChip and then
assembled in System Generator in order to achieve multiple rates.
Information regarding Xilinx's support for multiple clocks is described
at
http://www.xilinx.com/products/software/sysgen/app_docs/user_guide_Chapter_=
7_Section_2.htm
--Eric
Article: 83914Fred wrote: > I have a Maxplus design which is a year or more old which was compiled with > Maxplus. So far so good. I am required to make a small alteration. > > The licence has expired and Maxplus seems obsolete so my only option is to > download Quartus. > > Oh dear - I have never come across such a long winded process to convert > things to Quartus. > > After all the changes - Lo and behold it won't fit! > > Is this called progress? > > What on earth is wrong with allowing the use of "outdated" software for > "outdated" designs? Fred, And if you even have problems getting a new license for the MaxPlus, as others suggest.... An easy work around is to simply set back the date on your computer. Has it's problems, but works fine here for getting MaxPlus to run. (You won't want to have "email" simultaneously running on the same machine, for example.) You may want to get a copy of "touch" off the 'net to mess with source file time & dates to solve any file time dependency issues. Take a look at the license.dat file -- found it my Max II install directory, YMMV -- to see what the expiration date is to see how far back you need to push your clock.Article: 83915
On Mon, 09 May 2005 15:03:28 +0100, Fred wrote: > I have a Maxplus design which is a year or more old which was compiled with > Maxplus. So far so good. I am required to make a small alteration. > > The licence has expired and Maxplus seems obsolete so my only option is to > download Quartus. > A quick look at the Altera website gives links for downloading Maxplus and getting a license for it. They make it clear that they recommend moving to Q2, and that Maxplus is for legacy designs only, but they also make it simple to download and license. Did you actually try getting a new license, or did you just assume that "obsolete" means "unobtainable" ? http://www.altera.com/support/licensing/free_software/lic-max2baseline.jsp > Oh dear - I have never come across such a long winded process to convert > things to Quartus. > > After all the changes - Lo and behold it won't fit! > > Is this called progress? Given that Altera estimates a slight improvement on fitting on average when switching from Maxplus to Q2, I'd guess their support people would be interested in seeing the design and finding out what went wrong. > > What on earth is wrong with allowing the use of "outdated" software for > "outdated" designs?Article: 83916
Altera does not have any policy to stop users from using our legacy MAX+PLUS II software. We do encourgae users to take advantage of the latest Quartus II software performance and features but there is nothing to stop you from continuing to use MAX+PLUS II software. If you purchased an Altera subscription package your license should be perpetual i.e. it will work even after expiration. If you downloaded the free MAX+PLUS II BASELINE software the license will stop working after 6 months but you can simply request another free 6-month license extension on the Altera web site at http://www.altera.com/support/licensing/lic-index.html (2nd to last link under Legacy Software Licenses). I am sorry to hear you had an unpleasant experience trying to convert your MAX+PLUS II design into a Quartus II design. Altera has put a lot of effort into making this process as easy as possible and we have received a lot of positive feedback. We even went as far as including a MAX+PLUS II user interface option in the software and put a lot of effort into the "Convert MAX+PLUS II project..." feature to make the process as simple as possible. The Quartus II software on average offers 15% higher fmax performance and while consuming 5% fewer device resources when compared to MAX+PLUS II software. For more details refer to the Quartus II Handbook Chapter : Quartus II Design Flow for MAX+PLUS II Users at http://www.altera.com/literature/hb/qts/qts_qii51002.pdf. In the Quartus II software you might want to try changing the Analysis & Synthesis Optimization Technique setting from the default of "Speed" to "Area" to try to solve your fitting problem. I also encourage you to submit a service request at mysupport.altera.com so we can look into your problem specifically. I hope this helps. Regards, Rob Kruger Altera Software MarketingArticle: 83917
Why don't you take a look at the following 8051 from Hitech Global: http://www.hitechglobal.com/ipcores/dp8051.htm Their core is proven in multiple ASICs and FPGAsArticle: 83918
You may find the following DDR and DDR2 boards interesting: http://www.hitechglobal.com/xilinx/ml361.htm http://www.hitechglobal.com/ted/virtex4ddr.htm Regards,Article: 83919
What is the name of your company?Article: 83920
Hello, I want to configure a Spartan 3 with an ARM controller
comporting several GPIO pins (0-3,3v), from which I use 4 to drive the
JTAG controller of the FPGA.
I tried a basic configuration which only reads the IDCODE of the
device, but the value seen on TDO is not what is excepted, altough a
green led indicating that the device is properly configured becomes
active.
Moreover, I tried to configure the device with xsvf and it stops
rapidly with an error, because the TDO value mismatch.
Has anyone experienced these problems? Do we have to take care of other
things?
NOTE: to configure the device with JTAG, I reproduced the state machine
driven by TMS and TCK
I checked at the oscilloscope that the sequencing was correct
with respect to the state machine,
the only problem is the mismatch on TDO.
For the IDCODE = 01001, I ran first in SHIFT-IR state and
produced 1, 0, 0, 1, 0 on the TDI line
After that I ran in SHIFT-DR state, and clock TCK 32 times,
reading TDO at each edge
Thank you very much for your help, if anyone has a working detailed
example about this JTAG programming
Article: 83921Hi CPU, I have looked at those boards already. I find them a little bit expensive for me as student. However I think the XUPV2P board would work. I am just wondering why the XUPV2P board can only do ddr1 at 133 MHz... Does anybody know what the limiting factor is? regards, BenjaminArticle: 83922
it is not important!Article: 83923
it is not important! however,the ip quality is no problem!Article: 83924
Hello All:
I have a succes story about ISE 7.1i and Mandrake 10.1, with the
usual hassle of library linking and installing openmotif.
What I haven't been able to do is to use iMpact. The GUI loads
fine, but it seems unable to load the Xilinx cable drivers. I tried
to recompile the drivers, but that didn't work either. Has anyone
been able to use iMpact on a 2.6 Linux box? Or at a Linux box at
all?
Thanks!
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