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I have a Xilinx Spartan 3 board, and comes only with the parallel JTAG cable. My big problem is that any of my computers have parallel port, and I can't program it. As I work with a desktop and a laptop I had to discard buying a pci parallel card. I know that they have an usb and serial cable, but are very expensive and the shipping too. I'd like to know if there is any alternative, such as a homemade serial or usb cable, or if any of those parallel-to-usb adapters work with this. ThanksArticle: 83551
Rafa <rafaelgonzalez@ono.com> wrote: > I have a Xilinx Spartan 3 board, and comes only with the parallel JTAG > cable. My big problem is that any of my computers have parallel port, and I > can't program it. As I work with a desktop and a laptop I had to discard > buying a pci parallel card. I know that they have an usb and serial cable, > but are very expensive and the shipping too. I'd like to know if there is > any alternative, such as a homemade serial or usb cable, or if any of those > parallel-to-usb adapters work with this. A USB-to-Parallel Card with a FTDI Chip and a good driver should do the job... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 83552
Praveen,
The readback operation is supported in iMPACT only for PROMs and CPLDs
in Boundary-Scan and Desktop modes. Since iMPACT is a generic Xilinx
device configuration tool it indicates the complete set of operations
available for ALL devices but disables the ones that are not supported
for the selected device.
This is not unusual. For instance, in "Word" you may not be able to Cut
or Paste a protected document yet the operation is visible but disabled.
Praveen wrote:
> Thanks Glenn. Why list that option when we can't use it? ;). I read in
> the Impact help file that it can be used when using desktop
> configuration mode. But, I read elsewhere (in Xilinx help file) that
> suggested it can be used in SMAP and JTAG config modes. Doesn't make
> any sense.
>
--
*CAUTION:* Shameless self-promotion follows...
Article: 83553Xilinx told me that they are only selling version 7.1i EDK and 7.1i EDK will only work with ISE Foundation 7.1i. I have ISE 6.2i Foundation, so I am looking for a compatible version of EDK. ___________________________________________________________________ "Antti Lukats" <antti@openchip.org> wrote in message news:d55dc5$g45$00$1@news.t-online.com... > "Tod Adamson" <tod.adamson@starband.net> schrieb im Newsbeitrag > news:6fb14$427614e0$943fc5b9$2419@STARBAND.NET... > > Paying $200.00 > > > > mailto:tod.adamson@starband.net > > > > Why do you need 6.2 ? > Because the RoR team released a full key generator for it and there is no > keygen for newer releases? > Or is there some other reason for the 6.2 version ? > > Antti > > >Article: 83554
Oops. One correction. The reflection back toward the source is V/2, not -V/2. The polarity of the reflection only inverts if the wave encounters an impedance lower than its path. In this case, it's higher than the impedance of the transmission line. Bob "Bob" <nimby1_notspamm_@earthlink.net> wrote in message news:NlSce.3110$GQ5.2871@newsread1.news.pas.earthlink.net... > Roger, > > Driving with 75 ohms and terminating with a relatively high impedance, for > your case, is exactly what is needed for those LVTTL signals that need > their signal integrity maintained. For the video and sync signals, this is > important. > > If you generate a signal with a source impedance equal to characteristic > impedance of the associated transmission line (cable or trace), and then > terminate the end into a high impedance, then the end will receive a full > voltage (LVTTL level) swing -- and it will not have any signal-distorting > reflections contained in it. This technique is called "source > termination". > > For this "source termination" technique, what happens is that when you > drive a transmission line with a source of equal impedance value, the > signal is "launched" into the transmission line at half of its source > voltage (V/2). When the signal hits the end of the transmission line, the > signal will double in value (in the forward direction) -- thus > regenerating its original voltage level (V). A reflection heads back > toward the source at level -V/2 (note the minus sign). When it hits the > originating end's source impedance the reflected wave is completely > absorbed, so it doesn't reflect back to the destination end again. > > It is possible to end terminate LVTTL, but then it must be driven into the > transmission line at full V level. This implies that the source impedance > of the driver be very low. In practice, this is difficult to achieve. > That's why source termination is the most popular technique used for LVTTL > (and like) signals that need terminating. > > Bob > > > > "Roger" <enquiries@rwconcepts.co.uk> wrote in message > news:qBPce.8178$_s1.1100@newsfe6-gui.ntli.net... >> Falk, >> >> Looking into this a bit more, I've found monitor input impedances in the >> low KOhms range i.e TTL type inputs. >> >> Rog >> >> "Falk Brunner" <Falk.Brunner@gmx.de> wrote in message >> news:3dhq5tF6ttp5vU1@individual.net... >>> >>> "Roger" <enquiries@rwconcepts.co.uk> schrieb im Newsbeitrag >>> news:M_Nce.8045$_s1.3328@newsfe6-gui.ntli.net... >>> >>>> 1) Simply drive the signals from the FPGA (LVTTL signal level) and not >>> worry >>>> about it. >>>> 2) As above but put some protection diodes on the lines. >>>> 3) Put series resistors in the signals (I've seen this on an old FPGA >>>> board). >>> >>> Use series resistors of about 50 ohms. this will give you roughly 75 >>> Ohms >>> output impedance, well matched to the cable. >>> >>> Regards >>> Falk >>> >>> >>> >> >> > >Article: 83555
Ahh yes! sorry forgot about that dependancy yes! The ISE and EDK versions must match of course. Try contacting Memec, they sure have EDK 6.2 boxes maybe they will sell some eval board with bundled EDK and are willing to ship the old EDK with it. maybe the do it. they sure could. Antti "Tod Adamson" <tod.adamson@starband.net> schrieb im Newsbeitrag news:9c7db$42769668$943fc5b9$9344@STARBAND.NET... > Xilinx told me that they are only selling version 7.1i EDK and 7.1i EDK will > only work with ISE Foundation 7.1i. I have ISE 6.2i Foundation, so I am > looking for a compatible version of EDK. > ___________________________________________________________________ > > "Antti Lukats" <antti@openchip.org> wrote in message > news:d55dc5$g45$00$1@news.t-online.com... > > "Tod Adamson" <tod.adamson@starband.net> schrieb im Newsbeitrag > > news:6fb14$427614e0$943fc5b9$2419@STARBAND.NET... > > > Paying $200.00 > > > > > > mailto:tod.adamson@starband.net > > > > > > > Why do you need 6.2 ? > > Because the RoR team released a full key generator for it and there is no > > keygen for newer releases? > > Or is there some other reason for the 6.2 version ? > > > > Antti > > > > > > > >Article: 83556
Hi Neil, I think what you say is not entirely correct - impact doesnt do FPGA readback, not because it can not support it because Xilinx decided not to include this feature (available to the user). doing verify with FPGA in iMpact actually DOES readback of FPGA into internal buffer, then compares it to the .BIT file using the .MSK file and then trashes the internal readback. So the FPGA readback is internally used by impact, just the readback can not be saved to a file. sure the readback would not be the same as the programmed bitstream if the FPGA has been started, eg you would only get the proper .bit being read if the readback is done after JTAG configuration, but before jstart instruction, which I agree would be very rare case indeed. So I kind of understand why the FPGA readback is 'left out' from impact, but it doesnt mean its not possible. the usefullness of the readback is sure a question, there are only a few cases where it could be useful. Antti "Neil Glenn Jacobson" <n.e.i.l.j.a.c.o.b.s.o.n.a.t.x.i.l.i.n.x.c.o.m.> schrieb im Newsbeitrag news:d569t5$qaa2@cliff.xsj.xilinx.com... > Praveen, > > The readback operation is supported in iMPACT only for PROMs and CPLDs > in Boundary-Scan and Desktop modes. Since iMPACT is a generic Xilinx > device configuration tool it indicates the complete set of operations > available for ALL devices but disables the ones that are not supported > for the selected device. > > This is not unusual. For instance, in "Word" you may not be able to Cut > or Paste a protected document yet the operation is visible but disabled. > > > Praveen wrote: > > Thanks Glenn. Why list that option when we can't use it? ;). I read in > > the Impact help file that it can be used when using desktop > > configuration mode. But, I read elsewhere (in Xilinx help file) that > > suggested it can be used in SMAP and JTAG config modes. Doesn't make > > any sense. > > > > > -- > > *CAUTION:* Shameless self-promotion follows... >Article: 83557
> Do you have a Revision A USB Blaster (with standard ribbon cable to the PCB) > or a Revision B USB Blaster (with flex-pcb cable)? I have got a brand new Revision B USB Blaster with flex cable. MarkusArticle: 83558
Ben Twijnstra wrote: > Hi Markus, > > >>I have got problems using Signal Tap with the Altera USB Blaster >>download cable. >>Sometimes the data collected is correct, sometimes not, sometimes I get >>a jtag communication error. > > > Do you have a Revision A USB Blaster (with standard ribbon cable to the PCB) > or a Revision B USB Blaster (with flex-pcb cable)? > > The Rev A cables have signal integrity problems, so in that case, contact > your disti for a replacement if you such a cable. This should cost less > than a new cable. > > Before Dec 1st, 2004 Altera would have swapped your cable for shipping cost, > but now the offer has expired, unfortunately. > > Best regards, > > > > Ben Twijnstra > > Hi Ben, What is the difference between their original ribbon cable and their flex cable. Is the flex-cable soldered directly on the pcb of USB Byteblaster? How is this flex cable connected to the USB ByteBlaster? Thanks, LarryArticle: 83559
Hi again Peter Alfke wrote: > Preben. the extra delay is there to avoid a hold-tme requirement on the > input data. > Here is how: > When you use a global clock to clock in the data, that clock has to be > able to drive thousands of destinations. That means a "significant" > clock delay, more than the data delay to the input flip-flop. This clock-delay - is that what Xilinx ISE calls "clock skew"? Often there is "no" delay described unless you route the clock (not through global nets) And there is a but: the input flip-flop (IFF) is before this obtional delay element? Should the IFF be driven from another clock-source (some external)? > Whenever the clock delay is longer than the data delay, there is a > hold-time requirement: Assume a perfect flip-flop with zeo set-up time. > The data must then be held valid for some time after the clock. This is > ugly, since the data source sees no reason to keep the old data valid > after the new clock. Well, in my case, the A/D-converter holds the data valid 2ns after the clock, and only 3ns before the clock (running 100MHz). > Increasing the data delay to make it match the clock delay reduces the > hold-time requirement, hopefully to zero or a negative value. > The extra delay increases the set-up time, and thus reduces the max > clock rate a little. But it avoids failure when the data source isvery > fast. > > "Better to sacrifice some top speed, but avoid unreliable operation at > all (even slow) clock rates". > Peter Alfke, Xilinx Applications (from home) But this delay also delays the "valid-from" time, so if data isn't any longer valid after this extra delay (on the rising edge) then to use the extra delay-element will not help (make it worse) And I still need to know - why is the IFF so special? Isn't just a flip-flop without the use of the obtional delay-element? Thanks PrebenArticle: 83560
Hi Rafa, For your laptop, you can buy PCMCIA to Parallel port from Quatech www.quatech.com/catalog/parallel_pcmcia.php It's retail price is $129, perhaps you can buy it cheaper from Ebay. I use this device myself. I have mixed results with it. Sometimes it works right away, sometimes I have to retry it multiple times to make it works. You may have a better luck. USB to Parallel port adapter will NOT work! The software that is used to download the bitstream must see the parallel port at low hardware level. SPP100 works at low hardware level and fool the system to think that it has a real parallel port. The USB to Parallel port is for high level software emulation only. It only works for device like printer that has device driver. Your FPGA board doesn't have device driver. USB to Parallel port converter will NOT work with most FPGA board. HendraArticle: 83561
Hi, just wanted to check if somebody here had any luck programming the flash (AT45DB161B) on the Memec/Insigth development board. I have downloaded their Serial Flash Utility, as well, as Xilinx App note 800. Followed all instructions, and nothing ... I can download the bitfile directly in to the FPGA and it works. Trying to use the flash, I never get the "DONE" led lit up. I follow all instructions and configure all the jumpers as described. The programming of the FLASH seems to succeed - I get zero errors. I tried to also reprogramming the PLD, still nothing. We have several of these boards here, all behave the same way, so I doubt it's a bad board. Was anybody successful programming the FLASH on these boards ? Thanks, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and SynthesisArticle: 83562
thanks Benjamin.. i got the idea...this was what i was looking forArticle: 83563
Hi all, After synthesis if i get the following timing report then what will be my frequency of operation Minimum period: 11.536ns (Maximum Frequency: 86.685MHz) Minimum input arrival time before clock: 10.5 ns Maximum output required time before clock: 17.829ns Maximum combinational path delay: No path found now my maximum output required time before clock is more than the mimimum period. So will that limit my max operating freq?Article: 83564
Benjamin Menk=FCc wrote: > Hi, > > I am glad to tell you, that my LCD via LVDS works now :) However it > works only up to a lvds clock rate of about 200 MHz. > > I am not sure yet, if the 200 MHz limit originates from the fpga or the > cable. Has anybody put more than 200 MHz through a 0,4m SCSI cable? > > What is approximately the frequency limit of the (50 pin) scsi connector > on my board? (assuming my cable is perfect) > > regards, > Benjamin At 200 MHz I doubt your connector is affecting the signal significantly. We use National Channel-Link chipsets over multiple connectors at 595 Mb/s and cable lengths up to 10 meters. Also unless there is an impedance mismatch or significant line to line skew, your short cable should be no problem. Impedance mismatch and skew are usually larger on the printed circuit board rather than the cabling unless you take care during layout to control them. I would suspect a clock alignment issue at this low a frequency.Article: 83565
CODE_IS_BAD wrote: > Hi all, > After synthesis if i get the following timing report then what will > be my frequency of operation > > Minimum period: 11.536ns (Maximum Frequency: 86.685MHz) > Minimum input arrival time before clock: 10.5 ns > Maximum output required time before clock: 17.829ns > Maximum combinational path delay: No path found > > now my maximum output required time before clock is more than the > mimimum period. So will that limit my max operating freq? PUNEET, Gabor answered this question as well when you asked a slightly different question: http://groups-beta.google.com/groups?&q=%22Reports+Xilinx%22 In summary, "before clock" numbers are purely delay. To reduce delay times, put FF's in your IOB's. Have fun, MarcArticle: 83566
Umm - just a suggestion to fellow novice hardware designers: try another piece of hardware if your design seems perfect and it doesn't work. Damn board had a stuck-at-0 fault on one of the expansion header pins. Wahooo. Matter closed.Article: 83567
Phil Tomson wrote: > In article <4262f6e4$1@clear.net.nz>, > Jim Granville <no.spam@designtools.co.nz> wrote: > >Phil Tomson wrote: > >> In article <1113761592.889108.25670@f14g2000cwb.googlegroups.com>, > >> Marc Randolph <mrand@my-deja.com> wrote: > >>>Howdy Phil, > >>> > >>> It used to be. The GUI group appears to have gone to binary project > >>>file, at least on Windows version of ISE 7.1i - that move alone has > >>>almost driven me away from using the VHDL flow, back to using the edif > >>>flow. > >> > >> Bizarre. While the rest of the world is going to text formats like XML > >> (even Microsoft's Visual Studio.NET now store project files as editable > >> XML.) Xilinx decides to move to a binary format? Can anyone from Xilinx > >> comment on the rationale for doing this? > > > > There are solid version control, and user support, reasons for using > >an ASCII project file, that can be shared between GUI and command line > >flows. > > It also has operational benefits : You use the GUI for what it is good > >at ( one off set-up ), and the command line when speed and > >removal-of-operator-error are important. > > > > It can also save money - in this example, a user could set up in a > >borrowed Windows GUI, then run Linux command line, knowing the > >results will be (hopefully) the same. > > > > Where I have seen moves to binary project (and design!) files in the > >past, that has been driven by paranoia, and an effort to reduce > >portability to the "others". > > > > History shows that the minus side of this move, outweighed any plus > >side. Fundamental rule: Do not penalise the legitimate users! > > > > Seems to be two possible causes : > >a) A novice was put in charge of the project file decision > >and/or > >b) The paranoia quotient really is going up at Xilinx > > [see other posts ?] > > But what would they be paranoid about? Are they afraid that Altera will > create a Xilinx to Altera project converter or something? Even if they > did so, would it really be that big of a deal? The benefits of having a > user-editable ASCII project file (which you outline) seem to greatly > outweigh this risk. I'm guessing it wasn't paranoia, because they provide a way to import and export information to/from the new binary .ise file: http://support.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=21067 My WAG is that they mistakenly thought they needed to go binary to improve the speed of the GUI (which can be sluggish with large projects, even on a decently fast machine). So that would line up with cause (a) above. MarcArticle: 83568
Hi everyone, On a Spartan 3, I would like a single clock-signal to drive the inputs of all 4 DCM's. How would I get a clock-signal from the bottom to the top edge of the die, preferably with as little extra jitter as possible? I would like to use all 4 DCM's to shift the input signal by a different amount (say 45/4 = 11.25 degrees, ). But do I need to use a BUFG to 'feedback' these signals back to the DCM? There's no real 'delay' that I want to counter, I'm trying to (ab)use the FPGA as a phase discriminator. Secondly, I would like to have the four DCM outputs (0, 90, 180 and 270) each end up on the D-input of a flip-flop. Propagation delay on these paths should be small, but it is even more important that the signals arrive at their flip-flops simultaneously, or as much as possible. How can you enter that kind of constraint? There are not enough BUFG(MUX) resources to have all 4 I/Q-phase outputs of all 4 DCM's run over them. So I'm thinking of not using the BUFGMUX for that at all, but simply placing my flip-flops close to their associoated DCMs. Is there any information available on how I can connect to the DCM outputs (long-lines? hex-lines? neighbours?). What position relative to the DCM should the 4 FF be at for equal delay? When I've synthesized a design, I can see where it has placed all the resources. But is there any way to see how the actual routing of the signals over the FPGA is being done, what kind of lines are being used? That's enough questions for one posting, I hope someone out there is kind enough to help me along a bit. Regards, Paul Boven, PE1NUT Another FPGA-hobbyistArticle: 83569
Hi Larry, > What is the difference between their original ribbon cable and their > flex cable. Apparently, the original ribbon cable was unreliable when used at high speeds in noisy environments. Especially Signaltap was vulnerable to this. > Is the flex-cable soldered directly on the pcb of USB Byteblaster? > How is this flex cable connected to the USB ByteBlaster? Sorry, I understand your curiosity, but I'm not going to void the warranty on my cable to find out. My guess is that they use stubs to solder the cable to the PCB, but I could be completely off. Best regards, BenArticle: 83570
Marc Randolph wrote: > I'm guessing it wasn't paranoia, because they provide a way to import > and export information to/from the new binary .ise file: > > http://support.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=21067 > > My WAG is that they mistakenly thought they needed to go binary to > improve the speed of the GUI (which can be sluggish with large > projects, even on a decently fast machine). So that would line up with > cause (a) above. > > Marc "WAG" !!! Wow ! Last time I heard WAG was about 10+ years ago when I was working at Tandem. We also used EWAG (E=educated). Amazing, I almost forgot it ... ;*) Cheers, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and SynthesisArticle: 83571
Hi,
thanks for the answer Gabor. It seems that I have to do something inside
the fpga to get it faster.
I experimented a little bit further and found out, that my limit is at
240 MHz.
I am using a XC2VP4 with speedgrade 5.
The synthesize report says 240 MHz is the max clock for some nets, but
these (listed) nets are not important. The important lvds_in_x nets are
not listed there.
Is it usefull to put a bufg on every line that goes into the obufds? At
the moment these are just normal nets. (see the code attached).
At the moment I use a DCM to generate the 240 MHz.
Then I use a process, to divide the clock by 7 and form the asymmetric
clock. (see the code attached).
When I simulate my code in modelsim as Post-Map, everything looks okay.
But when I do Post-Place & Route the clock lvds channel and the data
channels are off by 1 lvds-clk cycle (I mean 1/240MHz), furthermore the
lvds-data-channel with the DTMG (Data Pixel Enable) doesn't go high (on
active) anymore, instead it becomes X for the high time. (However in
Hardware it works.)
My goal is about 350-400 MHz.
Maybe I should set some contraints, what would be a good starting point
for that?
I am happy about any hints that could help me.
Thanks in advance.
regards,
Benjamin
lvds3(6)<=DTMG;
lvds3(5)<=VSYNC;
lvds3(4)<=HSYNC;
-- generates serial data for one lvds-pair
lvds_1:process (lvds_tick)
begin
if rising_edge(lvds_tick) then
if load_lvds='1' then
reg1 <= lvds1;
else
reg1 <= reg1((5) downto 0) & '0';
end if;
end if;
lvds_1_in <= reg1(6);
end process;
lvds_clk_obufds : OBUFDS
port map (
O => lvds_clk_p,
OB => lvds_clk_n,
I => lvds_clk -- Buffer input
);
lvds_3_obufds : OBUFDS
port map (
O => lvds_3_out_p,
OB => lvds_3_out_n,
I => lvds_3_in -- Buffer input
);
-- lvds_tick is a clock at 7x pixel-clock (240 MHz)
-- lvds_clk is the clock for the lvds bus, same as pixel clock, but not
symmetric
-- like this for one pixel period: --___--
process (lvds_tick,screen_reset)
begin
if screen_reset='1' then
lvds_div<=0;
row_count <= 0;
col_count <= 0;
DTMG <= '1';
VSYNC <= '0';
HSYNC <= '0';
elsif rising_edge(lvds_tick) then
case lvds_div is
when 0 to 1 =>
lvds_clk <='1';
when 2 to 4=>
lvds_clk<='0';
when 5 =>
lvds_clk<='1';
------------
-- vsync and hsync stuff
case col_count is
when num_col -1 =>
DTMG <= '0';
if row_count = num_row -1 then
VSYNC<='1';
elsif row_count = num_row +1 then
VSYNC <='0';
end if;
HSYNC <= '1';
when num_col + 20 =>
HSYNC <= '0';
when others =>
end case;
if col_count = num_col + 60 then
col_count <= 0;
if row_count < num_row -1 then
DTMG<='1';
end if;
if row_count = num_row + 3 then
row_count <= 0;
DTMG<='1';
else
row_count <= row_count +1;
end if;
else
col_count <= col_count +1;
end if;
-------------
when 6 =>
lvds_div <= 0;
when others =>
end case;
if lvds_div < 6 then
lvds_div <= lvds_div +1;
end if;
end if;
end process;
Article: 83572Hi, I am using Synplify Pro for synthesis and Qurtus for remaining steps. In my design , I am using the filp-flop output from a counter as the clock for few modules. While running the fitter it says .... Info: Promoted cell "Quadrature:Quadrature_Map|Quad_Clk_Div:Quad_Clk_Div_Map|dclk_intl_Z" to global signal automatically But Later Timing Analizer says... Info: Detected ripple clock "Quadrature:Quadrature_Map|Quad_Clk_Div:Quad_Clk_Div_Map|dclk_intl_Z" as buffer Warning: Circuit may not operate. Detected 10 non-operational path(s) clocked by clock "Clk" with clock skew larger than data delay. See Compilation Report for details. 'dclk_intl' is a derived clock from 'Clk'. and in the timing report I get all the sequential elements driven by dclk_intl as having negative hold time (Clock skew is more then the data dealy) I searched this group and found related stuff. But that is for gated clock , and my clk source is from a sequential element.More over fitter promtes as making it a global signal but later I get a different message from timing analizer. Please suggest to fix this .... Thank you. -- Mohammed A Khader.Article: 83573
JD, I'll look into it. Austin JD_Design wrote: > I am doing some evaluation on a possible XC4VFX20 design and had a > question about the Xilinx Power Calculator on the web. This design is > over industrial temperature, and when I change the temperature in the > calculator some of the power values don't change. For example, > changing the temperature alone (from 25 to 85 degrees C) causes the > VCCINT to go from 88mW to 226mW (as is expected) but VCCAUX stays at > 88mW. The PowerPC cores do the same thing (no change over temp). Any > experiences with the accuracy of this are appreciated, as I need to > size this for power. Even though the PowerPC is a hard core it should > still vary at least somewhat over temperature, correct? I assumed the > same for VCCAUX as well. > > Any previous experience and knowledge appreciated. > > Thanks, > > Jim Davis > JDDC >Article: 83574
Probably most people upgraded their 6.2 ISE to 7.1 and therefore can not sell you the old 6.2 without loosing the update. But someone could sell you his old version including update for the price of a new ISE7.1 and than purchase a 7.1 for himself. A better solution that also addresses the problem of XC4K support would be that Xilinx added a note to the license agreement that ownership of a license of ISE also allows one to install any number of older versions of the software on the same machine. (Getting access to the installation media isn't difficult, just ask your nearest university) Xilinx allready more or less implies that this is allowed by providing instructions for how to run multiple versions of ISE after a upgrade. Usually after an upgrade you still only hold a license for one install of the software, not multiple. Kolja Sulimma Tod Adamson wrote: > Xilinx told me that they are only selling version 7.1i EDK and 7.1i EDK will > only work with ISE Foundation 7.1i. I have ISE 6.2i Foundation, so I am > looking for a compatible version of EDK. > ____________________________________________
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