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I have to agree. Jesse, Paul, Vaughn, and Subrotta (I'm sure there's more) have responded quickly to things with Nios, Quartus, etc, from my point of view. Take a look at how often, ie., Subrotto has responded to problem designs in the past. I'm very thankful for their presence. As for getting to people inside Altera, develop a good relationship with the FAE and let them do that for you - it's worked for me. -- Pete > Rudi, > > I don't think this point is quite fair. Besides Paul there are myself > (Nios/embedded questions here are what I answer), Vaughn, and others. > On the embedded side a lot of people have moved over to asking > questions on a new webaite (www.niosforum.com) where there area Altera > people from the engineering/apps/marketing teams who respond quite > regularly. > > I won't comment on the original FPGA Journal article, other than to say > that I enjoyed it :) On the other hand, one should realize that X has > been playing the same marketing games for years now without a peep from > the press... > > Jesse Kempa > AlteraArticle: 84126
Hi, The B5-X300 Spartan2E board takes the approach of bringing the the FPGA I/Os out to headers. http://www.burched.biz/b5x300.html Not much else on the board, except power supply, a header programmable oscillator (1 to 100MHz), one test LED, and one test pushbutton switch. It is a board that you can build into equipment, rather than just use for demo. Best regards, Tony Burch BurchED, Making FPGA Prototyping Easy, http://www.BurchED.biz BurchED FPGA boards... * Largest number of accessible I/O pins. * Widest selection of expansion modules. * Fast and economical prototyping of professional designs. * Ideal for advanced-student projects. "jgknowla1" <nospam@phyro.com> wrote in message news:1115906537.311753.114370@g49g2000cwa.googlegroups.com... > Gabor, > > Thanks for the ideas... I was originally not thinking deep enough and > planning on just getting the chip running, then breaking out the IOs to > headers. Of course that doesn't take into account what IO type I would > then want to use and any possible level converters. I guess that's why > there's a market for demo boards, afterall. > > thanks, > Josh >Article: 84127
Hello, in my actual design im using a few picoblazes. Now I wonder if it is possible to update the code in the bitstream without a new implementation run like it is possible with the microcblaze. I checked data2bram but it allows only an update of 16 Bit wide Brams, not the necessary 18 Bit. Thanks, MichaelArticle: 84128
Giox wrote: > I would like to implement a multiplier with word size equal to 16. > However I read some book, for example "Computer Arithmetic" by Parhami, > and I found only high radix multiplier radix-8 and radix-16 at maximum. Radix and word size are two different things. Radix describes the unit operation that the larger multiplier is made out of. A higher radix allows a faster multiplier using more logic. -- glenArticle: 84129
Athena wrote: > I want to do float computing with xilinx FPGA, but I don't know how. > In order to add libm.a into the project, I think you should explain more about what you are trying to do. In general, floating point is pretty inefficient in an FPGA, but it depends a lot on what you are trying to do. -- glenArticle: 84130
Stanley wrote: > Dear Gurus, > I've few concerns from the given function. > 1. Do I necessary have to re-implement the data-type from float/double > to integers? I found it's difficult to re-scale the coefficients into > integers for this particular polynomial, since the range is fall > between 35333307.73 and 0.014726741 (to keep the precision at least 7 > decimal places), and the integer for my machine can only support > 4bytes. How will the typical designer do to overcome this problem? Please explain what you are really trying to do. One reason to use FPGA instead of a more traditional processor is speed. An FPGA can do many additions, and with newer models, many multiplications at the same time. If your algorithm can be parallelized that way it can run much faster in an FPGA. For this to make sense, though, there must be a real need for the speed, especially when floating point is involved. In an FPGA the barrel shifters required to do floating point addition (pre and post normalization) is much larger than the logic that does the actual addition. For multiply it isn't so bad with integer multiply hardware. Division is a lot of work, fixed or floating point. If you don't need speed then it isn't so hard to do in an FPGA, but it is even easier in a normal processor. For your problem it might be that 60 bit fixed point will do. It might also be that you can use fixed point with the binary point at different positions in different parts of the calculation. To really answer the question the real goals of the project need to be considered, including cost, development time, and speed of the final product. (Both delay and throughput.) -- glenArticle: 84131
Joseph, I just saw a presentation that shows that V4 is faster on all interconnet paths (by as much as 500 ps for long paths) except the immediate neighbor paths, where we are just ever to slightly slower than S2 neighbor paths. I also saw LUT comparisons, which took 8 slides, with animations, as comparing the 4LUTs to the ALM-LUT is not trivial: you have to look at each and every input to output delay. And then you have to make a guess as to how your logic will get synthesized. Yes, we are faster for 4 LUT (most inputs), and they are faaster for wider functions (but not all inputs). For example: S2 4LUT input delays to output (in order): 155ps, 382ps, 360ps, 275ps. V4 4LUT: 165ps, 165ps, 165ps, 165ps. (fastest speed grades, both companies). Then there is the interconnect. V4 is 500 ps faster for full chip routes, 400 ps faster for 1/2 chip routes, 100-200 ps faster for a few CLBs, LABs, and 100-200ps for neighbor routes. Some very short routes are 30ps better in S2. Below 32 bits, S2 is slightly better for an adder, and over 32 bits, V4 is better. Same for cary chain, where S2 is ~ 200 ps better at ~ 16 bits, and V4 is >500ps better at 48 bits, and longer carry chains (equal at 24 bits). In our suite of test designs, we come out ~9% faster (on average) with a +/- 4% error margin. Of course some designs will be faster than that, and some slower, too. We generally favor wider arithemetic, and pipelining, where S2 favors empty designs, and small arithemetic functions. We tend to excell when the design gets full, and complex (like it does at the end of your project!). BRAM functionality depends a lot on the use of registers, as use of the fabric registers really slows things down (and takes more power) than using the registers built into the BRAM. Of course, anythign you can direct into the DSP48s will just scream, and outperform anything S2 has. I think that the newsgroup here will basically tell you to try a design in both architectures, and play with the constraints to see how well it does. Or, what I prefer, is to contact the FAEs of the respective companies, and ask them to show you how your design will perform (let them drive the tools). Or, do both. AustinArticle: 84132
Thomas Womack wrote: > Paul Lee <paul.sw.lee@gmail.com> wrote: >>I was wondering what is the best way of finding the median of a >>floating point array in hardware. I am currently thinking of using a >>bit voter scheme for fixed point but I don't think this will be able >>to differentiate the exponent in the floating point. Would I have to >>adopt a sorting method for floating? Why do you want to do this in hardware? The answer to your question depends much on why. How many numbers might you have, how fast do they come in, and how fast do you need the result? How many times will you be doing this? Otherwise... > Floating point numbers (at least in IEEE representation) sort in the > same way as integers; any FP number with exponent e+1 is larger than > any FP number with exponent e. Just think of them as 32- or 64-bit > numbers, and use the integer median algorithm. As long as they all have the same sign. If you convert the entire word to twos complement, then they will sort independent of sign. That is, if the sign bit is a '1' complement the rest of the bits and add one. (The PDP-10 does that, though it isn't IEEE.) Well, you need to do a twos complement comparison, or just invert the sign bit first. -- glenArticle: 84133
Austin Lesea wrote: > Joseph, > > I just saw a presentation that shows that V4 is faster on all > interconnet paths (by as much as 500 ps for long paths) except the > immediate neighbor paths, where we are just ever to slightly slower than > S2 neighbor paths. ...(lots of numbers deleted)... Without detailing what you're comparing (ie., which device at which speed grade) none of this is meaningful. Tommy -- not affiliated with either fighting bulls.Article: 84134
jgknowla1 wrote: > Greetings, > > I have one of the Digilent spartan-3 starter boards, and have been > browsing this newsgroup for a while. I think I may be ready to design > a small board of my own. I can't seem to find a minimum circuit to get > the chip running. I'm thinking really simple here...no external RAM, > etc. Just a JTAG interface, clock, and reasonable power/ground methods > (decoupling, etc). > > Has anyone seen something like this before? > > thanks, > the newcomer > http://www.trenz-electronic.de has about as minimal of a board you can get.. Might be worth looking at for your ideas of where to startArticle: 84135
Tommy, I thought I was clear, fastest speed grade, S2 and V4. Austin Tommy Thorn wrote: > Austin Lesea wrote: > >> Joseph, >> >> I just saw a presentation that shows that V4 is faster on all >> interconnet paths (by as much as 500 ps for long paths) except the >> immediate neighbor paths, where we are just ever to slightly slower >> than S2 neighbor paths. > > > ...(lots of numbers deleted)... > > Without detailing what you're comparing (ie., which device at which > speed grade) none of this is meaningful. > > Tommy -- not affiliated with either fighting bulls.Article: 84136
Hi André, The title talks about "Input max delay", while the help description cited is that for a delay chain setting: "Input delay from pin to input register". The two are different, and guide the Quartus tool in a different manner. "Input max delay" is a timing constraint, while the "Input delay from pin to input register"other one is a fitter setting to overwrite an delay chain in the I/O. Quartus is very good at automatically selecting the best delay, so there is really no need to use the "Input delay from pin to input register". Instead, you can use either the "Input max delay / input min delay" or "tsu/th" timing constraint to specify your requirements, and Quartus will do a good job at selecting the best settings (in a timing driven way). Hope this helps. Subroto Datta Altera Corp. <ALuPin@web.de> wrote in message news:1115895511.549661.165660@g44g2000cwa.googlegroups.com... Hi, in the Quartus Help I have found the following: #Input Delay from Pin to Input Register logic option # #A logic option that specifies the propagation delay from an input pin #to the data input of the input register implemented in the I/O cell #associated with the pin. This is an advanced option that should be #used only after you have compiled a project, checked the I/O timing, #and determined that the timing is unsatisfactory. For detailed #information on how to use this option, refer to the data sheet for #the device family. # #This option is useful for fine-tuning a design's I/O timing and meet #tSU/tH requirements. # #Legal integer values range from 0 through 63. # #This option is ignored if it is applied to anything other than an #input or bidirectional pin. This option can be set in the Assignment #Editor (Assignments menu). This option is available for CycloneT II #and Stratix® II devices. So it seems that this feature is not available for Cyclone devices? Is there some alternative method for Cyclone? Rgds AndréArticle: 84137
Austin Lesea wrote: <snip> > For example: S2 4LUT input delays to output (in order): 155ps, 382ps, > 360ps, 275ps. V4 4LUT: 165ps, 165ps, 165ps, 165ps. (fastest speed > grades, both companies). Since this is side-by-side, I was wondering why Xilinx spec all paths the same. Is that actually the worst path, and then the SW is free to use any path ? [but your physical speed margin might change, on a re-route] Or is there really such a difference in the implementation that Xilinx's end up precisely identical, and Altera's vary over 2:1 ? -jgArticle: 84138
Peter Sommerfeld wrote: > I have to agree. Jesse, Paul, Vaughn, and Subrotta (I'm sure there's > more) have responded quickly to things with Nios, Quartus, etc, from my > point of view. Take a look at how often, ie., Subrotto has responded to > problem designs in the past. I'm very thankful for their presence. > > As for getting to people inside Altera, develop a good relationship > with the FAE and let them do that for you - it's worked for me. > > -- Pete > >> Rudi, >> >> I don't think this point is quite fair. Besides Paul there are myself >> (Nios/embedded questions here are what I answer), Vaughn, and others. >> On the embedded side a lot of people have moved over to asking >> questions on a new webaite (www.niosforum.com) where there area > Altera >> people from the engineering/apps/marketing teams who respond quite >> regularly. >> >> I won't comment on the original FPGA Journal article, other than to > say >> that I enjoyed it :) On the other hand, one should realize that X has >> been playing the same marketing games for years now without a peep > from >> the press... >> >> Jesse Kempa >> Altera Jesse, Pete, I did not intend to offend anybody. I am sure there are many great guys here from both camps. My point was that I seem more tough discussions in the Xilinx camp. I don't know what the cause for that is. Are Altera user not doing any (b)leading edge designs ? Are they not using any fancy features of the devices, are they not pushing the devices to the limit ? I don't know. It's just my personal observation ... Regards, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and SynthesisArticle: 84139
Where can I find this assignment type "Input max delay / input min delay" in the Assignment Editor? Rgds Andr=E9 Subroto Datta schrieb: > Hi Andr=E9, > > The title talks about "Input max delay", while the help description cited is > that for a delay chain setting: "Input delay from pin to input register". > > The two are different, and guide the Quartus tool in a different manner. > "Input max delay" is a timing constraint, while the "Input delay from pin to > input register"other one is a fitter setting to overwrite an delay chain in > the I/O. > > Quartus is very good at automatically selecting the best delay, so there is > really no need to use the "Input delay from pin to input register". Instead, > you can use either the "Input max delay / input min delay" or "tsu/th" > timing constraint to specify your requirements, and Quartus will do a good > job at selecting the best settings (in a timing driven way). > > Hope this helps. > > Subroto Datta > Altera Corp. > > > > <ALuPin@web.de> wrote in message > news:1115895511.549661.165660@g44g2000cwa.googlegroups.com... > Hi, > > in the Quartus Help I have found the following: > > > #Input Delay from Pin to Input Register logic option > # > #A logic option that specifies the propagation delay from an input pin > #to the data input of the input register implemented in the I/O cell > #associated with the pin. This is an advanced option that should be > #used only after you have compiled a project, checked the I/O timing, > #and determined that the timing is unsatisfactory. For detailed > #information on how to use this option, refer to the data sheet for > #the device family. > # > #This option is useful for fine-tuning a design's I/O timing and meet > #tSU/tH requirements. > # > #Legal integer values range from 0 through 63. > # > #This option is ignored if it is applied to anything other than an > #input or bidirectional pin. This option can be set in the Assignment > #Editor (Assignments menu). This option is available for CycloneT II > #and Stratix=AE II devices. > > So it seems that this feature is not available for Cyclone devices? > Is there some alternative method for Cyclone? >=20 > Rgds > Andr=E9Article: 84140
Hi, Does this "Free ISE WebPACK 7.1i" for linux work with any distribution other than Red Hat Enterprise Linux 3 ? I tried to install this under Fedora Core 3 / Debian and installation didn't succeed. Looks like the installer is linked against libwiclient.so, libcommdlg50.so .... libodbc50.so etc, which are not there on the system. Does anyone know which package provides these ? Would like to know which packages are required to install this software. (An opensource Webpack will be a lot better idea :-)) Thanks, GeorgeArticle: 84141
Thanks for everyone's help! I have resolved the problem.In my program, i have inserted the "print("start receive");" sentence, but now i find this statement wastes so much time that i lost many characters in UART16550 FIFO, so i can receive all data wheni delete the statement,thanks for everyone's help!!!!
Article: 84142I doubt if anyone has seen a similar problem. You wanna know why? Because no one actually bought and used the Excalibur chip. I am amazed to see a post about it. Just wanted to let you know it is probably the biggest failed FPGA product in recent history and maybe in all of FPGA history. It probably cost around $100 million to develop. Earned around $0 million in sales. Do yourself a favor and go get yourself a Virtex 4 FX development kit. PowerPC with embedded 10/100/1G Emacs. Now that is a device people will use in large numbers. bta3 wrote: > BlankHi, > I seem to have a problem talking to a MAC chip that is connected as a > memory mapped device on the EBI bus of an EPXA1-672 chip (EBI2 for CS, no > split reads and no prefetch). EBI1 is connected to a flash chip. I am using > the GNU toolset to develop code and no OS (as yet). > > Apparently, if I read a single register (in my code), a series of 16 read > accesses are made by the chip and cached. Subsequent reads do not access the > MAC, rather return values from the cache - I do not see any CS transitions > at the chip pins. The write operations function perfectly well if I do not > perform a read - one CS for every write request. Once a read is performed, > the writes also cease to be "executed" and change the register value in the > cache only. > > Has anyone seen a similar problem? The Altera folks have not responded to > my trouble tickets - their support is not what it used to be. > > Thanks, bta3Article: 84143
I have receive large character data from RS232, i want to save it in the SDRAM memory, i find the SDRAM is 8M*32, but the character is 8bits,not 32bits, if i write a character into an Unit of SDRAM, next 24bits memory is wasted, and i find some data is not correct, how can i use the SDRAM correctly and efficiently?Article: 84144
On Fri, 13 May 2005 13:10:33 +0700, Rudolf Usselmann wrote: > Peter Sommerfeld wrote: > >> I have to agree. Jesse, Paul, Vaughn, and Subrotta (I'm sure there's >> more) have responded quickly to things with Nios, Quartus, etc, from my >> point of view. Take a look at how often, ie., Subrotto has responded to >> problem designs in the past. I'm very thankful for their presence. >> >> As for getting to people inside Altera, develop a good relationship >> with the FAE and let them do that for you - it's worked for me. >> >> -- Pete >> >>> Rudi, >>> >>> I don't think this point is quite fair. Besides Paul there are myself >>> (Nios/embedded questions here are what I answer), Vaughn, and others. >>> On the embedded side a lot of people have moved over to asking >>> questions on a new webaite (www.niosforum.com) where there area >> Altera >>> people from the engineering/apps/marketing teams who respond quite >>> regularly. >>> >>> I won't comment on the original FPGA Journal article, other than to >> say >>> that I enjoyed it :) On the other hand, one should realize that X has >>> been playing the same marketing games for years now without a peep >> from >>> the press... >>> >>> Jesse Kempa >>> Altera > > > > Jesse, Pete, > > I did not intend to offend anybody. I am sure there are many > great guys here from both camps. My point was that I seem more > tough discussions in the Xilinx camp. > > I don't know what the cause for that is. Are Altera user not > doing any (b)leading edge designs ? Are they not using any > fancy features of the devices, are they not pushing the devices > to the limit ? I don't know. It's just my personal observation ... > > Regards, > rudi It might also be at least partly to do with the type of people representing Xilinx and Altera in this newsgroup. I get the impression that certain Xilinx posters provoke discussions and arguements by their enthusiastic or agressive (depending on your viewpoint) promotion of Xilinx parts, while most Altera posters seem quieter, and will answer when asked. Both camps appear to have knowledgable and helpful posters, although obviously you have to remember that sometimes their facts and figures are seen from a biased viewpoint. Having not used Xilinx devices, I've had no occasion to test Xilinx support - but when I asked for help here for Altera devices, I got general information here, more specific help in private emails, contact from my FAE (obviously Altera people work closely with their FAEs), and in general a lot of interesting and useful information. The problem turned out to be a typo in my code with bizarre side effects, but I was very happy with the support I got.Article: 84145
Hi
I have a problem in simulating a memory block (VHDL-written control
unit and BlockRAM for Virtex II). BRAM is instantiated as shown below.
The problem for me is that the VHDL description of BRAM is not
available. The question is that
- Can we simulate it in modelsim SE 6.0c?
- In case only the BRAM-instantiation is enough to simulate and
synthesize, is it meaning that simulator/synthesis tool(XST) has the
library?
Thankyou in advance for comment
---------------------------------------------------------
.
.
.
component RAMB16_S9
port ( DI : in STD_LOGIC_VECTOR (7 downto 0);
DIP : in STD_LOGIC_VECTOR (0 downto 0);
EN : in STD_ULOGIC;
WE : in STD_ULOGIC;
SSR : in STD_ULOGIC;
CLK : in STD_ULOGIC;
ADDR : in STD_LOGIC_VECTOR (10 downto 0);
DO : out STD_LOGIC_VECTOR (7 downto 0);
DOP : out STD_LOGIC_VECTOR (0 downto 0));
end component;
.
.
.
-- 1st RAMB16_S9
port map(WE=>we, EN=>en, DIP=>dip, SSR=>ssr, CLK=>clk, ADDR=>addr,
DI=>din(7 downto 0), DO=>dout(7 downto 0));
-- 2nd RAMB16_S9
port map(WE=>we, EN=>en, DIP=>dip, SSR=>ssr, CLK=>clk, ADDR=>addr,
DI=>din(15 downto 8), DO=>dout(15 downto 8));
-------------------------------------------------------------
Article: 84146Hi, simulation of Xilinx blockram is no problem. You only need the Xilinx unisim library for this (\Xilinx\vhdl\src\unisims\ ) => You must compile this library with modelsim and include to your project.Article: 84147
either a) use 4 chip or bank selects as some SDRAM's have. b) use a read-modify-write cycle "ARRON" <mlpei279@gmail.com> wrote in message news:ee8e3ab.-1@webx.sUN8CHnE... > I have receive large character data from RS232, i want to save it in the SDRAM memory, i find the SDRAM is 8M*32, but the character is 8bits,not 32bits, if i write a character into an Unit of SDRAM, next 24bits memory is wasted, and i find some data is not correct, how can i use the SDRAM correctly and efficiently?Article: 84148
Geogle <georgevarughese@indiatimes.com> wrote: > Hi, > Does this "Free ISE WebPACK 7.1i" for linux work > with any distribution other than Red Hat Enterprise Linux 3 ? > I tried to install this under Fedora Core 3 / Debian and > installation didn't succeed. Looks like the installer is > linked against libwiclient.so, libcommdlg50.so .... > libodbc50.so etc, which are not there on the system. > Does anyone know which package provides these ? The webpac installer is in charge to install them. They are found in ../bin/lin > Would like to know which packages are required to install > this software. > (An opensource Webpack will be a lot better idea :-)) -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 84149
Hi, I have made a bootloader which runs from BRAM on a PPC. Now I want to download an application into external RAM and execute it. If I build my application and convert the .elf file into a binary file, the result is a 2 GB binairy file. This is because my external RAM starts at 0x80000000 and the startup up code contains a section called boot0, which is laid at 0xFFFFFFDC. AFAIK, the boot0 section contains a jump to my application (0x80000000). But, I think, the boot0 section is not needed. At startup the boot0 section (in BRAM) contains a jump to my bootloader program and I don't want to overwrite it. How can I create a .elf file (or .bin file) without the boot0 section (but with initialisation/startup code)? In that case I can simply download my application through the bootloader into external RAM and jump to it. TIA, Frank
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