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Hi Everyone,
Since, despite previously voicing opinions on the topic, Austin does not seem
to be willing/interested to reply to my question, I would like to extend it to
anyone at Xilinx, or in general anyone who might know the answer: Can anyone
explain the results that are described in my previous posting in this thread?
Thanks in advance,
Ljubisa Bajic
ATI Technologies
eternal_nan@yahoo.com (Ljubisa Bajic) wrote in message news:<9b0afb2c.0504271500.4dfc5a24@posting.google.com>...
> Hi Austin,
>
> I also tried using the power estimation tool on Xilinx' web site and
> ran into pretty much the same results as Paul described earlier in the
> thread.
> Specifically, I tried >10 different configurations with a V4 LX80
> part; varying the following parameters (all "utilization" parameters
> were between low and medium values, Vccint was varied between 1.1V and
> 1.3V):
>
> Vccint
> CLB Usage
> FIFO Usage
> RAM usage
> DSP block usage
> Amount of air flow
>
> What I found is that for every "configuration" I tried the ratio of
> Vccint_new/Vccint_old was almost exactly equal (equal at least to the
> precision of a mW) to the ratio of Power_new/Power_old (where the
> Vccint
> values are between 1.1 and 1.3 and Power_{new,old} refers to only the
> power
> reported as dissipated on the Vccint rail.
>
> Could you please shed some light on the behaviour described above? Are
> Paul and I simply doing something completely wrong with the power
> estimator?
>
> In order to avoid coming off as simple minded, I will refrain from any
> speculation on my side.
>
> Thanks,
> Ljubisa Bajic
> ATI Technologies
>
>
> Austin Lesea <austin@xilinx.com> wrote in message news:<d4mfgm$7d53@cliff.xsj.xilinx.com>...
> > Paul,
> >
> > It does change (with V), as is shown by the predictor.
> >
> > And yes, we do use Vccint. We also use Vccaux.
> >
> > Nothing is ever as simple as it first seems.
> >
> > The devil is in the details, and telling you how it works would just
> > allow you to copy it, and improve your own estimator.
> >
> > Austin
> >
> > Paul Leventis wrote:
> >
> > > Hi Austin,
> > >
> > >
> > >>Since we power the pass gates from Vccaux through a band gap
> > >
> > > referenced
> > >
> > >>supply for the entire interconnect, many simple minded formulas that
> > >
> > > you
> > >
> > >>may come up with will not apply.
> > >
> > >
> > > Excuse my simple-mindedness, but I am having trouble understanding.
> > > You have no circuitry powered off the actual VccInt rail? Your routing
> > > buffers, LUTs, DSPs, RAMs and other hard-IP blocks do not use VccInt
> > > but rather run off the regulated VccAux-driven supply?
> > >
> > > Yes, I will concur that simple rules-of-thumb are never quite true in
> > > practice, and depend on exact circuits used. But are you suggesting
> > > that your supply current doesn't change with voltage? At all?
> > >
> > > Paul Leventis
> > > Altera Corp.
> > >
Article: 83426Under the sim tab in the workspace box, a complete design hierarchy is present. You can browse through all of your sub-modules. If you want to add all signals for a sub-module into the wave you can simply drag the sub module. Otherwise, you can click on the sub-module and lookin the objects pane. It has all of the signals in that module. You can select all of the signals you want to add by ctrl+clicking each of them, then you can add them to the wave by going to add menu -> wave -> selected signals. Also, you can drag the signals from the objects pane straight to the wave window. Yes you can save the waveform settings. You click the save button while the waveform pane is selected. It saves to a .do file. A .do file is just a script file that you can run when you want to restore those settings. It's not automatic, but next time you load the project you can type in the console do wave.do (or whatever you saved it as). No you don't have to close Modelsim everytime you resynthesize. You just need to recompile (by going to the project tab of the workspace and right clicking and choosing the appropriate compile command) and then restart the simulation. I hope that helped (though it appears other people have replied already) -ArlenArticle: 83427
Does anyone know if Xilinx, Altera, or some of the others hold key patents in fpga architectures that barr entry of some of the traditional microprocessor companies. I have seen that ST has dabbled in embedded in FPGAs in the last few years, and have come up with their own proprietary embedded FPGA architecture. However, in the end they have abandonded it for 3rd party architectures. Does anyone have an idea why? AndreasArticle: 83428
Hi, my problem is that behavior simulation doesnt work somehow. Therefore I have to do post-translate simulation. However during translation XST doesnt keep the net-names, so its a little bit hard to find the right net in modelsim, I don't even know which net to take. Do I have to pick the right net using fpga-editor? Or how do I get an overview over the new nets? regards, BenjaminArticle: 83429
I am currently doing work on a small board with a FPGA and DSP. I have been planning to use the Xilinx XC3S1000-4FT256C , but Nuhorizons doesn't seem too interested in selling me 2 for a prototype. Where else could I find these? The Xilinx online store only has parts up to the XC3S400. I have checked digikey, but they are a few years behind on the Xilinx parts. I may have to consider changing to Altera since Digikey seems to stock them. I really don't want to do this, but if forced by unavailability of parts I will have to. Darrell Harmon http://dlharmon.comArticle: 83430
Well Bryan, if you have done it already, then you can easily answer my challenge: Assume a 1K-address deep FIFO implemented in a dual-ported RAM. Design only the EMPTY-flag detect circuit that operates reliably at totally asynchronous write and read clock frequencies of >300 MHz, and show a test circuit that proves that this operation is reliable. (Hint: The Virtex-4 BlockRAM does this job at up to 500 MHz worst case). Peter AlfkeArticle: 83431
"info_" <"info_"@\\nospam_no_underscore_alse-fr.com> wrote in message news:Qauce.51988$Of5.33143@nntpserver.swip.net... > http://www.alse-fr.com/English/Archive/VHDL_Coding_eng.pdf > > Your processes have many errors mentioned in this document. > > process 1 : missing reset on lvds_clk > process 2 : you use both edges of the clock ? (do you need this ?) > process 3 : wrong sensitivity list, maybe not synthesizable > depending on the target technology (asynchronous load), > lvds_1_in is clocked by both edges and negatively clock enabled > load_lvds ?? > ...and learn about 'case' statements. Syms.Article: 83432
I am assuming you are in the US but Xilinx have 3 official distributors there look here http://www.xilinx.com/company/sales/ww_disti.htm . There are a few other places in the US that stock Spartan-3 that I have come across. A web search will probably dredge those up. Unfortunately, other than catalogue operations, a lot of distributors are not interested in selling small numbers of parts. MOQs of hundreds or even thousands are not now uncommon. John Adair Enterpoint Ltd. - Home Of Low Cost Spartan-3 Development Board MINI-CAN. http://www.enterpoint.co.uk "dlharmon" <harmon.darrell@gmail.com> wrote in message news:1114799669.004339.239250@z14g2000cwz.googlegroups.com... > I am currently doing work on a small board with a FPGA and DSP. I have > been planning to use the Xilinx XC3S1000-4FT256C , but Nuhorizons > doesn't seem too interested in selling me 2 for a prototype. Where > else could I find these? The Xilinx online store only has parts up to > the XC3S400. I have checked digikey, but they are a few years behind > on the Xilinx parts. > > I may have to consider changing to Altera since Digikey seems to stock > them. I really don't want to do this, but if forced by unavailability > of parts I will have to. > > Darrell Harmon > http://dlharmon.com >Article: 83433
Stop by any time you like and sign an NDA, I think you can figure out where I am. I will be happy to show you my async FIFO schematic and why it integrates with higher performance than a coregen type FIFO. I don't design in VHDL or verilog because I am not a wizard, just an average engineer.Article: 83434
"Bryan" <bryan@srccomp.com> wrote in message news:1114802127.737459.181520@l41g2000cwc.googlegroups.com... > Stop by any time you like and sign an NDA, I think you can figure out > where I am. I will be happy to show you my async FIFO schematic and > why it integrates with higher performance than a coregen type FIFO. I > don't design in VHDL or verilog because I am not a wizard, just an > average engineer. Average engineers aren't pompous. Do you even KNOW where the first real async FIFOs came from?Article: 83435
Then Peter isn't an average engineer. Whats the prize? Wizard hat? I am always highly skeptical of anyone that claims to be the inventor of ideas(that sounds pompous). I certainly didn't invent a new FIFO. Just integrated it into my data path for the highest performance. If you want to make the challenge tricky then also design the FIFO to handle variable burst reads from 2 to 10 elements for all combinations of write and read clock speeds up to the maximum, otherwise it is just a simple fifo.Article: 83436
crazyd wrote:
> I have seen that ST has dabbled
> in embedded in FPGAs in the last few years, and have come up with
> their own proprietary embedded FPGA architecture. However, in the end
> they have abandonded it for 3rd party architectures. Does anyone have
> an idea why?
Discontinued products most often result from
a lack of paying customers.
-- Mike Treseler
Article: 83437You are going the wrong direction ! Benjamin Menküc wrote: > Hi, > > my problem is that behavior simulation doesnt work somehow. Why ? Understand what doesn't work and fix it ! Don't synthesize RTL code which doesn't even simulate... Do you hope synthesis will miraculously "fix" a bad description ? The usual question is : "my RTL works (simulates ok) but the chip doesn't". > Therefore I have to do post-translate simulation. I knew it was not for a good reason. > However during translation It's not a translation. It's synthesis. XST infers physical hardware on which it tries to map the behavior you've described in RTL. Garbage in -> Garbage out. > XST doesnt keep the net-names, so its a little bit hard to find the right > net in modelsim, I don't even know which net to take. Do I have to pick > the right net using fpga-editor? Or how do I get an overview over the > new nets? You should do as suggested by all the experienced designers : - Learn synchronous design. - Make sure you understand how VHDL works. - Write good quality RTL, follow the rules mentioned. - Make a very quick synthesis pass to uncover usual mistakes Focus on reports, warnings, and chase down words like "asynchronous", "combinational" "feedback" "loop" "latch" etc... - Write good (reliable, self testing, documented, reuseable...) test benches. - Simulate carefully the RTL code - Do a careful synthesis - If the design is challenging timing-wise, do a unitary P&R and verify the actual timing figures with Static Timing Analysis. There is usually no need to perform timing sim, for reasons outside the scope of this post (and for the complexity level you are targeting). * A little time spent with the tools' documentation is a good investment. * Analyze known good code and understand how the design it was implemented and why. Re-inventing the wheel has its virtues, but it takes time... And no : don't open ISE's JC VHDL examples projects ;-) Bert CuzeauArticle: 83438
Here are some lines I have used in presentations:
The maturing FPGA market
Dominated by two players, Xilinx and Altera
With 52% and 34% market share = 86% combined
Remaining players scramble for niches
All non-dedicated players have given up:
Intel, T.I., Motorola, NSC, AMD, Cypress, Philips, ST...
Late-comers have been absorbed or failed:
Dynachip, PlusLogic, Triscend, Siliconspice (absorbed)
Chameleon, Quicksilver, Morphics, Adaptive Silicon ...
It;s not just because of patents
The big guys lack the focus, the small ones lack the resources.
Peter Alfke
Article: 83439Austin Lesea wrote: > MM, > > A well designed link has 0 errors. > ?? Well in communication theory books they assume that if there is noise that there is a chance > 0 that there will be an error in a period of time >0, this is just a matter of physics and mathematics. Same physics say that noise of 0 is only possible at extreme conditions, so I would say even a well designed link has errors, every logic circuit will very very rarely generate levels even if noise margins are high. Best Regards, RoelArticle: 83440
Peter, I have no doubt you wrote many FIFO that work ok, and believe it or not many other Eng did it as well, and even simulate it. We are all here for the fun and joy of Eng, so Lets not make it a Contest of who have the bigger .... A Better approach which I believe will be more suitable and more education will be since you feel so strongly about the FIFO you design why don't you write App note or white paper about how it is done so other Eng that are not aware of how to make Async FIFO will see and learn and who knows maybe some of us that know how will learn something new as maybe you have new way, After all there are many way to design Async FIFO's depend on the requirement and amount of resource available. (e.g. Phase handler, PPM handler, in high out low, in low out high, any to any and they can be with and without gray, using pessimistic approach, and so on and so on). Back to simulation yes you can simulate Async FIFO even if theoretically you can have infinite number of condition, since many of those infinite are the same, just like when you test SONET Frame you can argue it is impossible since there is infinite number of combination as each data can be differ gap between frame can be differ, number of frame can be differ etc, and there are many more examples of infinite condition which using finite number of test you can verify very well your design assuming the test bench is done properly. To give you an idea of one approach is have a script that generate two value in define file which you later include in your simulation. So for example the file output can be `define clk1 19.9 `define clk2 24.9 in one time and in another time can be for example `define clk1 36.1 `define clk2 10.8 and so on and so on, where the number and resolution depend on what you want to test (Myself I run all in unix so this file is generated using unix script, but I'm sure there is a way to do it also in window/dos or what ever is your platform). Another parameter which should be randomize is burst of data you write and how many of them per simulation. Than you compile all and at the end verify automatically that all work ok and if so your script start all over. After one night or what ever depend on how strong is your machine etc you can cover all the ranges you wanted, as well as maybe some pre define freq and definition for dedicated tests. Using 1ns/1ps or 1ps/10fs etc can help you get the resolution you need. The important thing from my experience is once you did all your dedicated test and verify all to let the $random(seed) work in the ranges of value you want to cover as well as make sure the test run automatically just as the verifier so when you run an overnight test you get large range of coverage. Of course you should keep all the seed that generate failer in the test so in the morning you can re-generate the same condition that cause the failer. But as always the most important this is Have funArticle: 83441
Dan, At the top level, just instantiate the 'p' signal from your pair. Next assign this to pin 123 or 124, whichever is the 'p' I/O. The Quartus software will take car of creating the 'n' signal, and it will place it next to 'p'. In your design, do you plan on using this a normal I/O or a serialized I/O. If it's normal (i.e. SDR or DDR), you don't have to do anything special. Just use it like any other port. If is is serialized, you must instantiate Altera's SERDES core. The output of the core will have a std_logic_vector that you can use. John MArticle: 83442
Berty wrote: > Back to simulation yes you can simulate Async FIFO even if > theoretically you can have infinite number of condition, since many of > those infinite are the same, just like when you test SONET Frame you > can argue it is impossible since there is infinite number of > combination as each data can be differ gap between frame can be differ, > number of frame can be differ etc, and there are many more examples of > infinite condition which using finite number of test you can verify > very well your design assuming the test bench is done properly. > > To give you an idea of one approach is have a script that generate two > value in define file which you later include in your simulation. > So for example the file output can be > `define clk1 19.9 > `define clk2 24.9 > in one time and in another time can be for example > `define clk1 36.1 > `define clk2 10.8 > and so on and so on, where the number and resolution depend on what you > want to test (Myself I run all in unix so this file is generated using > unix script, but I'm sure there is a way to do it also in window/dos > or what ever is your platform). Berty, How do you handle the case of timing violations in timing simulations ? It's usually difficult, and I remember having used VHDL configurations to turn FlipFlops with timing models into models that do not propagate X'es while performaing multiple clock domains timing simulation (and the validation then becomes nil wrt timing violation). In other words, I naively thought timing simulation wasn't the right tool to validate asynchronous design, if only because of the "worst case only" timing models, no MonteCarlo methods etc... I was more confident in a human expert mind than on a timing simulator based on timings that do not exist in the design. I'm sure I'm going to learn something here (I'm NOT an asynchronous design expert) And I'm not ashamed to say that I am happy experts like you design the asynchronous for me and let me focus on higher level issues :-) Bert CuzeauArticle: 83443
On a sunny day (29 Apr 2005 13:26:34 -0700) it happened "Peter Alfke" <peter@xilinx.com> wrote in <1114806394.160637.87120@g14g2000cwa.googlegroups.com>: >Here are some lines I have used in presentations: > >The maturing FPGA market >Dominated by two players, Xilinx and Altera > With 52% and 34% market share = 86% combined > Remaining players scramble for niches Actel has nice flash based stuff. Now there is a security leap. Finally we can violate all patents, and nobody can prove it. I love it. >All non-dedicated players have given up: > Intel, T.I., Motorola, NSC, AMD, Cypress, Philips, ST... >Late-comers have been absorbed or failed: > Dynachip, PlusLogic, Triscend, Siliconspice (absorbed) > Chameleon, Quicksilver, Morphics, Adaptive Silicon ... > >It;s not just because of patents >The big guys lack the focus, the small ones lack the resources. >Peter Alfke > >Article: 83444
Hi, after I added an extra process which gets the data (without combinational logic) from the external device, everything worls fine (-: Thanks very much! Alex "info_" <"info_"@\\nospam_no_underscore_alse-fr.com> schrieb im Newsbeitrag news:%Qcce.51706$Of5.33110@nntpserver.swip.net... > Alexander Korff wrote: > >> Hello, >> >> I use Quartus 4.2 SP1 WebEdition for my work. >> The Hardware I built gets data from an external source with 40Mbit/s >> which has an 16Bit multiplexed bus with an High/Low word and Strobe Pin >> to tell me when data is valid and which is the high and wich is the low >> word. After that I analyse the data an give it to an PC. >> In the functional simulation everything works fine, but when I test this >> in reality, the demux unit does not seem to work right, with Signal Tap >> II I can see that the values comming out of this are something but not >> the values which are feed into the FPGA. But then the analysis of the >> worng values works fine, only the demux unit seems to be broken. >> Are there any tools to simulate such a behaviour or can you recommend me >> something to do ? Or can I change something in the timing options of >> Quartus ? >> >> Thanks in advance. >> >> With best regards. >> >> Alex >> > > If you are treating your IO pins as synchronous inputs, you > need to assign timing constraints on the IOs and on your clock. > Quartus does then a very good job at building correct delays to > achieve timing coherence, but it cannot guess your constraints. > You need to feed QII with accurate figures ! (garbage in garbage out) > > Then, static timing analysis (post P&R indeed) will confirm > that everything is fine (Tsu, Th figures in the timing reports). > > STP II, being a synchronous logic analyzer, isn't the best tool > for debugging timing issues. > Timing sim can help, but you need to feed to with accurate > timings indeed... back to square 1. > > Last : a mux is combinational. If you pile up logic (combinational > layers before the first FlipFlops, it becomes a difficult case > (with a potentially high difference between shortest & longest path). > If your IOs are resynchronized asap (before the combinational logic), > then timing issues become Fmax issues, which are trivial. > > Bert CuzeauArticle: 83445
Hi Folks, I was wondering what is the best way of finding the median of a floating point array in hardware. I am currently thinking of using a bit voter scheme for fixed point but I don't think this will be able to differentiate the exponent in the floating point. Would I have to adopt a sorting method for floating? Any help will be useful. Thanks PaulArticle: 83446
In article <815b13d9.0504291457.67b424fd@posting.google.com>, Paul Lee <paul.sw.lee@gmail.com> wrote: >Hi Folks, > >I was wondering what is the best way of finding the median of a >floating point array in hardware. I am currently thinking of using a >bit voter scheme for fixed point but I don't think this will be able >to differentiate the exponent in the floating point. Would I have to >adopt a sorting method for floating? Floating point numbers (at least in IEEE representation) sort in the same way as integers; any FP number with exponent e+1 is larger than any FP number with exponent e. Just think of them as 32- or 64-bit numbers, and use the integer median algorithm. I wonder why you want to use hardware for median of an FP array, when it's a nearly-linear-time algorithm in software. You want the Yth-largest element. So pick a random element X, partition the array into <X and >X counting how many elements were <X. If there are >Y elements <X, do the algorithm with the <X elements and Y, if there are Z elements <X with Z<Y, do the algorithm with the >=X elements and Y-Z. TomArticle: 83447
Here is the URL for a FIFO description that I published a few months ago. http://www.xilinx.com/publications/xcellonline/xcell_52/xc_v4fifo52.htm But back to simulation: I have tested metastability in our flip-flops, and I found that the metastability-catching timing window has a width of 0.07 ns for a metastable-caused delay of 1 ns 0.07 femtoseconds for a metastable-caused delay of 1.5 ns. For every extra half ns of delay, the window becomes a million times smaller. For a 2-ns delay you have to hit a timing bulls-eye of 10e-22 seconds. Please tell me how you can simulate that... Peter AlfkeArticle: 83448
On 29 Apr 2005 01:26:57 -0700, "Stanley" <cltsaig@tsmc.com> wrote: >Hi John, > >Thanks for your feedfack. > >>What exactly is this problem solving? >Using the FPGA to compute this function instead of CPU. Yes, but why are you moving this from a CPU to and FPGA ??? >> how many doubles FP ops/sec. >There is no performance requirement for my concern, as long as the >function is evaluate from the FPGA instead of CPU. So it isn't for speed. >> It looks like if you could do this at all in an FPGA you will be >needing a big one or will settle for many cycles. >Size of logic gates that it consumed is also not a matter. You aren't doing it for cost. >> MicroBlaze with a single precision FPU >Thanks for given this information, but I don't know to implement this >onto a FPGA, what is the best way that I can get start with designing >this FPU? You don't know how to implement floating point in an FPGA. >> You could perhaps use block floating point, or use differnet number >systems. >But normally the floating point IP block doesn't have trigonometric >function You dont know the difference between block floating point and a floating point block. I'll bet you don't know how to do trig with basic floating point either. >Kindest regards, > >Stanley I'll guess (based on your posting domain) that you are prototyping an ASIC. Therefore, getting this to run on an FPGA is probably the least of your problems. You need to figure out how this is going to run on your ASIC. Then write the HDL. Then simulate it. Then maybe port it to the FPGA (if it will fit), or multiple FPGAs. Good luck, Philip (FYI, my response to your initial post was to run screaming from the room, waving my hands wildly in the air. I could not think of a good way to post that.) I wish you even more good luck. Philip Freidin FliptronicsArticle: 83449
What you ask has already occurred: (see embedded links) "Berty" <wooster.berty@gmail.com> wrote in message news:1114809109.736832.199490@z14g2000cwz.googlegroups.com... > Peter, > I have no doubt you wrote many FIFO that work ok, and believe it or not > many other Eng did it as well, and even simulate it. > > We are all here for the fun and joy of Eng, so Lets not make it a > Contest of who have the bigger .... > > A Better approach which I believe will be more suitable and more > education will be since you feel so strongly about the FIFO you design > why don't you write App note or white paper about how it is done so > other Eng that are not aware of how to make Async FIFO will see and > learn and who knows maybe some of us that know how will learn something > new as maybe you have new way, After all there are many way to design > Async FIFO's depend on the requirement and amount of resource > available. (e.g. Phase handler, PPM handler, in high out low, in low > out high, any to any and they can be with and without gray, using > pessimistic approach, and so on and so on). How about: http://tinyurl.com/aa9or (http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sGlobalNavPick=SUPPORT&s SecondaryNavPick=&category=&iLanguageID=1&multPartNum=1&sTechX_ID=pa_fifo) Or maybe: http://www.eetimes.com/editorial/2000/design0003.html "In 1970, Alfke invented the first FIFO integrated circuit, the Fairchild 3341" This individual has made a career out of helping other engineers and it seems there are some here who don't RESPECT what this man has done for the average FPGA designer or UNDERSTAND his contributions across the last 4 decades. I, for one, appreciate the whitepapers and articles contributed outside the forum, the general help inside therse forums, and the contributions to the industry as a whole. Honestly, I don't understand the level of disrespect I see in this conversation. I never quite understood why "flaming" was such a big issue on the usenet because I've stayed away from the less professional venues. Here I expect people to have a little homework under their belt before making disparaging comments toward someone who KNOWS his business. > Back to simulation yes you can simulate Async FIFO even if > theoretically you can have infinite number of condition, since many of > those infinite are the same, just like when you test SONET Frame you > can argue it is impossible since there is infinite number of > combination as each data can be differ gap between frame can be differ, > number of frame can be differ etc, and there are many more examples of > infinite condition which using finite number of test you can verify > very well your design assuming the test bench is done properly. > > To give you an idea of one approach is have a script that generate two > value in define file which you later include in your simulation. > So for example the file output can be > `define clk1 19.9 > `define clk2 24.9 > in one time and in another time can be for example > `define clk1 36.1 > `define clk2 10.8 > and so on and so on, where the number and resolution depend on what you > want to test (Myself I run all in unix so this file is generated using > unix script, but I'm sure there is a way to do it also in window/dos > or what ever is your platform). > > Another parameter which should be randomize is burst of data you write > and how many of them per simulation. > Than you compile all and at the end verify automatically that all work > ok and if so your script start all over. > After one night or what ever depend on how strong is your machine etc > you can cover all the ranges you wanted, as well as maybe some pre > define freq and definition for dedicated tests. Using 1ns/1ps or > 1ps/10fs etc can help you get the resolution you need. > > The important thing from my experience is once you did all your > dedicated test and verify all to let the $random(seed) work in the > ranges of value you want to cover as well as make sure the test run > automatically just as the verifier so when you run an overnight test > you get large range of coverage. > Of course you should keep all the seed that generate failer in the test > so in the morning you can re-generate the same condition that cause the > failer. > > But as always the most important this is Have fun Having fun *is* important. I appreciate the comments that may help others explore the subject further and the insights you have into design and test. But there are people who actually "are" experts out there. My apologies, Berty, if it seems I'm coming across strong against *your* post since it's more Bryan's comments that disturbed me, but those whitepapers and App Notes ARE out there.
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