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Austin Lesea wrote:
> How many folks out there want to have the local spreadsheet version
> for estimating?
>
I vote for a spreadsheet. Using the web thing to present power numbers
to a customer is a real PITA.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 83726Benjamin Menküc wrote: > Hi, > > after I set the optimization effort to "high", I can get the whole > 270MHz now (thats all the DCM can generate out of 100 MHz). > > Any comments how to make my design better are still welcome though :) > > regards, > Benjamin Yup, use DDR clocking of your IOBs and double the internal path width. Just a sugestion without studying your code. This should give more than 600MHz. Regards, ThomasArticle: 83727
Is it a hard and fast rule that we map the signals/ports of the user logic to the ports of the OPB/PLB, or is it enough if we cna map them to the IPIF signals. Say User logic has some ports namely, clk, reset of std_logic, input and output of std_logic_vector. Now is it enought if we map these ports to the IPIF, which is the negotiator between OPB logic and user logic??. The question is, is it needed to map the reset to OPB_Rst, clk to OPB_CLK etc, (or) is it enough if we map clk to Bus2IP_clk, reset to Bus2IP_Reset, and input and output to the Bus2IP_Dbus and IP2Bus_Dbus. I will greatly appreciate if someone throws a clear picture about this issue. Thanks and Regards, Chak.Article: 83728
you may also reply to nara_chak45@yahoo.com. Thanks and Regards, Chakra.Article: 83729
Also I have another issue, I recently installed EDK 6.2 and when i try to open the application from the menu, it says "file libSecurity.dll was not found, reinstalling the application may solve the problem" . i reinstalled twice but the same issue comes in. If someone has any solution for this, it will be great if you could share the info. Thanks and Regards, chak.Article: 83730
Hi All, I am working on the ML300 board and am trying to control an external peripheral, which is a small DC motor using the board. I have written a PWM code (control the motor) and the code is synthesyzing fine also its simulation results are good enough. I also managed to convert it as a peripharal which attaches itself to the OPB, using IPIF. My question is, How do we make the PWM module inside the FPGA talk to the amplifier circuit for the motor ( supposing i have a bridge circuit which amplifies the PWM output(series of pulses) ). The issue is like this, I have a PWM output signal on the opb bus, and i want the output (the pulse), to be transferred to the external circuit, using the GPIO/Experimental area (board is directly below the touch screen). If someone could throw somelight into this problem, that will be of great help. Looking forward to replies in this regard. Thanks and Regards, Chak.Article: 83731
Rob Gaddi wrote: > So, it seems from another thread that the general consensus is > somewhat against clock gating. I'm still somewhat new at the whole > FPGA thing, so I was hoping for some input as to: > > a) Is this a general rule, or does it only apply to high speed clocks, > and if so, what starts to become "high speed"? > > b) I'm using a Spartan III and currently using a BUFGCE to gate a 40 > MHz clock that is only used externally. Is this poor form, or is it > just clock gating through LUTs that's frowned upon? > > Any advice is, as always appreciated. > > -- Rob When we used clock gating in PALs, GALs and even most CPLDs we could be aware that every path had almost (sub nano second) the same delay. This made things happen that were not possible in a different way with those devices. FPGAs are very different in one point: Delay! Thus you will likely get glitches and runt pulses and even a reroute won't give you a predictable result. You should avoid this. Today you simply have enough speed to double the clock if you want to adapt an old design. Regards, ThomasArticle: 83732
finding old archives might help you. i think there had been some relevant discussions in past on this topic. regards, $hreya$Article: 83733
Peter Alfke wrote:
>Remember, any circuit that does not work close to its speed limit
>represents waste.
>Peter Alfke
>
>
>
Peter, while this is true from a device utilization standpoint, there is
also development time, life cycle costs etc to consider. For someone
that is not well versed in the nuances, this sometimes significant cost
can weigh in favor of a larger design clocked at a relatively slow clock.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 83734On 4 May 2005 10:28:15 -0700, "Peter Alfke" <peter@xilinx.com> wrote: >Remember, any circuit that does not work close to its speed limit >represents waste. >Peter Alfke Designing close to the limit is a nice idea. But unless the part has been completely and correctly characterized by the vendor, designing too close to its speed limit can be fatal. Having been burnt by speed files that changed for the worse after I'd completed a design, I now try to keep a healthy margin between my design requirements and the speed limit du jour. Bob Perlman Cambrian Design WorksArticle: 83735
Maybe I misspoke. I meant to say that a cicuit that runs at a fraction of its speed capabilty can be miade to do multiple jobs sequentially. That obviously only applies when the designer runs the circuitry at half or quarter speed or less. Only then can you seriously think about time-sharing or time multiplexing. it's good to have friends who watch over me :-) Peter AlfkeArticle: 83736
Hi all. Does anyone have a link to any work done in FPGA for quantization and rate control? I need this for an undergraduate engineering project where I have to compare my own solution to previous work done in the area. Thanks. Dan NilsenArticle: 83737
Hal Murray wrote: > >I am designing a board with 9 Xilinx V4FX60 FPGA's configured via > >System Ace CF controller. > > > >Does anyone have any experience regarding the max number of FPGA's in a > >JTAG chain that can be succesfully configured? > > 9 is a big number. Be very careful of the clocks. > I wouldn't expect problems with anything else. I just got a JTAG analysis done on my board. Interestingly, they strongly suggested buffering TMS as well as TCK. MarcArticle: 83738
bart wrote:
>I need 1000 frequency "bins", where each bin is a descrete frequency.
>As Thomas Womack pointed out above, it is beter defined as a N-point
>DFT with 1000 frequency bins, where N = 1024. For each sample, every
>microsecond, there is 24-bits of data lets call that x(n). During that
>microsecond there must be 1000 MACS in parallel to calculate the N=1024
>DFT. This would happen for 1024 samples to calculate the N-point DFT.
>I hope that is a better description. Thanks for the input.
>
>
>
Bart, as others have pointed out, it sounds like you are doing a brute
force DFT. The FFT reduces the computations by exploiting symmetry
present in the evenly spaced bins. Most FFTs are done with a variation
of the Cooley-Tukey algorithm which factors DFTs with a power of 2
number of points by successively breaking the DFT into half sized DFTs
and combining the results with a phase rotation. Your post seems to
indicate that you are looking instead for a 1000 point transform. You
can either use a 1024 point FFT by padding the input data to fill out
the size and accepting the slightly smaller bin size, or if you need the
1000 point DFT, you can use some of the other FFT algorithms to arrive
at a 1000 point transform. Either way, you'll greatly reduce the number
of multiplies by using a Fast Fourier Transform instead of the DFT. The
Smith and Smith book (
http://www.amazon.com/exec/obidos/ASIN/0780310918/andraka/102-8981403-3626538
) provides a pretty good coverage of the various FFT algorithms that
you'd need for either approach. It is presented more from a software
perspective than from hardware, but nevertheless it provides a
comprehensive background to permit you to build a hardware
implementation that is far more efficient than what you are proposing.
The other point I should make is that you can use a process clock that
is faster than your sample clock, which I think you said is only 1 MHz.
Our FFT cores will run at over 300 MS/sec in current FPGA devices, and
they don't use anywhere near the 1000 multiplies you are looking at.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 83739Benjamin Menküc wrote: > Hi, > > when I want to use a SRL16, I have to "include" the component in my > entity like this: > > component SRL16 > port ( > Q : out std_logic; -- SRL data output > A0: in std_logic; -- Select[0] input > A1 : in std_logic; -- Select[1] input > A2 : in std_logic; -- Select[2] input > A3 : in std_logic; -- Select[3] input > CLK : in std_logic; -- Clock input > D : in std_logic -- SRL data input > ); > end component; > > Can I find templates for these component declarations somewhere? In the > lib.pdf I can find only instantiation templates. Besides that, I can not > use the generic map (INIT => X"0000")... > How do I do it properly? Are there any include files for all the design > elements? > > regards, > Benjamin Uncomment the following lines which ISE should insert in the beginning of any VHDL file it creates when you ask it to create a new "VHDL module": library UNISIM; use UNISIM.VComponents.all; This should allow you to use all the primitives defined in the Libraries Guide. -JimArticle: 83740
Benjamin,
You can simply include the UNISIM library which contains the component
declarations and attributes (black box attributes) for all of our supported
components. I have included a simple example below that shows the
instantiation of two SRLC16E's and a MUXF5 to produce a dynamic addressed,
32-tap shift register. Also notice that I have included the generic map for
INIT in my instantiation. This will be forwarded onto the PAR tools to
initialize your SRLC16E primitives. This code was compiled by XST so I am
unsure how other tools support passing the INIT attribute. Also note that
for SRL16E's, you can generally infer them in your HDL much easier than
instancing them.
Cheers... Mark
Xilinx FAE
-------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity srl16e_instance is
PORT (
clk : in std_logic;
ce : in std_logic;
din : in std_logic;
addr : in std_logic_vector(4 downto 0);
dout : out std_logic
);
end srl16e_instance;
architecture Behavioral of srl16e_instance is
signal srla : std_logic; -- output from U_SRL_LOW
signal srlb : std_logic; -- output from U_SRL_HIGH
signal srl_cascade : std_logic; -- cascade between LOW and HIGH
begin
u_SRL_LOW : SRLC16E
generic map
(
INIT => X"DEAD"
)
port map
(
CLK => clk,
CE => ce,
D => din,
A0 => addr(0),
A1 => addr(1),
A2 => addr(2),
A3 => addr(3),
Q => srla,
Q15 => srl_cascade
);
u_SRL_HIGH : SRLC16E
generic map
(
INIT => X"BEEF"
)
port map
(
CLK => clk,
CE => ce,
D => srl_cascade,
A0 => addr(0),
A1 => addr(1),
A2 => addr(2),
A3 => addr(3),
Q => srlb,
Q15 => open
);
mymux : MUXF5
port map
(
I0 => srla,
I1 => srlb,
S => addr(4),
O => dout
);
end Behavioral;
"Benjamin Menküc" <benjamin@menkuec.de> wrote in message
news:d5e9kl$5k1$01$1@news.t-online.com...
> Hi,
>
> when I want to use a SRL16, I have to "include" the component in my
> entity like this:
>
> component SRL16
> port (
> Q : out std_logic; -- SRL data output
> A0: in std_logic; -- Select[0] input
> A1 : in std_logic; -- Select[1] input
> A2 : in std_logic; -- Select[2] input
> A3 : in std_logic; -- Select[3] input
> CLK : in std_logic; -- Clock input
> D : in std_logic -- SRL data input
> );
> end component;
>
> Can I find templates for these component declarations somewhere? In the
> lib.pdf I can find only instantiation templates. Besides that, I can not
> use the generic map (INIT => X"0000")...
> How do I do it properly? Are there any include files for all the design
> elements?
>
> regards,
> Benjamin
Article: 83741In article <1114556692.455174.18400@f14g2000cwb.googlegroups.com>, Peter Alfke <peter@xilinx.com> wrote: >Berty, I disagree. >While it is good for every young engineer to learn the basic skills, >designing an asynchronous FIFO is far from "basic". I realize your credentials, but I will still have to disagree. Asynchronous boundary crossings are even more common these days than in previous decades (systems supporting a plethora or protocols and standards, chips so big and fast that signals can't even cross it in one clock cycle, etc.), and dealing with clock domain crossings needs to be part of the basic toolkit of almost any competent digital design engineer. If a system requires an async FIFO, there is a reasonable probability that there are other async crossings involved. An engineer who doesn't understand the basic problem and solution space will possibly screw-up somewhere other than the FIFO, especially if he/she doesn't even have a basic understanding of even how to solve and not solve the problem using at least some form of simplified logic structures. Now if you want to do analog circuit design of full-custom ASIC flip-flops to tweak the the metastability window a few picoseconds smaller at the same statistical certainty level, I'll agree that that may no longer be a basic skill. IMHO. YMMV. -- Ron Nicholson rhn AT nicholson DOT com http://www.nicholson.com/rhn/ #include <canonical.disclaimer> // only my own opinions, etc.Article: 83742
Duane Clark ha scritto: > I modified a little the ddr_clocks reference design. I added that diff > to the same location as the other files. Notice that it is against an > EDK6.2 version of that file. Also, I found and fixed one bug in > read_data_path.vhd, though this only affects the external interface. > > The bd_top.vhd file shows one example of how to connect everything. You > probably should run this simulation to make sure everything works, then > modify it to zero out the external interface and try it again. > > I also added an example system.mhs file to show how they are connected > in a real system. And finally, an example system_top.vhd file, to show > the top level structure of how they connect to the pins. Hi and thanks for the new files, worked on it again yesterday and now it still doesn't run properly but at least now when I write a 16 bit value the system stalls (before it couldn't write anything from 32 bit to 8 bit: I always got back 0), so it's clear that something as changed (although I don't know if for the better :) ). I'll see if finally I could make it work! Thank you for the great support!Article: 83743
I am about to buy an fpga dev board for personal use and am not able to decide between xess XSA-200 board which costs $149 and the spartan-3 starter kit from digilent costing $100(without jtag cable-$20). the features are more or less the same except for sram/sdram on board differences. can those of you who know more about these boards or used them give some suggestions on how they compare. thanks for all your feedbackArticle: 83744
In article <1114818211.545915.148920@o13g2000cwo.googlegroups.com>, Peter Alfke <peter@xilinx.com> wrote: >But back to simulation: >I have tested metastability in our flip-flops, and I found that the >metastability-catching timing window has a width of >0.07 ns for a metastable-caused delay of 1 ns >0.07 femtoseconds for a metastable-caused delay of 1.5 ns. >For every extra half ns of delay, the window becomes a million times >smaller. >For a 2-ns delay you have to hit a timing bulls-eye of 10e-22 seconds. >Please tell me how you can simulate that... One engineering rule is that "there is no such thing a digital". You seem to understand that. Digital logic is just a simplification of analog electronics used well away from thresholds. But another, more subtile rule is that "there is no such thing as analog". At 10e-22 seconds you are closer to the limits of electrical and thermal noise, maybe even quantum uncertainty. Neither standard Spice, nor an event-driven simulator will do. You will need do a statistical analysis. So you need to define "reliable" at some statistical level. Before throwing out a long string of nine's for your desired synchronizer failure rate, you also might want to ask about thermal noise, ground noise, EMI, crosstalk, environmental and package radiation, latent process faults which passed chip test, solder reliability, etc. etc. and how those might affect your total system failure rates. IMHO. YMMV. -- Ron Nicholson rhn AT nicholson DOT com http://www.nicholson.com/rhn/ #include <canonical.disclaimer> // only my own opinions, etc.Article: 83745
Libraries Guide is always a good place to start for component instantiation.
There are some component templates also available in ISE under the little
light style button.
If you want a simple shift then doing it in VHDL or Verilog is also easy. If
write your code as the following style (VHDL shown), i.e. without a reset,
most synthesisers will turn it into SRL16 based logic.
process(clk)
begin
if clk'event and clk='1' then
shift1 <= input;
shift2 <= shift1;
...
shift(n) <= shift(n-1);
end if;
end process;
John Adair
Enterpoint Ltd. - Home of low cost FPGA development board MINI-CAN.
http://www.enterpoint.co.uk
"Benjamin Menküc" <benjamin@menkuec.de> wrote in message
news:d5e9kl$5k1$01$1@news.t-online.com...
> Hi,
>
> when I want to use a SRL16, I have to "include" the component in my entity
> like this:
>
> component SRL16
> port (
> Q : out std_logic; -- SRL data output
> A0: in std_logic; -- Select[0] input
> A1 : in std_logic; -- Select[1] input
> A2 : in std_logic; -- Select[2] input
> A3 : in std_logic; -- Select[3] input
> CLK : in std_logic; -- Clock input
> D : in std_logic -- SRL data input
> );
> end component;
>
> Can I find templates for these component declarations somewhere? In the
> lib.pdf I can find only instantiation templates. Besides that, I can not
> use the generic map (INIT => X"0000")...
> How do I do it properly? Are there any include files for all the design
> elements?
>
> regards,
> Benjamin
Article: 83746Hi Jim, > Uncomment the following lines which ISE should insert in the beginning > of any VHDL file it creates when you ask it to create a new "VHDL module": > > library UNISIM; > use UNISIM.VComponents.all; > > This should allow you to use all the primitives defined in the Libraries > Guide. Thanks, that was it. regards, BenjaminArticle: 83747
Hi, sure it can be implemented. I am about to do it. What concerns do You have exactly? Serialization is no problem (I have done it for a LVDS LCD Interface). I/O cell, what do You mean? You have to use the OBUFDS Peripheral of the FPGA (in my case Xilinx Virtex II Pro), that does the electrical LVDS stuff. The Tx/Rx protocol is explained completely in the DVI specs, which can be found here: http://www.ddwg.org/downloads.html . regards, BenjaminArticle: 83748
Hi, I would take the board with the SDRAM from XESS. For applications like image or soundprocessing a little bit more ram never hurts. regards, BenjaminArticle: 83749
Hi, I am about to start with my DVI implementation. Since I need some testbench, I thought I could log the dvi signals using a logic analyser and add that data with a script to my vhdl testbench. How would you generate a DVI test-stream? Write a little C programm that generates the Data instead of loggin? That would be one source of error more though. Any suggestions or ideas? regards, Benjamin
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