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Hi, You can also download a free (limited) version of Modelsim's simulator from the same site that you can get Xilinx's free ISE tools (called webpack). The free simulator will start to slow down on larger files, but it still runs! A previous response mentioned the tutorials from Xilinx. Another source are the appnotes on www.dulseelectronics.com . Good luck with your FPGA designs. PhilArticle: 83926
"Benjamin Menküc" <benjamin@menkuec.de> wrote in message news:d5o79u$2ke$01$1@news.t-online.com... > Hi, > > I am doing stuff with Displays. The data rate is about 3 gigabits/s for > the pixels. I am thinking about using the XUPV2P from digilent for this > application. > > Since I would have to read and write at the same time, I would need a data > rate of about 6 gigabits/s. > Would it be possible with this board? > http://www.digilentinc.com/info/XUPV2P.cfm > > regards, > Benjamin Why don't you try emailing digilentinc, they usually reply quite promptly. AlexArticle: 83927
Hi peter, So what you mean to say is in simple dual port memories one port is restricted only for write, and the other one only for read. I read in ALTERA cyclone FPGA's that there memory blocks can be used as 1)Simple dual port memory. 2)True dual port memory. 3)FIFO buffers. Is it the same in XILINX. But according to your explanation Simple dual port memory is nothing but a FIFO, so why have they explicitly mentioned as FIFO buffers. Please clarify on the 3 types of memory usages. Thanks in advance, PraveenArticle: 83928
a no-name company touting quality ip cores, hmmmm... makes one wonder if its stolen stuff.Article: 83929
I have a 500K gate, 40MHz design. When I first implemented that for xc2v6000, P&R succeeded with 2ns margin. Now I decided to inserted a parallel - serial converter, by using DCM to raise the clock to 80MHz, synchronized with original 40MHz clock. The logic in P-S is quite simple, however, after I ran P&R, the timing violation for 40MHz occur and max path roared to 45ns, but timing for 80MHz is 10.5ns. I thought it was caused by the P-S and the output path, so I added a ring of 8 registers to the serial output in order to break down the output path and minimize its effect on the 40MHz design (whose timing was very tight). Now I achieved a 10.2ns on 80MHz clock and 37ns on 40MHz clock. Far from my goal. Device utilization was abundant at this time. Am I doing the right thing? What trick can you advise? Thank youArticle: 83930
I cannot speak for Altera and their marketing messages. A "true dual-port memory" is obviously a superset of a "simple dual-port memory", and it seems that both Xilinx and Altera have this type of memory. Dual-ported memories can be used for many things: FIFOs, LIFOs, Stacks, Caches, Register Files, State Machines, Code Converters, Sequencers, Counters... Xilinx Virtex-4 has a built-in "hard" FIFO controller (guaranteed for 500 MHz operation.) Altera does not have anything remotely similar. They are just the champions of Marketing B.S., and have been for decades... Peter AlfkeArticle: 83931
"Alex Gibson" <news@alxx.net> wrote in message news:3eanggF2268gU1@individual.net... > > Why don't you try emailing digilentinc, they usually reply quite promptly. > Their e-mail must be more reliable than their web site then. Maybe I'mj ust unlucky, but about half the time I try to go there (including today) I can't get in.Article: 83932
On 9 May 2005 23:02:11 -0700, "Peter Alfke" <alfke@sbcglobal.net> wrote: >I cannot speak for Altera and their marketing messages. >They are just the champions of Marketing B.S., and have been for >decades... >Peter Alfke Apparently you do speak about A's marketing messages. Don't you think it's a little bit silly to hide behind a non-X domain to call A names? I expected better from you and X to be frank.Article: 83933
> Whatever, I'll wait for Austin to post and clear this up! > Cheers, Syms. Me too!Article: 83934
Hi, I looked into the bin folder and the security.dll is available there. I guess the path variables are set when we install the software( there is a choice when we install, the software. well is there anyway we can set the path variables manually?? Thanks for the repliesArticle: 83935
Hi, I want to do the following: 32-Word CAM, 10-Bit Wide With Altera Cyclone or Stratix it can be done just by using am RAM:2-Port template. That leads to the following component: data[0] wraddress[14..0] wren rdaddress[9..0] rden clock q[31..0] rdaddress[9..0] corresponds to the 10bit-word to search (within one clock cycle) and q[31..0] shows the position of the hit. If there is more than one hit I perform a second stage search with a different module. data[0] is kept HIGH to write data into the CAM, it is kept LOW when erasing the CAM entry. So my question: Is such a CAM implementation possible for Lattice EC FPGAs ? Or is the architecture of the integrated RAM blocks quite different so that it will not work ? The Lattice IP MANAGER has the following pseudo dual port memory module: WrClock WrClockEn WE RdClock RdClockEn WrAddress Data Rdaddress Q Do "WrClockEn" and "RdClockEn" correspond to the "wren" and "rden" in Cyclone devices? Why does Lattice have an additional "WE" but no additional "RE" ? Thank you for your opinions. Rgds Andr=E9Article: 83936
Benjamin Menküc <benjamin@menkuec.de> writes: > Hi, > > I figured out so far, that I have to use a TFP401 from TI for the TMDS > interface. > > What DVI application are you developing? > We use DVI to display the results of our image processing system - we used VGA on the previous-generation system, but getting RAMDACs was getting harder and harder. We ended up with the TFP410 as well! Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 83937
Generally speaking.. by the time you get fifo-full.. its too late... 1/2 full is a better option Simon "Aurelian Lazarut" <aurash@xilinx.com> wrote in message news:d5nqi5$1461@cliff.xsj.xilinx.com... > FIFO full? > Aurash > > ARRON wrote: > > >I send 50 bytes character to serial port of UART1655 in FPGA Board,But only the first 16 bytes of received data is correct in turn, and the left is out of order,what is the matter? > > > >thanks for your help!!! > > > > > > > -- > __ > / /\/\ Aurelian Lazarut > \ \ / System Verification Engineer > / / \ Xilinx Ireland > \_\/\/ > > phone: 353 01 4032639 > fax: 353 01 4640324 > > >Article: 83938
Mostly when the software calculates its timings, it displayes the worst case timings assuming low voltage and max temp (85C). At 55C the timings get slightly better. If you want to use a device whos timings arn't met by default, then contact your Altera dealer directly. Simon <alanmyler@yahoo.com> wrote in message news:1115658186.564532.12360@f14g2000cwb.googlegroups.com... > How do I perform a timing analysis using Quartus, with a worst case > temperature of less than the default for the device? For example, I > would like to check timing on a commercial grage-7 Cyclone part at 55C. > > > Many thanks, > > Alan Myler >Article: 83939
The situation is that my design isn't meeting the default worst case timing. However, the device isn't going to heat up to 85C in operation, I estimate it'll hit 55C max., so I'm simply looking for some way of assuring myself that it'll meet the timing constraints under this less harsh operating environment. AlanArticle: 83940
Hello All, I am using Xilinx PCI/PCIX Logicore. FPGA is configured with a default bitstream first (either PCI or PCIX) and if the bus is different, after PCI reset in the bus idle time, the FPGA gets configured once again with another bit stream. 1. Is this a valid design...? 2. when I keep PCIX as default bitstream and insert the card in PCI system this strategi is working fine. but when I keep PCI as default bit stream and boot in PCIX machine. The card gets detected but it dosent allocate any resources to the card. can anybody give any clue what may be happening in the second case. Is there any measure difference bet PCI and PCIX machine boot sequence. Or I am forgetting something. Thanks in advance Regards KedarArticle: 83941
Piotr Wyderski schrieb: > Thomas Rudloff wrote: >> Maybe a CPLD instead of an fpga may be a better choice in your case. > Hm, I don't think so, large (512+ cells) CPLDs are very expensive. Yes, but to replace 500 - 1000 LUTs you do not need 512+ cells. You can usually get along with about the number of cells as the design has flip-flops, and most designs that I see use less flip-flops than LUTs. Kolja SulimmaArticle: 83942
<rkruger@altera.com> wrote in message news:1115674113.461392.325650@z14g2000cwz.googlegroups.com... > Altera does not have any policy to stop users from using our legacy > MAX+PLUS II software. We do encourgae users to take advantage of the > latest Quartus II software performance and features but there is > nothing to stop you from continuing to use MAX+PLUS II software. > > If you purchased an Altera subscription package your license should be > perpetual i.e. it will work even after expiration. If you downloaded > the free MAX+PLUS II BASELINE software the license will stop working > after 6 months but you can simply request another free 6-month license > extension on the Altera web site at > http://www.altera.com/support/licensing/lic-index.html (2nd to last > link under Legacy Software Licenses). > > I am sorry to hear you had an unpleasant experience trying to convert > your MAX+PLUS II design into a Quartus II design. Altera has put a lot > of effort into making this process as easy as possible and we have > received a lot of positive feedback. We even went as far as including a > MAX+PLUS II user interface option in the software and put a lot of > effort into the "Convert MAX+PLUS II project..." feature to make the > process as simple as possible. The Quartus II software on average > offers 15% higher fmax performance and while consuming 5% fewer device > resources when compared to MAX+PLUS II software. For more details refer > to the Quartus II Handbook Chapter : Quartus II Design Flow for > MAX+PLUS II Users at > http://www.altera.com/literature/hb/qts/qts_qii51002.pdf. > > In the Quartus II software you might want to try changing the Analysis > & Synthesis Optimization Technique setting from the default of "Speed" > to "Area" to try to solve your fitting problem. I also encourage you to > submit a service request at mysupport.altera.com so we can look into > your problem specifically. > > I hope this helps. > > Regards, > > Rob Kruger > Altera Software Marketing > Many thanks for your reply and for the others here. I apologise for not looking harder. It wasn't immediately obvious that I could still get licenses for obsolete software and indeed to be able to download obsolete software. It is a bind that it is time limited though but good that I can get another licence file if I change machine. Many thanks again.Article: 83943
"David" <david.nospam@westcontrol.removethis.com> wrote in message news:pan.2005.05.09.21.18.14.67000@westcontrol.removethis.com... > On Mon, 09 May 2005 15:03:28 +0100, Fred wrote: > >> I have a Maxplus design which is a year or more old which was compiled >> with >> Maxplus. So far so good. I am required to make a small alteration. >> >> The licence has expired and Maxplus seems obsolete so my only option is >> to >> download Quartus. >> > > A quick look at the Altera website gives links for downloading Maxplus and > getting a license for it. They make it clear that they recommend moving > to Q2, and that Maxplus is for legacy designs only, but they also make it > simple to download and license. Did you actually try getting a new > license, or did you just assume that "obsolete" means "unobtainable" ? > Guilty! > http://www.altera.com/support/licensing/free_software/lic-max2baseline.jsp > > >> Oh dear - I have never come across such a long winded process to convert >> things to Quartus. >> >> After all the changes - Lo and behold it won't fit! >> >> Is this called progress? > > Given that Altera estimates a slight improvement on fitting on average > when switching from Maxplus to Q2, I'd guess their support people would be > interested in seeing the design and finding out what went wrong. If requested I'd be happy to send them the design. > >> >> What on earth is wrong with allowing the use of "outdated" software for >> "outdated" designs? >Article: 83944
"Steve" <nospam@bit.bucket> wrote in message news:d5okqe$jmt$1@grandcanyon.binc.net... > Fred wrote: > >> I have a Maxplus design which is a year or more old which was compiled >> with >> Maxplus. So far so good. I am required to make a small alteration. >> >> The licence has expired and Maxplus seems obsolete so my only option is >> to >> download Quartus. >> >> Oh dear - I have never come across such a long winded process to convert >> things to Quartus. >> >> After all the changes - Lo and behold it won't fit! >> >> Is this called progress? >> >> What on earth is wrong with allowing the use of "outdated" software for >> "outdated" designs? > > Fred, > And if you even have problems getting a new license for the MaxPlus, as > others > suggest.... > > An easy work around is to simply set back the date on your computer. Has > it's problems, but works fine here for getting MaxPlus to run. (You won't > want > to have "email" simultaneously running on the same machine, for example.) > You may want to get a copy of "touch" off the 'net to mess with source > file time & dates to solve any file time dependency issues. Take a look at > the license.dat file -- found it my Max II install directory, YMMV -- > to see what the expiration date is to see how far back you need to push > your > clock. > My experience was that Maxplus was very touchy about dates and was smart enough to recognise "turning the clock back". Mine was an experience with Win ME where 2 files were dated some time in the future on a genuine OEM installation disk which came with the PC.Article: 83945
"Ben Twijnstra" <btwijnstra@gmail.com> wrote in message news:GXPfe.58352$0v1.26164@amsnews02.chello.com... > Hi Fred, > >> The licence has expired and Maxplus seems obsolete so my only option is >> to >> download Quartus. > > That's nonsense. If you have a valid subscription, Altera will still give > you Maxplus features in the license. If the features were not in your > latest license, you can simply request them. > > Best regards, > > > Ben > I was using Baseline for which the license expires after 6 months.Article: 83946
A piece of advice, use SPI interface (if you have one in your ARM micro)
and slave serial programming (PROG, DI, CCLK,DONE) it's far more
simplier not to mention that software is trivial (just open the
bitstream anf fire to the SPI byte by byte, you don't even need to strip
the header of the file, it will self synchronize)
if you are using this interface (jtag) for anything else than
programming the fpga then discard my post.
Aurash
jeycrisis wrote:
>Hello, I want to configure a Spartan 3 with an ARM controller
>comporting several GPIO pins (0-3,3v), from which I use 4 to drive the
>JTAG controller of the FPGA.
>I tried a basic configuration which only reads the IDCODE of the
>device, but the value seen on TDO is not what is excepted, altough a
>green led indicating that the device is properly configured becomes
>active.
>Moreover, I tried to configure the device with xsvf and it stops
>rapidly with an error, because the TDO value mismatch.
>Has anyone experienced these problems? Do we have to take care of other
>things?
>NOTE: to configure the device with JTAG, I reproduced the state machine
>driven by TMS and TCK
> I checked at the oscilloscope that the sequencing was correct
>with respect to the state machine,
> the only problem is the mismatch on TDO.
> For the IDCODE = 01001, I ran first in SHIFT-IR state and
>produced 1, 0, 0, 1, 0 on the TDI line
> After that I ran in SHIFT-DR state, and clock TCK 32 times,
>reading TDO at each edge
>
>Thank you very much for your help, if anyone has a working detailed
>example about this JTAG programming
>
>
>
--
__
/ /\/\ Aurelian Lazarut
\ \ / System Verification Engineer
/ / \ Xilinx Ireland
\_\/\/
phone: 353 01 4032639
fax: 353 01 4640324
Article: 83947Thank You all for the answers, I have already read the XAPP You mentioned, of course they help, but my feeling is that I am missing something about basic delay computations and misusage of design Tools and to cover this I asked help to the forum. Thanks GianniG Symon wrote: > "John M" <statepenn99@gmail.com> wrote in message > news:1115660749.715831.309210@o13g2000cwo.googlegroups.com... > > GianniG, > > > > I know this doesn't really answer your question, but why are you > > dividing down a 500 MHz clock via the DCM to run at 250 MHz internal? > > > Because that's what his ADC provides. 500MHz sampling rate. > > > > Distributing a 500 MHz clock on the board wastes power not to mention > > the EMI issues. In addition, I would imagine the Xilinx DCM adds > > jitter via the divide? Why not use a 250 MHz reference, or better yet, > > multiply up a 125 MHz reference?. > > > Because he doesn't want a sampling rate of 125MHz, he wants 500MHz. He's > doing exactly the right thing, maybe XAPP685 would help? Or XAPP268? > Cheers, Syms.Article: 83948
Hello Guys, I have to divide an clock by 2.5. I cannot use the DCM of virtex 2 pro has my clock is 10 MHZ which is too less for the DCM to handle. I think this division can be done using state machine (posedge and negedge).....but i cannot figure out on what state should i derive the clock and how many state are required?? Can any one please provide suggestions thanks and regards williamsArticle: 83949
mk schrieb:
> Apparently you do speak about A's marketing messages. Don't you think
> it's a little bit silly to hide behind a non-X domain to call A
names?
> I expected better from you and X to be frank.
???
1. Peter is well known - he doesn't need to hide hisself
2. if you read carefully, he signed in his first answer with
"Peter Alfke, Xilinx Applications."
3. do you have any "reasonable" comment on Peters answer ?
Jochen
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