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Hai all,
I heard that the SOFT CPU's have wide range of benefits than
the HARD CPU's. if so, then why still HARD CPU's are preferred.
plz let me know the answer.
regards,
kishore
Article: 82626simon.stockton@baesystems.com wrote: > Didn't understand about domain name either !!! I think he's implying that military equipment contractor (BAE Systems) == doesn't have to scrimp on a potentially undersized FPGA to save (literally) a buck. Makes sense to me ;-)Article: 82627
As mentioned before the issue is not about money but about the availavility of a specific COTS board, albeit with a potentially limiting FPGA XC2VP30 on it. See previous post. Thanks to everyone who has contributed, it looks like there still is a risk about fitting ABC & D in the XC2VP30 but it is smaller that perhaps I first understood. SimonArticle: 82628
"Erik Walthinsen" <omega@pdxcolo.net> schrieb im Newsbeitrag news:425F5935.1010009@pdxcolo.net... > simon.stockton@baesystems.com wrote: > > Didn't understand about domain name either !!! > > I think he's implying that military equipment contractor (BAE Systems) its funny that BAE systems appeared again today during my re-search, namly BAE holds 35% of MBDA and an email from MBDA.fr domain is listed as project coordinator for the dynamically reconfigurable FPGA project www.reconfig.org funnyly there is confusing presse announcement from Atmel (a partner of reconfig org project) from 5th March 2005 http://www.atmel.com/dyn/corporate/view_detail.asp?ref=&FileName=celoxica_3_7.html&SEC_NAME=Product about is some new product to be expected later this year, but unclear if thats hardware or just new tools. > == doesn't have to scrimp on a potentially undersized FPGA to save > (literally) a buck. > > Makes sense to me ;-) :) correct - for an system to be used in mission critical leave at least 10% free. To the original poster: even saying that with 80% you can expect some trouble, I am also sure that it is actually possible to FIT the ABCD into the target device, specially if D is delivered as HDL source code, you just may have to use synplify or physical synthesis to get better fit, and again this may not be needed at all, as the slice count for ABCD may drop by large % from the sum of A+B+C+D my wording isnt perfect english as english is the only human language from the 5 I speak that I havent learned at all. I just had to read the datasheets and learned the english language by guessing the meaning. I have also written a disassembler, Processor ISA description and partial description of the on chip peripherals document by reading 64K binary memory dump (and knowing nothing more than that 64k binary data) - the chip was CCU3000 and my learned (by reading binary dump) knowledge was quite correct as I later got the datasheets as well and compared :) Antti who is hitting 40 (decimal) on April 21 and has never had the joy to enjoy a paid vaccation is looking forward in the hope to be afford a real vaccation with the family - target goal is set for 2006. Thats my dream antti@truedream.org comments are welcome in my guestbook http://www.truedream.org/guestbook PS I am offline for the next 10 days.Article: 82629
On Thu, 14 Apr 2005 07:32:52 -0700, Mike Treseler wrote: > Reinier wrote: > >> I'm looking for a freeware or low cost program do document and >> illustrate the signal processing flow in my FPGA design. I'd like to >> use building blocks like adders, multipliers, memory, busses etc. What >> do you guys use to make some nice looking pictures? I don't want to >> spend days learning Corel Draw or something huge like that. > > Open office and dia are the best of the free, but > you will spend many days to get the first > "nice looking picture" out of the printer. I haven't tried it yet, but I gather that Open Office 2 (solid beta available) has better flowcharting functionality. > > Unless you have a paying audience for your artwork, > consider sketching the block diagram in your notebook > and spend the time you save cleaning up your > source code/schematic and simulation testbench. > > -- Mike TreselerArticle: 82630
Marc Randolph wrote: <-- snip --> > X's are obviously don't cares. Looks ok... I would have it done by myself if working for Xilinx ;-) > > BTW, I neglected to mention something on my original reply about the > configuration time: it is only that low (10 msec) if you can really > feed a byte to the part on every clock cycle. If you are driving the > selectMAP from a microprocessor, that may not be possible since it can > take them many cycles for each bus access. Right! I did that with a spartan2, and [MV MV SUB BEQ] @11MHz led to a 700ms configuration time... awful, but this was not a big deal. This time the idea is to use the ICAP port, when PR will be documented. And you know what? The bottleneck will be the nor flash I'm reading from! > > Marc >Article: 82631
Hi Simon, there is some risk that it may require some tweaking to get it fit and work. But it should defenetly be possible to fit. If XST synthesis is not good enough better synthesis tool may be needed. But try to the MAP report for for ABC when mapped together, and check how much the slice count drops for ABC from A+B+C. If the slice count doesnt drop and the and adding D would not also not yield to better slice utilization ratio, then there could be fit problem. Antti <simon.stockton@baesystems.com> schrieb im Newsbeitrag news:1113547216.554393.163910@l41g2000cwc.googlegroups.com... > As mentioned before the issue is not about money but about the > availavility of a specific COTS board, albeit with a potentially > limiting FPGA XC2VP30 on it. > > See previous post. > > Thanks to everyone who has contributed, it looks like there still is a > risk about fitting ABC & D in the XC2VP30 but it is smaller that > perhaps I first understood. > > Simon >Article: 82632
Hi (hai means "shark" in my native language) 1 your question doesnt have an answer. 2 and your assumptions are not correct. 3 and if you keep using an identy like "teen" what hardly is your name and wording in style 'Hai', 'plz' then you hardly will get answers to anything you ask. If you dont understand what I mean then it would be of benefit for you to go back to school and learn there something. 4 if you do not get upset to what I said above and do some homework then you will be able to correct your wrong assumptions and answer your question yourself. antti "teen" <nkishorebabu123@yahoo.com> schrieb im Newsbeitrag news:1113544130.628433.67240@o13g2000cwo.googlegroups.com... > Hai all, > I heard that the SOFT CPU's have wide range of benefits than > the HARD CPU's. if so, then why still HARD CPU's are preferred. > > plz let me know the answer. > > regards, > kishore >Article: 82633
"strayblue" <strayblue2003@yahoo.com-dot-cn.no-spam.invalid> schrieb im Newsbeitrag news:n5udnQdoZ_Ct1cLfRVn_vQ@giganews.com... > I think your conclusion about three kinds of people is very > classical.I hope that we will have more intercommunion. almost ROTFL, I hope it too. and I also hope there is nothing classical about me ;) at the uni some professor's where a little annoyed about me: "comes to my class, falls a sleep, wakes up to correct an error on the whiteboard and continues to sleep" - it was almost about that. I did quit then... Antti > > Antti Lukatswrote: > "strayblue" <strayblue2003@yahoo.com-dot-cn.no-spam.invalid> > schrieb im > > Newsbeitrag news:lt6dnd2PNq8vYcbfRVn_vg@giganews.com... > > Thank you very much,I will learn to do it,and will do it better. > > > thats better attitude, I belive that if you do, you can do it. > better. > > The links I provided do not give anything quite ready to use, just > those > starting points known to me. Hopefully there was some usefulness in > it. And > hope you didnt mind my writing style, I am very open, so I say what I > think. > So get a Smile and start doing. And try keep smiling :) > > Antti > BTW I am at the moment quite engaged with JTAG from different aspects, > both > from master and slave side and also in supporting software, so if you > make > something better, please keep me posted, or better would be if there > would > be some result from your work that could be used by others. > > > > [[/quote:a8cad9cfa2] >Article: 82634
John Larkin wrote: > On 13 Apr 2005 09:12:51 -0700, "Andy Peters" <Bassman59a@yahoo.com> > wrote: > > >>I'm sure others have this problem ... >> >>Is there a tool that'll let one view and hopefully print a schematic >>done in the old Xilinx F2.1i schematic tool? The new stuff doesn't >>want to know about the old stuff, and worse is that you can't even >>install 2.1i on an XP machine. (Yeah, that'll teach me to upgrade.) >> >>I don't want to do anything with this schematic other than view it. >>I'm doing a new board sorta based on an old design, and the new design >>will of course be in VHDL rather than as a schematic. >> >>Ideas? >> >>-a > > > > What the world needs is a standard schematic file format. > > Our policy now is to release PDFs of all schematics with the designs, > so at least it's easy to see what's there. > > John > Well... wasn't it EDIF that was supposed to become one (ANSI, IEC, EN standards)? The only thing is, that proprietary means money for vendors that own the format... keep the customer dependent on the solution. EGArticle: 82635
Praveen wrote: > If you have linux/unix -- Xfig is the tool..I have never used any other > tool after trying it. You have to spend an hr or so learning it. > Here is how to use it on windows: http://www.cs.usask.ca/grads/wew036/latex/xfig.html cygwin is available at: http://www.cygwin.com/ or alternatively you can try WinFig at:http://user.cs.tu-berlin.de/~huluvu/WinFIG.htm EG.Article: 82636
Using the Xilinx Project Navigator, I created a project and added a package definition (vhd-file) at the very top level. Inside this package I defined some types of integers, signed and unsigned. I included this package in all other vhd-files of the project with "use my_package.all". All syntax checks were successfull. Now the problem: When I automaticaly create a Schematic or a Testbench file, the package definitions seem to be ignored: all ports defined in the original vhd-file as integers (8bit) are now only std_logic. This can be seen directly in the schematics drwaing, or the testbench grafical display or the testbench vhd-file. I get an error message saying: "Compiling vhdl file ##_top.vhd in Library work. ERROR:HDLParsers:3014 - ##_top.vhd Line 9. Library unit my_package is not available in library work. WARNING:HDLParsers:3465 - Library as no units. Did not save reference file xst/work/hdllib.ref for it." Does anyone know where the error is located? -- __________________________________________ Dipl.-Ing. Hanns-Walter Schulz TU Braunschweig Institut fuer Luft- und Raumfahrtsysteme Institute of Aerospace Systems Hermann-Blenk-Str. 23 Tel.: ++49 531 391 9968 D-38108 Braunschweig Fax: ++49 531 391 9966Article: 82637
Hello, thanks for the answers. I am sorry, that i didn't give you enough information. I am using the Xilinx XCV 800bg432-4 and i am also using VCD and sdf files. I know the FPGA is a really small one, but i need it for researching purposes only. Yesterday I found some information in the Xilinx Answer Database. The accuracy seems to be in the range of 10 % (PRODUCTION/FINAL). Here is the link to the Article: http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=14285 parityArticle: 82638
could anyone please explain me the difference between the buffers IBUF OBUF BUFGP BUFGDLL BUFT etc available in XILINX FPGA.Article: 82639
"vlsi_learner" <bajajk@gmail.com> schrieb im Newsbeitrag news:1113563692.919736.183860@f14g2000cwb.googlegroups.com... > could anyone please explain me the difference between the buffers IBUF > OBUF BUFGP BUFGDLL BUFT etc available in XILINX FPGA. > RTFM anttiArticle: 82640
vlsi_learner wrote: > could anyone please explain me the difference between the buffers IBUF > OBUF BUFGP BUFGDLL BUFT etc available in XILINX FPGA. Just have a look at <Xilinx-Install-Dir>\doc\usenglish\books\docs\lib\lib.pdf JochenArticle: 82641
Jochen wrote: > vlsi_learner wrote: > >>could anyone please explain me the difference between the buffers > > IBUF > >>OBUF BUFGP BUFGDLL BUFT etc available in XILINX FPGA. > > > Just have a look at > <Xilinx-Install-Dir>\doc\usenglish\books\docs\lib\lib.pdf > > Jochen > or... http://toolbox.xilinx.com/docsan/xilinx6/books/docs/lib/lib.pdf EGArticle: 82642
Hi out there,
maybe someone can give her/his opinion:
I have the following assignment in my top level file:
entiy top is
port ( ...
Sdram_csn : out std_logic_vector(1 downto 0);
...
);
end top;
architecture rtl of top is
...
begin
Sdram_csn <= ('1' & l_sdram_csn);
...
end rtl;
When performing a functional simulation with Modelsim
Sdram_csn gets "10" at a certain point. (Reset: Sdram_csn="11")
The Timing Simulation with Modelsim instead shows that
Sdram_csn gets "11".
Is it possible that l_sdram_csn is '0' and yet
Sdram_csn gets "11" at the pin ? I tried to make the signal "l_sdram_csn"
visible in Modelsim, but the problem is that it is spread over
various slices after place and routing...Any tipps to find that signal ?
Rgds
André
Article: 82643On Thu, 14 Apr 2005 22:48:50 -0700, teen wrote: > Hai all, > I heard that the SOFT CPU's have wide range of benefits than > the HARD CPU's. if so, then why still HARD CPU's are preferred. > > plz let me know the answer. > > regards, > kishore You heard wrong. A hard CPU is faster and cheaper then a soft CPU. By cheaper I mean they take much less die area then an equivalent soft CPU. The downside of the hard CPUs is that they are only available in high end FPGAs like the Virtex2P and Virtex4. The cheaper FPGAs like the Spartan3 don't have embedded CPUs. If you needed a processor in a Spartan3 you would have to use a soft CPU, however you want to use one that was much simpler then the PPC in the Virtex2Ps and 4s. If you implemented a full PPC you would use so many slices that you would negate the cost advantage of the Spartan3.Article: 82644
Engineering Guy wrote: > or... > http://toolbox.xilinx.com/docsan/xilinx6/books/docs/lib/lib.pdf I like this one best: http://toolbox.xilinx.com/docsan/xilinx5/data/docs/lib/lib0027_11.html or this for Virtex-4: http://toolbox.xilinx.com/docsan/xilinx6/books/data/docs/v4lsc/v4lsc0013_4.html cu, SeanArticle: 82645
if i am having a set of modules which reference some common control registers and each of these modules can read or write to these registers then there is a severe problem of 'bus' first of all and secondaly the 'mode' of the control registers(INOUT??). Is there any design reference or document that may be of help to me?Article: 82646
Look at creating a .do macro with Modelsim that adds the signal with the add wave command. Look at the syntax that the input and output signals are declared with in the signals window when you've simulated and follow that format.Article: 82647
thanks a lotttArticle: 82648
Cost!!!! That is the main reason why Hard CPU's are still used. They are cheaper.... a Phillips Arm 7 32 bit CPU is about $3.50 in quantity. An FPGA with a similar size softcpu like a Microblaze is about $10. Soft CPU's are used for performance. They take advantage of the FPGA's logic and use parallelizm to speed up operatiations (ie multipuly two 32 bit numbers in a single clk cycle). A hard CPU would take 4 or more clk cycles to multiply two 32bit numbers. So SoftCPU's used with FPGA logic can have a higher performance than an equivelent hardCPU. So it totally depends on your application to whether a soft or hard CPU is for you. EricArticle: 82649
SoftCPUs also can have custom peripherals (ie 5 x UARTs, 6 x SPI bues, 20 x I2C bues). With a Hard CPU your stuck with what the manufacturer gives you. Personally SoftCPU's are more fun.... custom home brewed CPU's are exciting!!! Writing a VHDL model of a CPU is the closest to designing my own CPU I'll ever get. There is something exciting about that!!!! Eric
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