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When a DCM is locked, can I be sure that CLK0 and CLK2X are perfectly phase-aligned? (Virtex-4 DCM_BASE Unisim model seems to show this.) Actually, I want to register a IOB signal on CLK0 and use it with an internal CLK2X clock. The problem is: how to know which is the 'good' rising edge of CLK2X ? Can I drive the IOB register with CLK2X and enable it with the condition (CLK0='0') ? I think I don't respect the EN hold time of the register. And the compiler may shout on me for testing a clock! Maybe a 1 bit counter that starts on LOCKED='1' has the same waveform as CLK0 and will not produce a gated clock warning? Thanks for help, StephaneArticle: 81801
Hi,
I'm a beginner in VHDL.
I'm trying to implement the xess-sdram controller. When I try to
simulate it, I keep getting errors from modelsim like: 'Types do not
match..'. But they are the same type.
I stripped it now down to nothing else than the controller and some
signals in the file. But still the errors occure. Any hints?
for example:
----8<----
...
component sdramCntl is
generic (
...
);
port (
...
sDIn: in unsigned(DATA_WIDTH-1 downto 0); -- data from SDRAM
sDOut: out unsigned(DATA_WIDTH-1 downto 0); -- data to SDRAM
);
...
signal sdram_data_in : unsigned(SD_DATA_BUS_WIDTH-1 downto 0);
signal sdram_data_out : unsigned(SD_DATA_BUS_WIDTH-1 downto 0);
...
port map (
...
sDin => sdram_data_in,
sDOut => sdram_data_out,
...
);
---->8----
Error message from modelsim:
----8<----
...
# WARNING[1]: memory_tester_2_top.vhd(183): Types do not match for port sdin
# WARNING[1]: memory_tester_2_top.vhd(183): A use of this default
binding for this component instantiation will result in an elaboration
error.
# WARNING[1]: memory_tester_2_top.vhd(183): Types do not match for port
sdout
# WARNING[1]: memory_tester_2_top.vhd(183): A use of this default
binding for this component instantiation will result in an elaboration
error.
...
---->8----
Thanks
André Schieleit
Article: 81802André, What are the values of DATA_WIDTH and SD_DATA_BUS_WIDTH ? What is the generic part of your component for ? Nicolas Pinault André Schieleit a écrit : > Hi, > > I'm a beginner in VHDL. > I'm trying to implement the xess-sdram controller. When I try to > simulate it, I keep getting errors from modelsim like: 'Types do not > match..'. But they are the same type. > I stripped it now down to nothing else than the controller and some > signals in the file. But still the errors occure. Any hints? > > for example: > ----8<---- > ... > component sdramCntl is > generic ( > ... > ); > port ( > ... > sDIn: in unsigned(DATA_WIDTH-1 downto 0); -- data from SDRAM > sDOut: out unsigned(DATA_WIDTH-1 downto 0); -- data to SDRAM > ); > ... > signal sdram_data_in : unsigned(SD_DATA_BUS_WIDTH-1 downto 0); > signal sdram_data_out : unsigned(SD_DATA_BUS_WIDTH-1 downto 0); > ... > port map ( > ... > sDin => sdram_data_in, > sDOut => sdram_data_out, > ... > ); > ---->8---- > > Error message from modelsim: > ----8<---- > ... > # WARNING[1]: memory_tester_2_top.vhd(183): Types do not match for port > sdin > # WARNING[1]: memory_tester_2_top.vhd(183): A use of this default > binding for this component instantiation will result in an elaboration > error. > # WARNING[1]: memory_tester_2_top.vhd(183): Types do not match for port > sdout > # WARNING[1]: memory_tester_2_top.vhd(183): A use of this default > binding for this component instantiation will result in an elaboration > error. > ... > ---->8---- > > Thanks > André SchieleitArticle: 81803
Hi Victor, the quality of your VHDL code definetely influences the achievable frequency in your design. Even the best VHDL synthesis tools are not able to generate a 'good' netlist from 'bad' code. For the moment you can try to have somebody experienced with VHDL taking a look at your code. Furthermore, you should do a detailed Critical path analysis. I might be that just a tiny piece of VHDL causes a problem (maybe a RAM implemented out of registers etc). You also can try a better synthesis tool such as Synplify Pro from Synplicity. Regards, PhilArticle: 81804
Hi, in QuartusII v4.2 SP1 I have the following problem: My top level file is a schematic file called "H_top.bdf" In this top level file I have several symbols, for example "cache_search.bsf". The component cache_search is also a schematic file from which I created a .vhd file in Quartus so that I have one "cache_search.bdf" and one "cache_search.vhd" which are of course identical. Now in my top level file I include under PROJECT --> ADD/REMOVE FILES IN PROJECT the file "H_top.bdf" Under USER LIBRARIES I include the directory in which the "cache_search.bdf" and "cache_search.vhd" are included. When I click on the symbol "cache_search.bsf" in the top level schematic "H_top.bdf" file the "cache_search.vhd" is opened. I would like to choose whether to look at the "cache_search.vhd" or the "cache_search.bdf" ... How can I do that ? Any suggestions are appreciated. Rgds AndréArticle: 81805
"Antti Lukats" <antti@openchip.org> schrieb im Newsbeitrag news:d2hlvl$4t9$05$1@news.t-online.com... > Hi > > early beta version is available for immediate downloads > http://gforge.openchip.org/projects/fpgafreqmeter/ > uups as usually something went wrong the initial 1.0.0 release did not includes dlportio drivers this is fixed in 1.0.1 release and driver download is available separatly as well. anttiArticle: 81806
You'll need a
> little state machine to manage it.
>
> John
If he use a dual port data ram he will not need a state machine
1 port for reading the data to increment and the other to write the new
value
----------------------------
adress_read <= data;
value_to_increment <= histogram(adress_read);
adress_reg<= adress_read;
value_incremented <= std_logic_vector(unsigned(value_to_increment) +1);
adress_write <=adress_reg;
histogram(adress_write) <= value_incremented;
-------------------------------
something like that should be ok.
with histogram declaration has an array :
--------------------------------
type mem is array (0 to 255) of
std_logic_vector(7 downto 0);
signal histogram : mem;
----------------------------------
alexis
Article: 81807
Hi,
I have an fpga which is accessed from ARM as a
memory-mapped device.
A register in fpga is used to drive a I2C bus connected to
a device . Two bits in the register represent clock and
data lines of the bus.
When I try to write into this register from ARM software as
shown below, write is not happening. ARM is running at 48 Mhz.
int* reg = 0x44400030;
*reg = 0x3;
The above code is not able to modify the register.
But when I write using Lauterbach trace32 command as shown below, it
works.
data.set SD:0x44400030 %LE %LONG 0x3
What could be the reason ?
Please advise.
thanks
shankar
Article: 81808On 1 Apr 2005 04:25:56 -0800, <shankar.vk@gmail.com> wrote: > int* reg = 0x44400030; > *reg = 0x3; > [...] > > What could be the reason ? Possibly, missed "volatile" qualifier. Vadim BorshchevArticle: 81809
Stephane wrote: > When a DCM is locked, can I be sure that > CLK0 and CLK2X are perfectly phase-aligned? Howdy Stephane, There is no such thing as "perfectly aligned" in the real world! :-) The datasheet specs "CLKOUT_PHASE", the phase offset between any DCM outputs, just for this. In general though, Xilnx says that you can treat the phase alignment of the outputs as close enough that you can transfer data between them. Many people, myself included, have succesfully done just that. There have been a few reports of problems doing this when there is extra jitter on the input clock, or even jitter induced from nearby pins. > Actually, I want to register a IOB signal on CLK0 and use it > with an internal CLK2X clock. The problem is: how to know which > is the 'good' rising edge of CLK2X ? Since CLK0 doesn't change on the falling edge of CLK2X, how about using that falling edge to sample CLK0 and determine its phase? > Can I drive the IOB register with CLK2X and enable it with the > condition (CLK0='0')? I think I don't respect the EN hold time of > the register. And the compiler may shout on me for testing a clock! Try it and see what the tools say - that's what timing analyzer is for. When a clock goes to non-clock destinations, I believe you have the same guarantees as general logic: no hold time problems. But with the global clock delay as large as it is on the V4, I'm a little curious if that's still the case. > Maybe a 1 bit counter that starts on LOCKED='1' has the same > waveform as CLK0 and will not produce a gated clock warning? If it is an option, generating the clock enable with a toggling flop in the CLK2X domain from the start is the best option. Then there is no chance of prop delay, setup, or hold time issues. Have fun, MarcArticle: 81810
I am looking for a morphology operator that will detect the concavity of binarized shapes. And, if any one is in the know, an explanation of the term "bulk hull", and where it came from. Very mysterious to me. Thanks, Brad b r a d @ a i v i s i o n . c o m 415-661-8068Article: 81811
On Fri, 1 Apr 2005 05:33:45 -0800, "Brad Smallridge" <bradsmallridge@dslextreme.com> wrote: >I am looking for a morphology operator that will >detect the concavity of binarized shapes. And, if >any one is in the know, an explanation of the term >"bulk hull", and where it came from. Very mysterious >to me. Is "bulk hull" the same as "convex hull"? That's the form you get by (conceptually) pulling a piece of string tight around the shape, so that it hugs all the external convex parts and stretches across any concave regions of the shape's outline. AIUI the concavity is 1-(A/H) where A is the shape's area and H is the area of its convex hull. But I could easily be wrong - it's ages since I did any of this stuff. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 81812
When you diuble click on a symbol in the bdf the behavior is to open the design file that was used as part of the compilation. In this case it was the file with the vhd extension (as a vhd extension has a higher priority than a bdf extension). If you want to open the bdf instead do a File Open, traverse to the directory which has te bdf file and open it. If you want the bdf file to be used for compilation, add the bdf file explicitly to the file list. Hope this helps, Subroto Datta Altera Corp. "ALuPin" <ALuPin@web.de> wrote in message news:b8a9a7b0.0504010346.7f9b3bb0@posting.google.com... > Hi, > > in QuartusII v4.2 SP1 > I have the following problem: > > My top level file is a schematic file called > "H_top.bdf" > > In this top level file I have several symbols, for example > "cache_search.bsf". > > The component cache_search is also a schematic file from which > I created a .vhd file in Quartus > so that I have one "cache_search.bdf" and one "cache_search.vhd" > which are of course identical. > > Now in my top level file I include under PROJECT --> ADD/REMOVE FILES > IN PROJECT the file "H_top.bdf" > Under USER LIBRARIES I include the directory in which the > "cache_search.bdf" > and "cache_search.vhd" are included. > > When I click on the symbol "cache_search.bsf" in the top level > schematic "H_top.bdf" file > the "cache_search.vhd" is opened. > I would like to choose whether to look at the "cache_search.vhd" or > the > "cache_search.bdf" ... > > How can I do that ? > > Any suggestions are appreciated. > > Rgds > AndréArticle: 81813
Hi is it only me that every time I try to use some a little advance feature I trap into some Xilinx bug?? 1) implementing SRL16 based serial divider, found bug in MAP 2) implementing JTAG Hub found synthesis bug 3) implementing frequency meter in FPGA found P&R bug with Virtex 4 devices for 1 and 2 there are simple workarounds those are not fatal. but with the Virtex 4 bug, thats a bit scarier a simple design with 16 counters connected to 16 pin locked GCK inputs. P&R fails, saing one signal is not fully routed the same desing with 16 clocks works Ok for Virtex-2 !!! Virtex 4 has more clocks but what does it help if the tools are broken??? I am about to start a VERY challenging designs that will be housed in several ATCA racks, so far considering V4FX20 as the main FPGA on the boards, but if the V4 support has more issues that we will find too late, than maybe its not to late to reconsider the design to use V2Pro what hopefully has less bugs as it has been in use for longer time. AnttiArticle: 81814
Joseph wrote: > Thanks Vasanth, > > Can you or anyone else reccomend an SMP OS for the Virtex II? > Specifically, I am working on the ML310 board. There isn't much > literature on running both cores at once, so any advice is appreciated. > Currently I am looking at the MontaVista preview kit to see if that > will get me going in the right direction. I think the software will > eventually be fine, but then organizing the FPGA correctly may be a > challenge... anyone do this kind of thing already? > > thanks again The PowerPCs in the Virtex FPGAs do not have hardware support for keeping their caches coherent with each other. Read the memory management section of the user guide for more information on this. Lack of hardware support for cache coherency is a problem if you want to use an SMP OS. You can however run two separate copies of an OS, each with their own memory space. You can also have shared memory regions, but you will have to deal with cache coherency issues in software. Would that solve your problem? Regards, John McCaskillArticle: 81815
Eric wrote: > I just got my copy of ISE 7.1 and noticed that I now have to click through > both the GPL and the LGPL before installing... I don't remember having to > do this before -- does anyone know what changed or was added? > ...Eric Has someone noticed that in feature summary (http://www.xilinx.com/ise/products/webpack_config.htm) it says that WebPack 7.1 would support VirtexE-XCV600E ? But at least I cannot select it from device list. Only same models are available than in previous version (xcv50e-xcv300e). Bug in software or wrong information on the web page or stupid user :) ? .VilleArticle: 81816
Hi Antti, Make sure you open a webcase thingy. I want that stuff fixed when I get around to using those parts!! Seriously, I'd stick with the newer part. You'll find you get better support from Xilinx than on the older parts. Remember, they're trying hard to flog these new devices to their biggest customers who won't be happy with problems like the one you describe. And it looks better on the CV. Cheers, Syms. "Antti Lukats" <antti@openchip.org> wrote in message news:d2jmvr$fcs$02$1@news.t-online.com... > 3) implementing frequency meter in FPGA found P&R bug with Virtex 4 > devices > P&R fails, saing one signal is not fully routed > > the same desing with 16 clocks works Ok for Virtex-2 !!! > Virtex 4 has more clocks but what does it help if the tools are broken??? >Article: 81817
Try this: int* reg = (int*)0x44400030; *reg = 0x3; Regis. <shankar.vk@gmail.com> wrote in message news:1112358355.997835.104340@z14g2000cwz.googlegroups.com... > > Hi, > > I have an fpga which is accessed from ARM as a > memory-mapped device. > > A register in fpga is used to drive a I2C bus connected to > a device . Two bits in the register represent clock and > data lines of the bus. > > When I try to write into this register from ARM software as > shown below, write is not happening. ARM is running at 48 Mhz. > > int* reg = 0x44400030; > *reg = 0x3; > > The above code is not able to modify the register. > > But when I write using Lauterbach trace32 command as shown below, it > works. > > data.set SD:0x44400030 %LE %LONG 0x3 > > What could be the reason ? > > Please advise. > thanks > shankar >Article: 81818
Or this: int* reg = (int*)0x44400030; *reg = 0x3L; Regis (regis@dacafe.com) "RS" <regis@dacafe.com> wrote in message news:CVd3e.43674$AN1.42984@fed1read03... > Try this: > > int* reg = (int*)0x44400030; > *reg = 0x3; > > Regis. > > <shankar.vk@gmail.com> wrote in message > news:1112358355.997835.104340@z14g2000cwz.googlegroups.com... >> >> Hi, >> >> I have an fpga which is accessed from ARM as a >> memory-mapped device. >> >> A register in fpga is used to drive a I2C bus connected to >> a device . Two bits in the register represent clock and >> data lines of the bus. >> >> When I try to write into this register from ARM software as >> shown below, write is not happening. ARM is running at 48 Mhz. >> >> int* reg = 0x44400030; >> *reg = 0x3; >> >> The above code is not able to modify the register. >> >> But when I write using Lauterbach trace32 command as shown below, it >> works. >> >> data.set SD:0x44400030 %LE %LONG 0x3 >> >> What could be the reason ? >> >> Please advise. >> thanks >> shankar >> > >Article: 81819
If anyone is still interested in Transputers, I am now releasing the 1st half of a new FPGA Transputer through email, mostly docs but also an Instruction Set simulator, the C cycle model and Verilog sources for later, all works in progress better than spam I presume see comp.sys.transputer regards all johnjakson at usa dot comArticle: 81820
Hi, I am having trouble finding directive to call a port by different names in ABEL HDL (Xilinx). Could someone let me know? Thanks, PapuArticle: 81821
Hmmmmm, Are all of the posts today in honor of April Fools day? I am having a hard time seeing if these are serious, or not..... AustinArticle: 81822
André Schieleit wrote: > Hi, > > I'm a beginner in VHDL. > I'm trying to implement the xess-sdram controller. When I try to > simulate it, I keep getting errors from modelsim like: 'Types do not > match..'. But they are the same type. > I stripped it now down to nothing else than the controller and some > signals in the file. But still the errors occure. Any hints? > > for example: > ----8<---- > ... > component sdramCntl is > generic ( > ... > ); > port ( > ... > sDIn: in unsigned(DATA_WIDTH-1 downto 0); -- data from SDRAM > sDOut: out unsigned(DATA_WIDTH-1 downto 0); -- data to SDRAM > ); > ... > signal sdram_data_in : unsigned(SD_DATA_BUS_WIDTH-1 downto 0); > signal sdram_data_out : unsigned(SD_DATA_BUS_WIDTH-1 downto 0); > ... > port map ( > ... > sDin => sdram_data_in, > sDOut => sdram_data_out, > ... > ); > ---->8---- > > Error message from modelsim: > ----8<---- > ... > # WARNING[1]: memory_tester_2_top.vhd(183): Types do not match for port sdin > # WARNING[1]: memory_tester_2_top.vhd(183): A use of this default > binding for this component instantiation will result in an elaboration > error. > # WARNING[1]: memory_tester_2_top.vhd(183): Types do not match for port > sdout > # WARNING[1]: memory_tester_2_top.vhd(183): A use of this default > binding for this component instantiation will result in an elaboration > error. > ... You have clipped too much for an answer. But it appears the messages mean that your declaration of the component sdramCntl where it is coded does not match the declaration where it is used. The messages have nothing to do with sdram_data_in/out.Article: 81823
Papu wrote: > Hi, > > I am having trouble finding directive to call a port by different > names in ABEL HDL (Xilinx). Could someone let me know? > > Thanks, > Papu ABEL has a declarations section, which is everything between the module keyword and the Equations keyword. Within the declaration section you can make aliases using the equals sign like: MY_ADDR = [0,1,1,0,1,0,1]; " 6A write, 6B read " Input data shift register ISR7..ISR0 NODE istype 'reg' ; IN_SR = [ISR7..ISR0] ; Where IN_SR is an alias of the vector ISR7..ISR0 and MY_ADDR is a constant vector. Aliases can also be to simple port names like: FRANK PIN istype 'reg' ; george = FRANK ; Hope this helps, GaborArticle: 81824
"Austin Lesea" <austin@xilinx.com> schrieb im Newsbeitrag news:d2jssm$gga2@cliff.xsj.xilinx.com... > Hmmmmm, > > Are all of the posts today in honor of April Fools day? > > I am having a hard time seeing if these are serious, or not..... > > Austin you want some 4/1 ? sorry my posts are not foolish, the bugs i am experiencing are real. That V4 can not handle 16 clocks while V2 can can do it, that made me a bit unsecure about using V4, the tools seem to be to untested ?? what makes me a little happier is that JTAG programming from bit files seem to be unchanged for V2, S3 and V4 the same algorithm seems to work, I was expecting more difficulties http://wiki.openchip.org/index.php/OpenChip:FpgaFreqMeter V4LX support inclusive programming is now also added and tested :) Antti
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