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The little bit I have read about these is that the more complex ones have two parts. The first part allows the user to interrupt the normal booting process and choose a boot device may it be a another boot PROM, flash memory card, or hard drive. The second part is alternative boot PROM. They probably hacked the one on the mother and using a BIOS chip from a motherboard with a similar chip set coded their own. Since the XBox is based on a PC platform, compared to Game Cube and Play Station 2 it probably would be easier to create a mod for the XBox but there is always all that nasty encryption surrounding the DVD-ROM drive. Unless you trying to start a business I would imagine it would be cheaper to buy one and possibly modify the mod kit. DerekArticle: 81851
"Piotr Wyderski": > [,,] > This simple scheme provides sine wave with 17 bits of accuracy, > which can be used directly to feed a quadrature mixer. Another > important property is that the interpolation error near pi/2 is > negative (i.e. forall x . |my_sin(x)| < 1), so there is no need for > guard bits. I have some ideas how to further increase accuracy, > but I am not sure whether I should start developing them, because > 17 bits are far better than any modern digital RF front-end expects. > I have implemented a complete quadrature mixer (not just an NCO) > on a multiplierless Cyclone 1C6 and it occupies only 815 LEs, where > the majority of them is consumed by a 17x16 shared multiplier. Its > top performance is limited by M4K RAMs and for -6, -7 and -8 speed > grades this is, respectively, 255.9 MHz, 226.3 MHz and 197.0 MHz. > [,,] another option might be to simply rotate a point XY by an angle alpha: x(t+1) = x(t)*k1 + y(t)*k2 // k1 = cos alpha y(t+1) = -x(t)*k2 + y(t)*k1 // k2 = sin alpha k1 and k2 might (depending on alpha) have 50% bits set, on average. So if alpha is fixed, and if n is the number of bits in x and y, one complete step is made by 2*n ADDs. An average summand may be x or y shifted right by floor(n/2). The useful calc-precision below LSB(x) or LSB(y) is ceil(lg(n)). So we'd need 2*n*(floor(n/2) + ceil(lg(n))) 1-Bit full-adders: n : 1-bit-fulladders (average) 24: 816 23: 736 22: 704 21: 630 19: 532 18: 504 16: 416 14: 308 12: 240 11: 198 10: 180 8: 128 This method of course has the disadvantage of relying on a fixed alpha per step, and maybe a "zero-phase-counter" (to reset x and y, when t is a multiple of period) is needed. Gruss Jan BrunsArticle: 81852
While creating a new design using EDK, in ADD/EDIT CORES -> PORTS tab Signals can be separated into external ports and internal ports. Does anyone know of any document which explains this? All these ports are internal or external with respect to what??? Which signals should you call internal and which signals should be called external??? Please help.Article: 81853
milind.parelkar@gmail.com wrote: > While creating a new design using EDK, > in ADD/EDIT CORES -> PORTS tab > Signals can be separated into external ports and internal ports. Does > anyone know of any document which explains this? http://www.xilinx.com/ise/embedded/edk_docs.htm In particular, the "Embedded System Tools Reference Guide (EST)" and "Platform Studio Tools User Guide" may be helpful to get an overal feel for EDK. I don't think they specifically answer your question above, but will provide a high-level view of EDK. > All these ports are internal or external with respect to what??? Which > signals should you call internal and which signals should be called > external??? The external ports are the inputs/outputs to/from the FPGA. For instance, if you are using the serial interface (UART), you will have a few of these external ports. These ports should be listed at the top of the MHS file. (see the EST guide for what the MHS file is) The internal ports are the inputs/outputs to/from the top-level modules/pcores in the EDK design. If you look at the MHS file, these are the ports that are listed for each pcore in your design.Article: 81854
Hi, I am trying to use RAMB16_S9 to store some data. Since this is my first time doing this, I am trying to test it to see how it works. I let wr_en = 1 for 256 cycle, and make wr_en = 0 for 256 clk cycle. But I am running into problem. It looks like the data never got written in or something. The data coming out is always 00000000. Can someone help? Thanks. This is what my code look like: main module: counter mycounter (.clk(FPGA_CLK), .write_en(wr_en), .reset(1'b0)); RAMB16_S9 top_ram (.DO(user_DO), .ADDR(11'b00000001000), .CLK(FPGA_CLK), .DI(8'b00001000), .EN(1'b1), .SSR(1'b0), .WE(wr_en), .DIP(DIP), .DOP(DOP)); Counter module: parameter IDLE = 0, WRITE = 1, READ = 2, DONE = 3; always @(posedge clk) begin if (reset) begin count <= 0; write_en <= 1'b0; state <= IDLE; end else begin case (state) IDLE: begin count <= 0; write_en <= 1'b0; state <= WRITE; end WRITE: begin if (count < 255) begin count <= count + 1; write_en <= 1'b1; end else begin count <= 0; state <= READ; end end READ: begin if (count < 255) begin count <= count + 1; write_en <= 1'b0; end else begin count <= 255; state <= DONE; end end DONE: begin state <= DONE; end default: state <= IDLE; endcase end endArticle: 81855
Try this link http://ece.gmu.edu/courses/ECE449/viewgraphs_S05/449_lecture3.html It has some information about how to use the memory. Although it is not in verilog (the course is about VHDL), it should be helpful. MilindArticle: 81856
ModelSim needs an env variable called LM_LICENSE_FILE which points to the license.dat file. When you install ModelSim as administrator I guess that this env. variable is installed in the private space of the administrator. Have you verified that LM_LICENSE_FILE is defined as system variable and not user variable? Can you see it when you log in as a normal user? Eric Nemesis wrote: > Hi all, > I'm trying to install ModelSim XE (both II and III) on a WindowsXP box > but I can't get it working when I login as a simple no privileged User. > > I installed the software logged as Administrator, and I loaded the > license.dat file, in this situation the software works correctly, but > when I use the computer as a normal User (I'm not the Administrator of > that computer) ModelSim doesn't work, It prints and error like this: > > ---------------------------------------------------------------------- > Your evaluation license has been invalidated because > a text file necessary for licensing cannot be written. > > In order to continue with the evaluation of Modelsim you will need to > correct the error, re-install the evaluation copy and re-request > an evaluation license from Model Technology. > > Evaluation Error: 104 > ---------------------------------------------------------------------- > > I also changed the permissions on the ModelSim folder, and gave full > controll on it, but nothing changed. > > Is there a way of using ModelSim not being Administrator on WindowsXP?Article: 81857
Thanks, that was helpful. MilindArticle: 81858
How do you connect custom IP cores to Microblaze using IPIF? Should all interface signals for the IPIF be on the top level entity of the custom IP Core? What if all the signals are not required and some of these signals are left unconnected? Please help. MilindArticle: 81859
v_mirgorodsky@yahoo.com wrote:
> ... if you put special constraints on SRL16 block and
> trigger than they may got to the same slice, but this leads to
> completelly unportable code even between Xilinx family chips.
>
> Design with pure triggers runs fast enough and I don't have any clue
> why SRL16's are not.
Sounds like two good reasons to keep the design generic.
I expect that the SRL regs are not quite as fast
as the standard registers.
-- Mike Treseler
Article: 81860Mike Treseler wrote: > v_mirgorodsky@yahoo.com wrote: > >> ... if you put special constraints on SRL16 block and >> trigger than they may got to the same slice, but this leads to >> completelly unportable code even between Xilinx family chips. >> >> Design with pure triggers runs fast enough and I don't have any clue >> why SRL16's are not. > > > Sounds like two good reasons to keep the design generic. > I expect that the SRL regs are not quite as fast > as the standard registers. Maybe someone from Xilinx can comment on that - does using SRL16's have a real speed impact ? -jgArticle: 81861
"Mike Treseler" <mike_treseler@comcast.net> wrote > I expect that the SRL regs are not quite as fast > as the standard registers. > I found that on an old 2V1000 design that I did. I was using plenty of SRLs to compensate for filter delays, but I had to stick an extra register on the output of each one to get decent speed.Article: 81862
Does such an animal exist? I have looked around but as of yet Ive not seen one. Saw reference to a couple of non-open ones. A x86 core would be nice too, but i doubt ill find one of them due to IP rights... I know performance would be dismal, but this is just for some experimentation i want to do. ( and no, im not up to 'rolling my own' version of something that complex )Article: 81863
Ziggy <Ziggy@TheCentre.com> writes: > Does such an animal exist? I have looked around but > as of yet Ive not seen one. Saw reference to a couple > of non-open ones. > > A x86 core would be nice too, but i doubt ill find > one of them due to IP rights... There's probably a lot less problem with IP rights on the x86 than on the PowerPC. The x86 has been around long enough for the patents to expire. (Maybe not on things like MMX and SSE, but you didn't indicate that you needed those.)Article: 81864
Hello: I have seen a couple of Altera development kits that allow you to program the FPGA using a USB port (instead of JTAG). This is accomplished using a usb interface chip such as one from ftdi chip and a cpld from altera (such as max 7000, part# EPM7064). Can anyone tell me where I can obtain the programming files to program the max 7000? Thanks in advance/ JSArticle: 81865
> Maybe someone from Xilinx can comment on that - does using SRL16's >have a real speed impact ? Look at the data sheet. Last time I checked, the clock-out was slow, might even be called very slow. If you want to go fast, it's basically a bug if the software takes a chain of FFs and turns them into a SRL without putting the last one in a FF. Is there a flag or such to get that? Humm. I can't find the SRL timing info in the Spartan3 data sheet. Virtex2 data sheet says: CLB FF Clk=> Q 0.57 ns CLB Shift Register - 2.9 ns. CLB as RAM timings are also slow. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 81866
Hi, Does anybody know where can I find datasheet of UARTlite IP core with detailed information of the signals and its working inside. Thank you.Article: 81867
"Antti Lukats" <antti@openchip.org> wrote in message news:d2gl1k$jec$01$1@news.t-online.com... > "Neo" <zingafriend@yahoo.com> schrieb im Newsbeitrag > news:1112266425.535008.282930@o13g2000cwo.googlegroups.com... >> Actually, I am new to boards and want to buy one which also has >> embedded processor to program and experiment with, at home. I found the >> one said above attractive but little expensive. any suggestions on >> which one to go for(xilinx ?) are welcome. >> > > something with s3-1000 as minimal on board, xess xsa3-1000 is $199 > www.xess.com > > antti > > also www.digilentinc.com can get a version of the S3 starter kit with a s3-1000 low cost $149 + whatever modules you decide on. More of a beginners board , good for getting started with AlexArticle: 81868
Hi Jeffrey, I was asked the same question not long ago because, with our Tornado board (http://www.alse-fr.com/tornado/torn_educ_us.pdf) we do USB programming with the ftdi chip :-) AFAIK, Altera would not be willing to give away the USB Blaster technology, but indeed you should ask them with your own arguments and see their answer. Designing the CPLD to just send an RBF bitstream at a given bitrate is very simple, provided you accept to write your own programmer utility (very simple too in this limited case). But it couldn't be transparently compatible with Altera's programmer SW and all its functions without deeply reverse-engineering all their USB blaster technology (bit arrangement, commands protocols, reporting, JTag control, etc...) and this is certainly not legal. The easy way to get USB speed and retain software copatibility with Altera tools is purchasing the Altera USB blaster. Bert Cuzeau Jeffrey Smith wrote: > Hello: > > I have seen a couple of Altera development kits that allow you to > program the FPGA using a USB port (instead of JTAG). This is > accomplished using a usb interface chip such as one from ftdi chip and > a cpld from altera (such as max 7000, part# EPM7064). > > Can anyone tell me where I can obtain the programming files to program > the max 7000? > > > Thanks in advance/ > > JS >Article: 81869
Hi Peter, I suspect the P&R tool, knowing the MRam is not initializable, may probably feel free to connect the data and address pins in any order :-( Hacking the simulation netlist automatically (Tcl script?) might be possible, recognizing the bus order from the net names and rewiring them in an orderly fashion to your own initialized model, but this doesn't seem obvious. Pls keep us posted on your findings, this is an interesting case :-) Bert Peter Y wrote: > For whatever reason, I need to be able to initialize the M-RAMs in Altera > chips, and I need to do this in a timing simulation, for which I use > Modelsim. > > So I've hacked the stratix_atoms simulation libraries to initialize them, > and that works fine. I can start a simulation, look in those memories and > everything they have is correct, but now the simulation is incorrect. > Anyone know why this might be? Are the columns of the RAM permuted for > timing reasons, is it endianness, or anything else? > > I need to do this with a lot of designs, so setting break points and using > the Update Embedded Memories in Quartus' simulator is annoying. Any other > suggestions? > >Article: 81870
Mentre io pensavo ad una intro simpatica "Eric DELAGE" scriveva: > ModelSim needs an env variable called LM_LICENSE_FILE which points to > the license.dat file. When you install ModelSim as administrator I guess > that this env. variable is installed in the private space of the > administrator. Have you verified that LM_LICENSE_FILE is defined as > system variable and not user variable? Can you see it when you log in as > a normal user? Now I can't control (I'll see tomorrow) but the error says that a "text file" cannot be written. However I'll try setting this environment variable. -- Just do it. |\ | |HomePage : http://nem01.altervista.org | \|emesis |XPN (my nr): http://xpn.altervista.orgArticle: 81871
I did this and then the RAM is not synthesized away. AlexArticle: 81872
Hello, I would like to know whether turning on the caches in the PPC influences the functionality of XMD. 1) For instance, when XMD downloads an ELF binary to the memory, it issues writes to processor through the debug ports. Is it safe to assume that these writes bypass the data cache? If this wasn't the case and you are using a writeback cache setting, then there is a chance that the instructions wouldn't make it to main memory. Thus, when executing the program, the instructions won't be read by the processor because it searches the instruction cache, then main memory on a miss. Does this make sense? 2) When using the debug mrd (memory read) or mwr (memory write), is it safe to assume that the data cache is bypassed since it is a debug memory read/write, even if the address actually resides in the cache? If the debug read/write does search the cache and causes a miss, will the configured cache behavior ensue (like fetching the rest of the cache line on a miss)? If this is the case, then debug reads could change the state of the cache/memory, which may not be desired by the programmer. In general, I would like to understand the mechanism that XMD uses to issue writes/reads to the processor for both instruction download and debug memory read/writes. The "PowerPC Processor Reference Guide" goes into nice detail about the debug capabilities of the PPC 405 with the various configuration registers and signals. However, there is no documentation (that I have found) that discusses how XMD employs those debug features. Therefore, I don't know if XMD is configuring the caches to go into non-cacheable mode for the debug memory accesses or it uses the existing configuration as defined by the program. I'm working on a ML 310 board with a V2P30 -6 chip. NNArticle: 81873
Hi, Does anyone have already heard about the CPLD that are part of chip mod for console?? And if there is any website talking about about making a chip mod? Thanks AlexisArticle: 81874
Eric Smith wrote: > Ziggy <Ziggy@TheCentre.com> writes: > >>Does such an animal exist? I have looked around but >>as of yet Ive not seen one. Saw reference to a couple >>of non-open ones. >> >>A x86 core would be nice too, but i doubt ill find >>one of them due to IP rights... > > > There's probably a lot less problem with IP rights on the x86 than on > the PowerPC. The x86 has been around long enough for the patents to > expire. (Maybe not on things like MMX and SSE, but you didn't indicate > that you needed those.) I hadnt thought about the patents expiring on the older X86 stuff, which would suit the bill fine. A reproduction of a 486 or base Pentium would be plenty for what i want to do. I also thought that PPC was more like ARM and SPARC, and the specs were available openly, just that it would cost to be 'certified' ( which in my case doesnt matter ). But ive been wrong before ;)
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