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The Xilinx Microblaze coprocessor interface is called Fast Simplex Link (FSL). The Xilinx Virtex4 PPC405 coprocessor interface is called the Auxiliary Processor Unit (APU). While this doesn't answer your question, the terms should help direct your googling.... Paul Praveen Krishnamurthy wrote: > > Hi Folks, > Can anyone point to or give me examples of applications that have been > known to use the coprocessor interface on SPARC or MIPS? > > In particular I am looking of apps that have greatly benefitted by the > coprocessor unit, or could potentially benefit if only there were an > appropriate coprocessor. > > Thanks in advance, > PraveenArticle: 82376
Kohn, Thanks for replying, could you elaborate a little more Thanks MORPHEUSArticle: 82377
You should go to www.altera.com to get the documentation on how to download the programming files into Cyclone part. There are a few tools, either use Quartus II programming, Jam player or embedded tools. You can find it all there including documentations. "yp" <ypuilee@yahoo.com> wrote in message news:<d3dcie$3tt$1@zcars129.ca.nortel.com>... > hi, > I have brought a cyclone development board (EZ1CUSB-12) from easyfpga > (www.easyfpga.com) . The CDROM version is 0.9 There is no > documentation/software how to download software to the cyclone chip. > According to the web site/menu, it can download from USB ( passive mode) or > AS ( active mode, which I think it can download from byteblasterMV cable). > Anybody can provide the software code !! > Thanks in advance. > Regards, > YPArticle: 82378
On 11 Apr 2005 19:44:28 -0700, "morpheus" <saurster@gmail.com> wrote:
>Kohn,
>Thanks for replying, could you elaborate a little more
>Thanks
>MORPHEUS
Exponential smoothing just simulates an R-C lowpass filter.
Define a filter box, with samples S coming in and output F going out.
Now, every sample clock, do
F = F + (S-F) / N
where N is the smoothing factor. If N is a power of two, the divide is
just a right-shift. So you can do this with just a register, two
adders, and a misaligned bus to do the shift.
F will settle to the mean value of S. Keep N pretty big to reduce the
small output ripple, or cascade two filter boxes. Making the filter
word size bigger than the ADC "S" word width helps a bit; in other
words, keep some or at least a few bits of the right-shifted stuff.
So just subtract F from each incoming sample. (S-F) is in there
somewhere already, so that's free.
In integer math, you'll have all the usual rounding and rollover and
sign extension issues to worry about. Still, it's not hard and works
well.
Done carefully, this will actually AC-couple the signal to an accuracy
of a fraction of an LSB.
John
Article: 82379Praveen wrote: > >if falling_edge(clk) then > > adtemp <= adin; > > end if; > > > > if rising_edge(clk) then > > addata <= adtemp; > > end if; > > This is (as I know) definitely not a good idea. You cannot using both > the edges of a clock in evaluating. Howdy Praveen, Why not? > Somebody please correct me if I am wrong. No offense intended, but why not try it rather than asking people to correct you? Synplify has no problem with his code. The style may not fit everyones taste, but works fine as written. Depending on the clock and data delay, it may not do what the OP wanted it to do (namely catch his data that appears to only be valid on a rising edge), but that's a different problem. Have fun, MarcArticle: 82380
Rudolf Usselmann wrote: > It's been now several weeks since the release of 7.1. However > I still have not seen a "fix" that would allow us to install > ISE 7.1 on 64 bit platforms: > > [rudi@cpu10 ISE71i_DesignEnv_lin64]$ ./setup > /home/tmp/7.1/ISE71i_DesignEnv_lin64/platform/lin64/bin/lin64 > /home/tmp/7.1/ISE71i_DesignEnv_lin64/platform/lin64/xilsetup: Symbol > `_XtperDisplayList' causes overflow in R_X86_64_PC32 relocation > /home/tmp/7.1/ISE71i_DesignEnv_lin64/platform/lin64/xilsetup: Symbol > `_XtGetPerDisplayInput' causes overflow in R_X86_64_PC32 relocation > Wind/U Error (294): Unable to install Wind/U ini file > (/home/tmp/7.1/ISE71i_DesignEnv_lin64/platform/lin64/data/WindU). > See the Wind/U manual for more details on the ".WindU" file and the "WINDU" > environment variable. > /home/tmp/7.1/ISE71i_DesignEnv_lin64/platform/lin64/setup: line 163: 19510 > Segmentation fault (core dumped) $setuploc/xilsetup $switch $batchfile > > > ************ setup done! *************** > > Will xilinx ever release a setup program that works, or do we > have to wait for 7.2 ? Howdy Rudi, I don't know if your posting prompted it, but two days after you posted, an answer record is now avaialble on this issue: http://support.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=21000 Good luck, MarcArticle: 82381
I have a custom board using Xilinx VirtexII. i'm using a master-serial mode. After power on reset(Power status is good) cclk must output clock. But clock just logic high. I can't find why clock is not out! Thanks to read my poor English message.Article: 82382
"eou4" <false0@gmail.com> schrieb im Newsbeitrag news:1113280439.883212.273370@l41g2000cwc.googlegroups.com... > I have a custom board using Xilinx VirtexII. > i'm using a master-serial mode. > After power on reset(Power status is good) cclk must output clock. > But clock just logic high. > I can't find why clock is not out! > Thanks to read my poor English message. > check M0 M1 M2, INIT_B, PROG_B and powersupplies if all of the above are correct then the CCLK should start antti http://gforge.openchip.org/Article: 82383
Hello all, I am working on a Virtex4 design and need to use RocketIO. Is there a sample design based on Virtex4 RocketIO that I can leverage on. I could not find any info in the Xilinx website other than the Virtex4 RocketIO user guide. Thanks, AjithArticle: 82384
According to their web site / document, there should be a way to download the configuration to Cyclone throught the USB port. I have brought their APEX 1k kit before and it comes with software and examples. So I expect that it will come with Cyclone development kit too. "Kar" <khkuan@yahoo.com> wrote in message news:db6ff787.0504111858.d7f7777@posting.google.com... > You should go to www.altera.com to get the documentation on how to > download the programming files into Cyclone part. There are a few > tools, either use Quartus II programming, Jam player or embedded > tools. You can find it all there including documentations. > > "yp" <ypuilee@yahoo.com> wrote in message news:<d3dcie$3tt$1@zcars129.ca.nortel.com>... > > hi, > > I have brought a cyclone development board (EZ1CUSB-12) from easyfpga > > (www.easyfpga.com) . The CDROM version is 0.9 There is no > > documentation/software how to download software to the cyclone chip. > > According to the web site/menu, it can download from USB ( passive mode) or > > AS ( active mode, which I think it can download from byteblasterMV cable). > > Anybody can provide the software code !! > > Thanks in advance. > > Regards, > > YPArticle: 82385
Thanks for the answers. So it shouldn't give any problems. I assume that having only the LMB bus, will still allow me to divide the code into a bootloader and application part. And to download the application into a reserved address range in the BRAM?! Frank "Paul Hartke" <phartke@Stanford.EDU> wrote in message news:42569481.C1817F26@Stanford.EDU... > No problem having both LMB and OPB BRAM visible to the same processor as > long as the addresses are not overlapping as indicated in the original > post. > > I agree that LMB is likely preferred if the Microblaze is the only > entity to access the memory space. OPB BRAM might be needed if other > peripherals require access to the memory such as a DMA engine. > > Paul > > Aurelian Lazarut wrote: >> >> Frank, >> why not having the whole bram (sum of your LMB and OPB) attached to LMB >> only? how is helping you if you have two mems on different buses? (OBP >> can get slow if you have to many peripherals...) >> Aurash >> >> Frank van Eijkelenburg wrote: >> >> >Hi, >> > >> >We have a design with a microblaze which runs from bram at startup >> >(connected through the LMB bus). After startup it is possible to >> >download an >> >application to sdram (connected through the OPB bus) and run from sdram. >> >Since we are going to change the fpga type and get a lot more brams >> >available; we are thinking to remove the sdram (to reduce costs) and >> >replace >> >it by bram. >> > >> >My question is: is it possible to have a microblaze with bram connected >> >to >> >the LMB bus and a seperate bram connected to the OPB bus and have >> >different >> >programs in the brams (a bootloader in de bram which is connected to the >> >LMB >> >bus, and an application downloaded at runtime in the bram which is >> >connected >> >to the OPB bus) and run both of them (not at the same time of course)? >> > >> >As far as I can see, it doesn't matter what kind of memory is used for >> >the >> >application (bram or sdram) as long as the code is built to run from the >> >correct addresses. Can anyone confirm this and/or has experience with >> >this? >> > >> >Thanks in advance, >> >Frank >> > >> > >> > >> > >> >> -- >> __ >> / /\/\ Aurelian Lazarut >> \ \ / System Verification Engineer >> / / \ Xilinx Ireland >> \_\/\/ >> >> phone: 353 01 4032639 >> fax: 353 01 4640324 >> >>Article: 82386
M0 M1 M2 is tied with pull-up resistors. INIT_B is connected with XC18(xilinx PROM)'s OE/reset pin. (pull-up with 4.7k) PROG_B is connected with XC18's /CF pin. (pull-up with 4.7k) Power(VCCINT, VCCAUX, VCCO,GND) levels are good, and mode setting correct. But cclk isn't start..Article: 82387
M0 M1 M2 correct("000"). Power levels are correct.
INIT_B, PROG_B are logic high. These pins are connected with 4.7k
pull-up and xilinx PROM(OE, /CF)
Antti Lukats wrote:
> "eou4" <false0@gmail.com> schrieb im Newsbeitrag
> news:1113280439.883212.273370@l41g2000cwc.googlegroups.com...
> > I have a custom board using Xilinx VirtexII.
> > i'm using a master-serial mode.
> > After power on reset(Power status is good) cclk must output clock.
> > But clock just logic high.
> > I can't find why clock is not out!
> > Thanks to read my poor English message.
> >
>
> check M0 M1 M2, INIT_B, PROG_B and powersupplies
> if all of the above are correct then the CCLK should start
>
> antti
> http://gforge.openchip.org/
Article: 82388Hello, Brijesh <brijesh_xyz@cfrsi_xyz.com> wrote in message news:<d3e426$rbl$1@solaris.cc.vt.edu>... > The double clocking of the CRC generator mentioned was when strobe was > directly used to clock the CRC generator. In my design I am using > internal clocl for CRC generator. Although I am still using the strobe > to clock in the data at the IOB's. So right now I suspect thats where > the problem is. How do you know when new values are available to take them into your core clock domain? Can double clocking occure at this point? > So currently Iam trying to identify the cause, > Is it really the double clocking that is causing the trouble? You could put the captured data on a debug output, capture it with an logic analyzer and compare it with your reference. High effort, though. > > I don't know much about these issues (I design circuits for FPGA/ASICs > > and do no "real" hardware), but don't you need to take LVCMOS33 for > > outputs? > > The Voh and Vol for LVCMOS33 and LVTTL33 on V2 device are identical and > match that of the IDE spec. Really? I read in the ds031.pdf (v3.4) on page 4 in module 3, that Voh is 2.4 V for LVTTL and Vcco-0.4 for LVCMOS33. But anyway, the requirement is 2.4 V for UDMA3. I had the more restrictant Voh2=VDD3-0.51V in mind, which is required for UDMA5 and greater. > Also just read that the LVTTL and LVCMOS > inputs have approximately 100mV of hysteresis. Again for UDMA5 and greater, there are additional requirements for the input thresholds to keep the average of the two close to 1.5 V. I think this is to ensure that a rising STROBE and a falling DATA edge will switch at the same time. Hmm - I see that the requirement for the 320 mV hysteresis is for UDMA5 and greater only, too. Sebastian WeiserArticle: 82389
Hi as per today press release from Xilinx and Philips the PX1011A PCI Express PHY and supporting IP are now available from Philips/Xilinx, but unfortunatly it all seems to be only the big press release bla bla, that is not closer info available not from Xilinx and not from Philips, eg there is no Datasheet for PX1011A and even the PX1011A product brief contains typographical errors in the chips signal namings, so it seems that all is still very early. Has anyone seen the datasheet or the PX1011A silicon? I mean real silicon not on the presse photo? Antti http://gforge.openchip.orgArticle: 82390
Dear all, I would like to make use of the XAPP333 vhdl codes provided by Xilinx on my Spartan 2E. It's an I2C bus controller, and I would like to make it to run at slave mode all the time. What should I do? And also, I don't use it with a microcontroller, so I wonder the microcontroller interface is necessary!? ThanksArticle: 82391
Hello, I'm using Edk 6.3i with service pack 2 and have created a user core, which has a Tri-state Port with import/creat wizard. I import it to EDK but when I want to make the netlist, I get this error: "No default binding for component", "Ports <*_I,*_O,*_T> are not on the entity" I have checked the component declaration and instantiation, they match. The declaration match the port declarations of the submodule too. Thanks in advance, Regards, SKHArticle: 82392
"SKH" <khezerloo@itiv.uni-karlsruhe.de> schrieb im Newsbeitrag news:ee8d640.-1@webx.sUN8CHnE... > Hello, > > I'm using Edk 6.3i with service pack 2 and have created a user core, which has a Tri-state Port with import/creat wizard. > > I import it to EDK but when I want to make the netlist, I get this error: > > "No default binding for component", "Ports <*_I,*_O,*_T> are not on the entity" > > I have checked the component declaration and instantiation, they match. The declaration match the port declarations of the submodule too. > > Thanks in advance, > > Regards, > > SKH can you post the .MPD and the comp declaration part? anttiArticle: 82393
According to the data sheet... Power supply, USB drivers, reference, documentation and designs with source code come with the kit.. I would suggest you ask the supplier where yours are. Simon "yp" <ypuilee@yahoo.com> wrote in message news:d3fpbv$r6h$1@zcars129.ca.nortel.com... > According to their web site / document, there should be a way to download > the configuration to Cyclone throught the USB port. I have brought their > APEX 1k kit before and it comes with software and examples. So I expect > that it will come with Cyclone development kit too. > > "Kar" <khkuan@yahoo.com> wrote in message > news:db6ff787.0504111858.d7f7777@posting.google.com... > > You should go to www.altera.com to get the documentation on how to > > download the programming files into Cyclone part. There are a few > > tools, either use Quartus II programming, Jam player or embedded > > tools. You can find it all there including documentations. > > > > "yp" <ypuilee@yahoo.com> wrote in message > news:<d3dcie$3tt$1@zcars129.ca.nortel.com>... > > > hi, > > > I have brought a cyclone development board (EZ1CUSB-12) from easyfpga > > > (www.easyfpga.com) . The CDROM version is 0.9 There is no > > > documentation/software how to download software to the cyclone chip. > > > According to the web site/menu, it can download from USB ( passive mode) > or > > > AS ( active mode, which I think it can download from byteblasterMV > cable). > > > Anybody can provide the software code !! > > > Thanks in advance. > > > Regards, > > > YP > >Article: 82394
>M0 M1 M2 correct("000").
Your previous post said:
> M0 M1 M2 is tied with pull-up resistors.
I usually think of "up" as being a 1. If you really
have pullups, that's probably your problem.
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Article: 82395Ben Twijnstra wrote: > Also, the current version always compiles into library "work". As long as > there's no namespace conflicts this is quite workable, but not quite what > the LRM specifies. I have heard that version 5.0 will support named > libraries. You could change the library in the file properties tab with the GUI or with the following TCL command: set_global_assignment VHDL_FILE my_pkg.vhd -líbrary my_lib This works in QuartusII 4.2. The drawback is that a single file could NOT be in two libraries. Regards FrankArticle: 82396
"DerekSimmons@FrontierNet.net" <DerekSimmons@FrontierNet.net> wrote in message news:<1113268524.450443.117240@g14g2000cwa.googlegroups.com>... > The examples you are looking for would have to be specific to the board > you are using and you haven't told us that. > > Derek Ya, sorry about that. The board is a Xilinks Spartan - 3 XC3S200. Thanks!!Article: 82397
0201 fits nicely on the 1mm via grid underneath the FPGA allowing the optimal termination point. 0201 are not generally available in the common used UK catalogues as yet. Digi-Key do have stock though if you can suffer the US export questions. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "Nial Stewart" <nial@nialstewartdevelopments.co.uk> wrote in message news:425acdf6$0$2595$da0feed9@news.zen.co.uk... >> You can fit yourself if you are very good with a soldering iron but >> beware as the resistor sites are 0201 size. > > 0201! > > I thought 0402 was bad, 0201 must be like dust. > > I presume components this size remove all the headache of decoupling/ > terminating BGA designs, but are they easy to get hold of, and where > do you source them in the UK (they're not in the RS catalogue :-( ). > > > Nial. >Article: 82398
Hi, I have used the Xilinx XPS to debug a design on a custom board (on-chip hw debug). Now, I want to disable the debug so the code run once the FPGA is programmed. Beleive or not, but I don't find a easy way to to do this. Can anyone help me? Thanks, John -- Sendt med M2 - Operas revolusjonerende e-postprogram: http://www.opera.com/m2/Article: 82399
"John" <nospam.nospam@nospam.com> schrieb im Newsbeitrag news:opso36rgfbg6mgav@visitech-jd.visitech.local... > Hi, > > I have used the Xilinx XPS to debug a design on a custom board (on-chip hw > debug). Now, I want to disable the debug so the code run once the FPGA is > programmed. Beleive or not, but I don't find a easy way to to do this. Can > anyone help me? > > Thanks, > > John there is no disable and its also not needed, you can leave the MDM component in the system it doesnt do anything if not accessed by XMD, so it doesnt matter. After cold start the Microblaze starts from the initialized BRAMs. If you are sure you dont need the MDM anymore just remove the MDM core instance and related signals and resynthesize in XPS antti http://gforge.openchip.org
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