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Hi, I follow the steps from http://www.fpga-faq.org/FAQ_Pages/0044_Xilinx_Parallel_on_Linux.htm Environment: Suse9.2 (Kernel 2.6.8-24) ISE6.3.03i EDK6.3.02i Impact6.3.03i When I try load xpc4drvr module, the kernel message shows following message xpc4drv: unsupported module, tainting kernel. xpc4drvr: init_module I tried reload the module again, same message appear again. I am sure that xpc4drvr module is loaded on the module list. However that xmd show that it can't find the module and operating in compatibility mode instead of high speed mode. Is anyone knows how to fix this problem? Partial Message log: AutoDetecting cable. Please wait. Connecting to cable (Parallel Port - parport0). WinDriver v6.23 Jungo (c) 1997 - 2004 Build Date: Nov 17 2004 X86 11:07:13. parport0: baseAddress=0x378, ecpAddress=0x778 LPT base address = 0378h. ECP base address = 0778h. ECP hardware is detected. Cable connection established. Connecting to cable (Parallel Port - parport0) in ECP mode. Module xpc4drvr is not loaded. Cable connection failed. Connecting to cable (Parallel Port - parport0). WinDriver v6.23 Jungo (c) 1997 - 2004 Build Date: Nov 17 2004 X86 11:07:13. LPT base address = 0378h. ECP base address = 0778h. Cable connection established. ECP port test failed. Using download cable in compatibility mode. Thanks in advance. JasonArticle: 82326
As I said, the memory access works through jtag debugger Trace32. What is the difference in execution flow of memory access through debugger command and software instruction ? This is the key to solve this problem.Article: 82327
Hi, with the latest quartus II software I created two VHDL packages. After testing the packages I wanted to combine them in a custom VHDL library with no success. My goal is to have a directory that contains the library (preferrably precompiled) so that I can pass it around and it could be used by others as simple as the standard VHDL libraries (e.g. ieee) like LIBRARY my_lib; USE my_lib.package1.all; USE my_lib.package2.all; without adding each single VHDL file the packages are based on. Any pointer to information or hints how I could get things up and running would be a great help. thanks in advance, /chArticle: 82328
Hai all,
I have a virtex pro II fpga board. I would be thankful if
anyone can tell me how can we generate bit streams for verilog HDL
programs using XPS(xilinx platform studio),by which I can make use of
those bit streams for prgramming VIRTEX II PRO fpga board.
plz let me know at your earliest attention.
regards,
kishore
email id : nkishorebabu123@yahoo.com
Article: 82329Uwe, Thanks, BTW it works in 6.3.03i Dave Colson "Uwe Bonnes" <bon@elektron.ikp.physik.tu-darmstadt.de> wrote in message news:d3c3d2$dut$1@lnx107.hrz.tu-darmstadt.de... > Dave Colson <dscolson@rcn.com> wrote: > > Hi, > > > Does anyone know what this switch really does? > > They don't explain as to what is in that directory. > > > Does it mean that if you have an "`include" directive > > in your verilog code that XST will search that directory for > > the files? > > > Yes... > > ... however Xilinx screwed that option before 5.3 and after 5.3. > > -- > Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 82330
"nkishorebabu123" <nkishorebabu123@yahoo.com> schrieb im Newsbeitrag news:1113228014.342103.280320@g14g2000cwa.googlegroups.com... > Hai all, > > I have a virtex pro II fpga board. I would be thankful if > anyone can tell me how can we generate bit streams for verilog HDL > programs using XPS(xilinx platform studio),by which I can make use of > those bit streams for prgramming VIRTEX II PRO fpga board. > > plz let me know at your earliest attention. > > regards, > kishore > email id : nkishorebabu123@yahoo.com > its very simple! open a project and select meny 'download' this will generate the bitstream and download to the v2pro board antti PS Verilog is not programming language but hard ware DESCRIPTION language and it is not used to write programs. but to define hardware that can execute programsArticle: 82331
Hi, are there any free books on HDLs (verilog preferred) online? I found several "getting started" tutorials, but what I am looking for is - the workflow to get some kind of a "hello world" program running on the example of any development kit. - some examples with simple hardware interaction ( eg. RS232 communication, logic analyzer, ...) - maybe the implementation of a very simple processor - special features like PLL or DCM usage - a brief reference of the HDL - all contained in one pdf, if possible. If there is no such book online, which one do you recommend to purchase to get practical experience using verilog for a Spartan 3 based development kit? JensArticle: 82332
Hi Folks, Can anyone point to or give me examples of applications that have been known to use the coprocessor interface on SPARC or MIPS? In particular I am looking of apps that have greatly benefitted by the coprocessor unit, or could potentially benefit if only there were an appropriate coprocessor. Thanks in advance, PraveenArticle: 82333
Hello Sebastian, > According to the ATA/ATAPI spec, you need input buffers with at least > 320 mV of hysteresis. The appendix notes that double clocking of the > CRC calculator while capturing the correct data or calculating the > correct CRC while capturing wrong data had been observed, thus the > requirement. Maybe that's your problem? The double clocking of the CRC generator mentioned was when strobe was directly used to clock the CRC generator. In my design I am using internal clocl for CRC generator. Although I am still using the strobe to clock in the data at the IOB's. So right now I suspect thats where the problem is. So currently Iam trying to identify the cause, Is it really the double clocking that is causing the trouble? Is the double clocking occuring of ringing or because of cross talk? Trying to answer the above questions. Currently I am planning to slow the rise time further and see its effect. > BTW: The spec also notes that your inputs must be 5 V tolerant, which > AFAICS can't be achieved on a pure Virtex-II while keeping the correct > dimensions of the series resistors. The FPGA must even widthstand 6 V > ringing voltages. I don't know if a Virtex-II can do this. We are using voltage clamp device from TI to limit the input volate to 3.3v. http://focus.ti.com/docs/prod/folders/print/sn74tvc3306.html > I don't know much about these issues (I design circuits for FPGA/ASICs > and do no "real" hardware), but don't you need to take LVCMOS33 for > outputs? The Voh and Vol for LVCMOS33 and LVTTL33 on V2 device are identical and match that of the IDE spec. Also just read that the LVTTL and LVCMOS inputs have approximately 100mV of hysteresis. > The ATA/ATAPI specs dictate that the series termination plus input > impedance is between 50 and 85 Ohms. How have you taken the values for > your board without knowing those of the FPGA? The typical suggested values were used. Plus the spec recommends that we should terminate the cable rather than the device, ie. the termination resistors are placed as close to connector. Thanks for the input. Brijesh Sebastian Weiser wrote: > Brijesh <brijesh_xyz@cfrsi_xyz.com> wrote in message news:<d33k4c$sjr$1@solaris.cc.vt.edu>... > >>We have a board with multiple IDE interfaces implemented in Virtex2 >>device. We are using UDMA 3 protocol. >>One of the boards is giving a CRC error at random times, erros occurs >>once in 12 hrs of continous read operations. Error occurs on the same >>IDE channel. > > > According to the ATA/ATAPI spec, you need input buffers with at least > 320 mV of hysteresis. The appendix notes that double clocking of the > CRC calculator while capturing the correct data or calculating the > correct CRC while capturing wrong data had been observed, thus the > requirement. Maybe that's your problem? > BTW: The spec also notes that your inputs must be 5 V tolerant, which > AFAICS can't be achieved on a pure Virtex-II while keeping the correct > dimensions of the series resistors. The FPGA must even widthstand 6 V > ringing voltages. I don't know if a Virtex-II can do this. > > >>All inputs are LVTTL 3.3V, no IBUF delays used on strobe or data. On >>Strobe pins I have enabled DCI with 50 Ohm resistor. But now my >>understanding is that for LVTTL 3.3V input pins, DCI does no good. > > > I don't know much about these issues (I design circuits for FPGA/ASICs > and do no "real" hardware), but don't you need to take LVCMOS33 for > outputs? > > >>A separate question I was trying to look up the source impeadance/input >>impeadance of V2 outputs/inputs, couldn't find the number anywhere. Are >>they specified? > > > The ATA/ATAPI specs dictate that the series termination plus input > impedance is between 50 and 85 Ohms. How have you taken the values for > your board without knowing those of the FPGA? > > > Sebastian WeiserArticle: 82334
Hello, I am designing a system using Virtex 4 FPGA. The FPGA is interfaced with a 12-bit A/D. The problem is that the A/D generates an inherent dc component in the digital values it ships to the FPGA. This is impacting my results at the lower end of my specs. The methods I have thought of are 1. Trim the A/D manually using a resistor 2. pass the lower 3-bits of the A/D word through a large moving average filter at the input(filter design is a pain!!) Is there any other method which can be used Thanks MORPHEUSArticle: 82335
Take a look at GenoByte, http://www.genobyte.com/cbm.html. News is old though, ca. 2000. -- Pete e wrote: > Has anyone investigated implementimg neural nets in FPGAs?Article: 82336
Peter Alfke wrote: Thanks for the link. It has some helpful tips and tricks. > Seems like I gave you a bad URL. > Try this one: > > http://www.te.rl.ac.uk/esdg/atlas-flt/talks/StockholmXilinx.pdf. > > Peter Alfke >Article: 82337
Hi,
I have an A/D-converter attached to my Spartan3 starter kit, running at
100Mhz Maximum speed.
But the A/D converter only has valid data 7 ns after the rising clock
edge and until 2ns after the next rising clock edge?
Where should I sample running a low-frequent sampling of fx. 10 MHz?
Is this the way, or isn't a good way?
process(clk)
begin
if falling_edge(clk) then
adtemp <= adin;
end if;
if rising_edge(clk) then
addata <= adtemp;
end if;
end process
and then use the addata for something else!
Thanks for helping!
Article: 82338Only thing I can add is if you are using internal tri-state buffers in Xilinx FPGA, use negative true control signals. A tri-stated signal is read as a logic High. Ankit Raizada wrote: > I have a microprocessor core (Plasma from Opencores), I want to > implement a shared bus (Data as well as Address) among the this core > and a number of other cores as well. If anyone has some experience > about implememnting a shared bus please let me know. I have 2 ideas (1) > to connect the cores in a daisy chain kind of fashion (2) to connect > the cores using tri state logic. which will give me more performance > benefit? Also other experiences, ideas and knowledge about nuances of > this design are welcome. >Article: 82339
"morpheus" <saurster@gmail.com> schrieb im Newsbeitrag news:1113232619.700616.34200@z14g2000cwz.googlegroups.com... > Hello, > I am designing a system using Virtex 4 FPGA. The FPGA is interfaced > with a 12-bit A/D. The problem is that the A/D generates an inherent dc > component in the digital values it ships to the FPGA. This is impacting > my results at the lower end of my specs. > The methods I have thought of are > 1. Trim the A/D manually using a resistor > 2. pass the lower 3-bits of the A/D word through a large moving average > filter at the input(filter design is a pain!!) > Is there any other method which can be used > Thanks > MORPHEUS > Check out Ken Chapmans TechExclusives at www.xilinx.com there its explained how todo this antti http://gforge.openchip.orgArticle: 82340
On Wed, 6 Apr 2005 02:23:57 -0700, "Anthony Ellis" <> wrote: >XAPP176 defines how to read back the configuration file but doesn't >state whether this can be done while the device is operating normally? > >Anthony Readback can be done while the FPGA is operational. But ... readback includes the state of the flipflops and the LUTs. Since FFs will be changing, and you may be using some of the LUTs as RAM, the readback will be dependent on the state of your design, which wil be changing while you are doing the readback. You may want to read up on the .LL file created by bitgen, which will help you separate the static bits from the dynamic bits of the readback data. Philip Philip Freidin FliptronicsArticle: 82341
morpheus wrote:
>Hello,
>I am designing a system using Virtex 4 FPGA. The FPGA is interfaced
>with a 12-bit A/D. The problem is that the A/D generates an inherent dc
>component in the digital values it ships to the FPGA. This is impacting
>my results at the lower end of my specs.
>The methods I have thought of are
>1. Trim the A/D manually using a resistor
>2. pass the lower 3-bits of the A/D word through a large moving average
>filter at the input(filter design is a pain!!)
>Is there any other method which can be used
>Thanks
>MORPHEUS
>
>
>
If you can afford run a calibrate cycle at start-up, you can subtract
the DC using a simple adder in the FPGA. Finding the value to subtract
(and adjusting it as the DC offset drifts) is the hard part. You can
use a CIC filter with a fairly high decimation ratio to extract the DC
value with relatively little complexity.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 82342Hi, I want to write an interface in vhdl for a HD44780 LCD Controller. What is the best methodology to do that? Moore-Automat? How should I realize the neccessary wait operations? Especially the initialization of the LCD requires about 7 steps to be performed in order with some waits in between.... regards, BenjaminArticle: 82343
The maximum operating frequency of the DCM is not a function of the input clock, but of the internal delay lines. The Virtex-II and above families include a divide by two function on the CLKIN pin of the DCM dropping the frequency from 622 to 311 MHz for the delay lines in the DCM which is within the operating range of the DCM. Ed Benjamin Menküc wrote: > Hi, > > in the introduction i find: > "At SDR clock frequencies below the maximum operating frequency (420 > MHz) of the Virtex-II > Digital Clock Manager (DCM), implementing a single data rate design can > be easily > accomplished using standard design techniques. This application note > describes a method of > implementing an SDR interface at clock frequencies higher than the > maximum operating > frequency of the DCM, without exceeding the AC timing specifications of > the Virtex-II devices." > > but later on, on page 3, the input ref_clk is connected to a DCM. Why is > that possible? I thought the frequency is higher than the max DCM input > frequency? > > regards, > BenjaminArticle: 82344
I made an interface with PicoBlaze (made the interface in assembler). It was for a project at school. "Benjamin Menküc" <benjamin@menkuec.de> skrev i meddelandet news:d3e6ri$okp$05$1@news.t-online.com... > Hi, > > I want to write an interface in vhdl for a HD44780 LCD Controller. What > is the best methodology to do that? Moore-Automat? How should I realize > the neccessary wait operations? Especially the initialization of the LCD > requires about 7 steps to be performed in order with some waits in > between.... > > regards, > BenjaminArticle: 82345
Hi Elektro, In my design I dont have no processor, therefore I am not sure if it is worth is setting up a processor just for the lcd... A good thing would be a little place in the ram, where I write my two lcd lines and a seperate process that writes the lines to the lcd each time something in the lcd-ram-area changes. Maybe a moore state machine would be the right solution.... regards, BenjaminArticle: 82346
Look here: http://www10.dacafe.com/book/parse_book.php?article=BITSLICE/index.html This gave me some ideas to implement an interface to a circuit that required some steps to initialize and then a loop to get some values from. I made a state machine that executed instructions from a ROM. Maybe you could do it like that? "Benjamin Menküc" <benjamin@menkuec.de> skrev i meddelandet news:d3eb55$72q$04$1@news.t-online.com... > Hi Elektro, > > In my design I dont have no processor, therefore I am not sure if it is > worth is setting up a processor just for the lcd... > > A good thing would be a little place in the ram, where I write my two > lcd lines and a seperate process that writes the lines to the lcd each > time something in the lcd-ram-area changes. > > Maybe a moore state machine would be the right solution.... > > regards, > BenjaminArticle: 82347
In the MAX7000S datasheet, it says the I/O pins are tri-stated and (weakly) pulled-up, to avoid board conflicts, during programming. What should the state of the I/O pins be _before_ programming? I have a sample EPM7128S device here which appears to be pulling them low - but it also fails the blank test, so I think it must have been programmed. How should a brand-new part behave?Article: 82348
On 11 Apr 2005 08:16:59 -0700, "morpheus" <saurster@gmail.com> wrote: >Hello, >I am designing a system using Virtex 4 FPGA. The FPGA is interfaced >with a 12-bit A/D. The problem is that the A/D generates an inherent dc >component in the digital values it ships to the FPGA. This is impacting >my results at the lower end of my specs. >The methods I have thought of are >1. Trim the A/D manually using a resistor >2. pass the lower 3-bits of the A/D word through a large moving average >filter at the input(filter design is a pain!!) >Is there any other method which can be used >Thanks >MORPHEUS Exponentially smooth the incoming samples to get the average value, and subtract that from the data stream. KohnArticle: 82349
Hi i have buy, virtex 4 evalutation board. In the box there isn't any cable for the bitstream download. Can i download with impact the fpga bitstream with serial null modem cable or usb cable? ThaNKS bss
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