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Bob Perlman wrote: > On Sat, 07 May 2005 16:05:13 GMT, Jeff Cunningham <jcc@sover.net> > wrote: > > >>>>>Bob Perlman wrote: >>>>>1) Do you use capacitors on digital lines? >>>>>2) Do you use analog one-shots in your designs? >>>>> >>>>>Ray Andraka wrote: >>>>>3) do you connect logic outputs to clock inputs (or do you use gated >>>>> clocks)? >>>>> >>>>>Symon Brewer wrote: >>>>>4) Have you had any bugs that 'fixed themselves' without you knowing >>>>>why? >>>>> (They always come back!) >>>>>5) Any unterminated digital lines going off board and/or longer than >>>>>c.15cm? >>>>> >>>>>Philip Freidin wrote: >>>>>6) Do you have any pet theories on how to fix metastables? >>>>> >>>>>7) Do you use the async set and reset pins on FFs for other than >>>>> system initialization? >>>>> >> >>Thomas Rudloff wrote: >> >>>8) Do you use pull up resistors on fast CMOS busses that require less >>>than 10ns/V rise / fall time? >> >>9) In what situations might it be acceptable knowingly violate worst >>case timing specs? > > > Good question, Jeff, but we're looking for questions with yes/no > answers. > > Bob Perlman > Cambrian Design Works Let me rephrase: 9) Do you ever knowingly violate worst case timing specs?Article: 83851
Similar comments to Brannon. If you have more than one device in the JTAG chain make sure you have the appropriate pullups on the paths between devices. The Flash devices seem to have enough internal . The V2Pro does not seem to have enough internal pullups on these lines. We have a setup with 4 V2pros in the chain and we missed the pullups (except on the last device to the cable.) We added the pullups and went from 7 min in cable II Compat mode to 20 sec in Cable IV mode. (ECP mode with Int 7 enabled with both) On Fri, 06 May 2005 12:33:55 GMT, Sean Durkin wrote: > > >Hi folks, > >this is starting to drive me nuts: > >I use a Xilinx Parallel Cable IV to program some big FPGAs (big as in >V2P70 and the like). Now Impact and Chipscope always open this cable in >"Compatibility Mode", meaning it is used as a Parallel Cable III and >takes FOREVER to download a bitstream. No matter what I do, no matter >what settings for the parallel port I use, it keeps getting detected as >a Parallel Cable III. This is a problem we've been having constantly for >years now... on some machines it works fine, on some it doesn't, and on >some others it sometimes works but sometimes doesn't. > >The only certain thing is that it never works on the machine I am >currently working on when I have a lot of testing to do and big bitfiles >to download. > >Now, I've googled my eyes out for this, read all the answer records, >tried everything mentioned there and everything I could think of: > >- I tried all possible BIOS-settings for the parallel port: ECP, EPP, >bidirectional, different DMA-channels, different IRQs; you name it, I've >tried it > >- I tried uninstalling the cable drivers from Xilinx, reinstalling new >ones. I tried uninstalling the entire ISE, making sure there's nothing >left in the Windows-Drivers-Dir, reinstalling ISE. I've tried every >ISE-version from 4.2 to 7.1 without success. I've tried doing a fresh >install on a freshly installed Windows, nothing. > >Now we bought one of the new platform cables for USB, works much better, >but those are expensive and we have probably half a dozen "Parallel >Cable IVs" in use. > >Any pointers, any hints? > >cu, >SeanArticle: 83852
I want to do float computing with xilinx FPGA, but I don't know how.In order to add libm.a into the project, I know that I can made it by edit the MSS file, but I don't know how. Who knows how? Please tell me. Thank you very much!Article: 83853
>Bob Perlman wrote: >1) Do you use capacitors on digital lines? >2) Do you use analog one-shots in your designs? > >Ray Andraka wrote: >3) Do you connect logic outputs to clock inputs (or do you use gated > clocks)? > >Symon Brewer wrote: >4) Have you had any bugs that 'fixed themselves' without you knowing > why? (They always come back!) >5) Any unterminated digital lines going off board and/or longer than > c.15cm? > >Philip Freidin wrote: >6) Do you have any pet theories on how to fix metastables? > >7) Do you use the async set and reset pins on FFs for other than > system initialization? > >Thomas Rudloff wrote: >8) Do you use pull up resistors on fast CMOS busses that require less > than 10ns/V rise / fall time? > >Jeff Cunningham wrote: >9) Do you ever knowingly violate worst case timing specs? > > >Philip Freidin wrote (again): >10) Do you only use time specs for the "important" parts of your design? Philip Freidin FliptronicsArticle: 83854
Hi Folks, I'm using ECS (yes, I know...). Now, ECS forces one to insert a buffer whenever one wants to rename a bus. I have done so. I was stunned to see that buffer appear in the routed design - as a LUT with D=A1! I'm sure I can get rid of it using the proper XST or PAR options, but I don't know which. Can anybody help? Thanks a lot GunterArticle: 83855
Mouarf wrote: > thanks, > > these board seems to be cheap but my goal is more designing digital > around automotive busses than coding drivers and learn PCI bus. > > I bookmarked this board. > Automotive busses aren't very complex so if you want to build a PCI card interfacing with many automotive busses, then this board might definitely be a player. Ethernet and some of the heavy higher protocol layers that are often involved today are practically begging for a CPU and an operating system (with these layers already available!), but for automotive busses, HDL solutions should be viable. BertArticle: 83856
Paul Leventis (at home) wrote:
> If you are willing to use resistors/translator on inputs, you can also
> consider Altera's Max II family (specifically the EPM1270 in this case).
Well, 2 IDE channels require ~64 buffered IO lines and it means 8
additional LVX245 chips, what makes the board considerably larger
and increases the cost by about 2$ (low cost is a priority in this design).
Resistors would be good, because they are small and cheap, but
I don't believe that they will perform their job well at this speed.
> You've stated a "133 Mhz" operation requirement, but the speed of
> operation is a combination of what your design is doing and the speed of
> the device.
Of course, but here the design can be easily pipelined, so the chip
doesn't have to be extremely fast just to compensate a wrong algorithm.
> The EPM1270 gives you 1270 4-input logic elements, integrated
> configuration memory, and very high operating speeds.
But it cannot work with 5V devices. :-(
Best regards
Piotr Wyderski
Article: 83857
hi all
we following the steps from
http://www.fpga-faq.org/FAQ_Pages/0044_Xilinx_Parallel_on_Linux.htm
and install the parallel cable driver under linux kernel 2.6.10 (suse
9.3 pro)
Impact was not able to find xpc4drvr module thus parallel cable IV has
been set to compatibility mode. following message is from "make
download" in command mode
AutoDetecting cable. Please wait.
Connecting to cable (Parallel Port - parport0).
WinDriver v7.00 Jungo (c) 1997 - 2005 Build Date: Apr 26 2005 X86
11:07:13.
parport0: baseAddress=0x378, ecpAddress=0x778
LPT base address = 0378h.
ECP base address = 0778h.
ECP hardware is detected.
Cable connection established.
Connecting to cable (Parallel Port - parport0) in ECP mode.
Module xpc4drvr is not loaded.
Cable connection failed.
Connecting to cable (Parallel Port - parport0).
WinDriver v7.00 Jungo (c) 1997 - 2005 Build Date: Apr 26 2005 X86
11:07:13.
LPT base address = 0378h.
ECP base address = 0778h.
Cable connection established.
ECP port test failed. Using download cable in compatibility mode.
from the message the cable is operating in compatibility mode because
"xpc4drvr" is not loaded. When i check the module list, the "xpc4drv"
is loaded (instead of "xpc4drvr").
The kernel message shows the following message when xpc4drvr is loaded.
xpc4drv: unsupported module, tainting kernel.
xpc4drvr: init_module
Anyone has a solution to this?
The only certain thing is that it is about 10X slower than high speed
mode. This become very annoying when trying downloading a big bitfile.
thank you
Jason
Article: 83858Piotr Wyderski wrote: > Thomas Rudloff wrote: ... >> use some "Quick Switches" in series. > > Hm, what are they? > > Best regards > Piotr Wyderski Piotr, check out the SN74TVC3010 from TI. It's a 10 channel voltage level converter. We use them to interface 5 Vdevices to 3.3V FPGAs. Works like a charm, and 133 MHz should be no sweat either ... DigiKey lists them for about $1.10 each (qtty 25) Best Regards, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and SynthesisArticle: 83859
Rudolf Usselmann wrote:
> check out the SN74TVC3010 from TI. It's a 10 channel voltage
> level converter. We use them to interface 5 Vdevices to 3.3V
> FPGAs. Works like a charm, and 133 MHz should be no sweat either ...
>
> DigiKey lists them for about $1.10 each (qtty 25)
Thanks for this information, but these chips are very expensive
(relatively to their capabilities) -- LVC245 will do this task as well,
but its cost is 0.33$ (one unit quantity) or 0.25$ (25 units).
Best regards
Piotr Wyderski
Article: 83860In one of our product where we required a 5.0V tolerant I/O, we actually used SN74CB3T16211DL ($2.09/1K)from TI. Those are 24bit bus switch with 5V tolerant level shifter. Just use them as "pass throught". It is PCI compatible (33mhz) but im not too sure for Ultra ATA 133. You get 24bit in a single package and u will need 3 of them in order to cover your 64bit bus. Still you save on board space plus least routing for your pcb. Right now, digikey sells them for $2.38/unit. Good luck JacquesArticle: 83861
Nitro wrote: > Similar comments to Brannon. If you have more than one device in the JTAG > chain make sure you have the appropriate pullups on the paths between > devices. The Flash devices seem to have enough internal . The V2Pro does > not seem to have enough internal pullups on these lines. We have a setup > with 4 V2pros in the chain and we missed the pullups (except on the last > device to the cable.) We added the pullups and went from 7 min in cable II > Compat mode to 20 sec in Cable IV mode. (ECP mode with Int 7 enabled with > both) I don't think this has anything to do with the actual JTAG-connection. When you start up iMPACT or ChipScope, it opens your cable, and before it even starts scanning your JTAG-Chain, the cable is openend in compatibility mode. You don't even have to hook up the cable to any board at all, the software just detects a cable III on one machine and a cable IV on another. Plus, why does everything work perfectly with the exact same Parallel Cable, with the exact same board, just by hooking it up to a different PC? And why does it work fine with the USB-cable? I guess this is just a driver problem.... cu, SeanArticle: 83862
Hello, An Israeli company is looking for a consultant to help our Software and Hardware team to develop embedded processing capabilities using Xilinx embedded Power-PC. The successful candidate (doesn't have to be from Israel) will help the team to define u-architecture, select HW/SW tradeoffs for algorithms implementation and will develop some of the blocks for the first projects. We are looking for someone with proven experience using Xilinx EDK , preferably developing video / image processing systems. Please submit your resumes to ppc_consultant@walla.com. Thanks in advance!Article: 83863
Hi Jason, At least Altera's download cables are supported by the standard ppdev interface. Even the USB-based cables will be supported under Linux in the near future. Best regards, BenArticle: 83864
Check with www.hitechglobal.comArticle: 83865
Hi Peter, > You got it ! Does it use a dedicated feedback line or local routing? Best regards, BenArticle: 83866
Hi, I have a microblaze system with uart,intc and a user ip on the opb bus.I have used the create new peripheral procedure to get the user ip into the system.I had the code written before hand.SO I just copy pasted the code into the template provided by the tool in user_logic.vhd But i have some components which are instantiated into my user_logic.vhd. I have copied them into the vhdl directory where the tool have generated the templates for user_logic.vhd and my_ip.vhd. Now when i generate the bitstream i get error NGDBuild error It says that the component instantiation in my user_logic.vhd cannot be resolved. Where am I going wrong?Is it because its not able to find the codes for the components which are declared in m y user_logic.vhd? Thanx in advanceArticle: 83867
Each of the new files for instantiated modules must be listed in the *.pao file in the data directory of the pcore: "A PAO (Peripheral Analyze Order) file contains a list of HDL files that are needed for synthesis, and defines the analyze order for compilation." http://www.xilinx.com/ise/embedded/psf_rm.pdf "kittyawake@gmail.com" wrote: > > Hi, > I have a microblaze system with uart,intc and a user ip on the opb > bus.I have used the create new peripheral procedure to get the user ip > into the system.I had the code written before hand.SO I just copy > pasted the code into the template provided by the tool in > user_logic.vhd But i have some components which are instantiated into > my user_logic.vhd. I have copied them into the vhdl directory where the > tool have generated the templates for user_logic.vhd and my_ip.vhd. Now > when i generate the bitstream i get error > NGDBuild error > It says that the component instantiation in my user_logic.vhd cannot be > resolved. > Where am I going wrong?Is it because its not able to find the codes for > the components which are declared in m y user_logic.vhd? > > Thanx in advanceArticle: 83868
Dedicated feedback, of course. It has to be blinding fast, so that the set-up time of CE is kept low. There really is no choice, since gating the clock with a potentially asynchronous input would be a disaster. Peter Alfke, Xilinx Applications (hoping to make this a single posting...)Article: 83869
Hi folks, Let's say I have a module with 2 inputs and 2 outputs module1(input1, input2, output1, output2) Then I instantiate it like this module1 my_module1 (.input1(input1), .input2(input2), .output1(output1), .output2()); output2 is intentionally not used. How do I flag XST to suppress the warning of not using output2? HendraArticle: 83870
Bert Cuzeau wrote: >As of "having no time etc...", I fear the worst... >(data used at several places in the design without any >resynchronization : good luck in this case !) I have some part (that is when I receive external data) which I can resynchronisize. But there is also some portion (that is when I send data to external device) where I am not able to resynchronisize because external device is expecting data on the next clock cycle when asserting the control signal "NXT". Do you mean that it is impossible to use external synchronous data in a state machine without resynchronization ? Why? Thank you for your help. Rgds Andr=E9Article: 83871
"Piotr Wyderski" <wyderskiREMOVE@ii.uni.wroc.pl> wrote: > I need an FPGA chip which fulfills the following constraints: > > -- it has at least 64 IO lines; > -- it is not very fast, 133MHz is the highest possible internal frequency; > -- it contains about 500--1000 LE; > -- very important: it can directly communicate with 5V TTL devices, > this means that its inputs are 5V-tolerant, or better: its V_io = 5V; > -- the software can be easily obtained and is cheap or even free, > so perhaps only Altera and Xilinx should be considered as possible > vendors; > -- it is relatively cheap; > -- built-in configuration memory would be a great feature (because of > piracy). Check the Actel A54SX-S Device. Every requirement above could be met by a 54SX-S, if you accept a wide range for relative cheap *veg*. 133 MHz need a good design job, but I've allready seen 140MHz (MIL-Conditions) in real design . bye ThomasArticle: 83872
Start here http://www.xilinx.com/ . There is a button for IP on the page follow that. I have not given the direct link as you get a lot of garbage in the header. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "Mouarf" <toto@toto.de> wrote in message news:427d1b4c$0$11586$636a15ce@news.free.fr... > many thanks for these answers and advices. > > Some more questions: > - How is the IP licence managed? I mean, in evaluation mode, is there a > time limite (or whatever) in ISE web edition, is it downloadable or do I > need to get in touch with Xilinx sales men? > > - When buying IP, are there royalties on each PCI board sold? What is the > difference in the IP with those different licence? Are there some > limitations? > > - Are IP availble in a complete set of VHDL code etc or is it a > precompiled file set? > > - Could you give me a link to Xilinx PCI IP core, there are many available > on their website, I don't know which you are talking about? > > My project is mainly an evaluation/learning project. I want to learn FPGA > designs with a real and complete project (software, driver, digital > design, hardware) that could be done in any company (I've studied VHDL/ > Verilog years ago but only with simulations). > > Since my budget is not so large, I would like to least estimate my project > costs (with commercial IP in evaluation mode first, then if the project is > a succes, I plan to buy them) before starting and asking for funds to some > company that would be interested in this project (some are ready to help > me and wait for my budget estimation). > > Best regards > > John Adair a écrit : >> If you are just looking to experiment then the Xilinx PCI Core can be run >> on evaluation mode. Buy costs vary on license 32bit / 33MHz of the order >> $2000-5000. If you are a student there are education licensing as well. I >> believe there is one on opencores but it;s size may be quite large. >> >> $40 does not go far and Virtex and Stratix families are almost certainly >> out of that range unless you happen to be an extremely large user or go >> for the smallest parts in the range. For automotive applications >> Spartan-3 is a good fit for your application although I'm a bit biased to >> Xilinx. It is getting very difficult to get parts that are not BGA, or >> fine pitch like the QFN, let alone larger parts in an easy to use >> package. We should have something for hobby / student market in the shape >> of a low cost module in 2/3 months to assist with this problem. >> >> For simple size comparision I would use number of raw LUTs and flip-flops >> followed by memory size /organisation. The latter is not always simple as >> block rams can sometimes be inefficient for given applications. Xilinx >> have an advantage in this area with the ability to do local rams and >> shift register elements SRL16s from LUTs. This resource is in addition to >> block rams. >> >> Low cost processors I would look at opencores. Processors like MicoBlaze >> can be evaluated free but the kit does cost $495 if you need to buy the >> license. >> >> If you need a very large memory then bear in mind that FPGA ram is >> relatively expensive. However standalone Dual Port Memories are getting >> expensive too. For the large FIFO consider using a single interface >> memory ram, or dram, and use your FPGA as a controller to time multiplex >> access the data reads and writes. Smaller FIFOs are good things to do in >> your FPGA. >> >> John Adair >> Enterpoint Ltd. - Home of MINI-CAN, PCI and CAN Development Board. >> http://www.enterpoint.co.uk >Article: 83873
Hi, I have troubles with my reset using Altera MAX7000AE. Can I re-route the GCLR signal (global signal) from an internal signal, or is the GCLR really dedicated to the PIN GCLRn ! Larry, www.amontec.comArticle: 83874
Hi all, I would like to add the library: libm.a into my project, but I don't know how. who knows? Please help me. Thank you very much.
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Compare FPGA features and resources
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