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Thomas Rudloff wrote:
> Have a look at http://www.idt.com/?id=34 the "Quick Switches" were
> invented by "Quality Semiconductor".
Thanks, they look nice. :-)
> Maybe a CPLD instead of an fpga may be a better choice in your case.
Hm, I don't think so, large (512+ cells) CPLDs are very expensive.
But an ACEX FPGA seems to be a reasonable candidate (250MHz,
5V-tolerant, available in the TQFP100 and TQFP144 packages and
they have more than enough cells). FLEX6K are good too.
Best regards
Piotr Wyderski
Article: 83826Hi Peter Alfke, > Nice try! > ECC at the 64-bit parallel level eats only 8 extra bits, and our > BlockRAMs had those traditional parity bits all the time. No extra > storage cost. Just some clever partitioning... There's addtitional bit lanes in Altera devices too. So what does this add then? Did you add optional hard ECC generation/detection blocks to these 9th/18th bits? Or does the user have to code this him/herself? If it's an optional hard macro we're looking at 2 configurable muxes and an ECC generator on the input side, and 2 configurable muxes and an ECC checker on the output side for evey set of 9 bits. Also, do the V4s run continuous config sanity checks like Altera's devices? Best regards, BenArticle: 83827
Hello Ma, I started digital design as an experienced programmer. I'm sure other people who have followed the same learning path will tell you that this can actually be a real disadvantage. Your programming habits and developments methods will generally not migrate well to digital design. Thinking VHDL or Verilog is a programming language is the first trap to avoid, this leads you to think that you can use the same development methods. For example, while it's easy to start small programming projects by just hacking out a few classes, and modifying the design as you go along (a bad habit of course) I personally found this approach totally impractical for digital design work. I don't mean to dampen your spirits, simply to save you a lot of frustating hours on the learning curve. Before you jump in head first I would suggest reading some good books that include information on HDL inference and synthesis if you haven't already, as this maybe particulary hard to get to grips with for programmers. I'd suggest VHDL Design Representation and Synthesis, by Armstrong and Gray, although I'd read this after one of Peter Asheden's books. As for tools, well both Xilinx and Altera have free tools so I'd start there. Just my 2cents. Andy.Article: 83828
If you are just looking to experiment then the Xilinx PCI Core can be run on evaluation mode. Buy costs vary on license 32bit / 33MHz of the order $2000-5000. If you are a student there are education licensing as well. I believe there is one on opencores but it;s size may be quite large. $40 does not go far and Virtex and Stratix families are almost certainly out of that range unless you happen to be an extremely large user or go for the smallest parts in the range. For automotive applications Spartan-3 is a good fit for your application although I'm a bit biased to Xilinx. It is getting very difficult to get parts that are not BGA, or fine pitch like the QFN, let alone larger parts in an easy to use package. We should have something for hobby / student market in the shape of a low cost module in 2/3 months to assist with this problem. For simple size comparision I would use number of raw LUTs and flip-flops followed by memory size /organisation. The latter is not always simple as block rams can sometimes be inefficient for given applications. Xilinx have an advantage in this area with the ability to do local rams and shift register elements SRL16s from LUTs. This resource is in addition to block rams. Low cost processors I would look at opencores. Processors like MicoBlaze can be evaluated free but the kit does cost $495 if you need to buy the license. If you need a very large memory then bear in mind that FPGA ram is relatively expensive. However standalone Dual Port Memories are getting expensive too. For the large FIFO consider using a single interface memory ram, or dram, and use your FPGA as a controller to time multiplex access the data reads and writes. Smaller FIFOs are good things to do in your FPGA. John Adair Enterpoint Ltd. - Home of MINI-CAN, PCI and CAN Development Board. http://www.enterpoint.co.uk "Mouarf" <toto@toto.de> wrote in message news:427b6277$0$284$636a15ce@news.free.fr... > hello all, > > Could someone give me an advice of the best FPGA(s) that meets following > requirements: > > Application: PCI board to be connected to an automotive bus (CAN, or LIN, > or FlexRay etc...), an IP will be integrated for each of thoses busses > (only 1 bus type per PCI board, several channels). > > The application must include: > - a 5V PCI target core (32 bit, 33Mhz), how much does this cost? > - the PCI core owns a Win98 (option: Linux) driver and an API to map the > dual port RAM (ie: the application gets a pointer to the dual port RAM and > use it as memory without any function to be called when accessing PCI > hardware), how much does this cost? > - a dual port RAM core (maybe with anti collision feature or boundary > areas), with a size of at least 512kbit or a large FIFO, how much does > this cost? What is the RAM size range that is possible to build in a FPGA? > - the automotive bus IP core (I will code it) > - a non BGA package because of higher production cost and hardware debug > difficulties and low pin count (<150) > - low price (very very small quantities), below $40 in single quantity > (for one or 2 FPGA that will do the job), and low power consumption (ok, > everyone ask for that!) > - Xilinx or Altera because the FPGA community (like this newsgroup) know > their product well (ie: good support) > - free 16 or 32 bit processor core (or already integrated core like ARM or > PowerPC or maybe LEON) with well documented free development tools > (gcc...) or used by many open source projects, the firmware code will be > stored in an external parallel Flash memory. > > I know that I should first code and then choose the best FPGA that fits > the application but I must make a preselection in order to have more ideas > about the board architecture, power consumption and price... > > Should I consider that everything fits in a 300kGate FPGA? > > Could someone tell me and approximate number of required Kgate for each > block mentionned above? > > For more flexibility in the future (eg: available IC for processor or > automotive bus), I've thought about using 2 FPGA on the board: > - one for PCI interface, very large dual port RAM and a small FIFO (both > with the same connexion to external local bus), this will be the same for > every new board > - one for the automotive bus controller, and the processor (and its RAM) > that will have an external connection to the RAM inside the first FPGA, > this board can be changed to use a fast microcontroller instead of > processor core and/or to use an already existing CAN/LIN controller. > > Which FPGA would you recommend for both? > > > Other question: > Does someone know if there is an equivalent product table as > http://www.xilinx.com/products/tables/fpga.htm but for Altera, Actel or > Lattice?Article: 83829
What is the correct definition of clock delay or clock skew? And what is the difference between those two things! Thanks for your always good answers. / PrebenArticle: 83830
>>> Bob Perlman wrote: >>> 1) Do you use capacitors on digital lines? >>> 2) Do you use analog one-shots in your designs? >>> >>> Ray Andraka wrote: >>> 3) do you connect logic outputs to clock inputs (or do you use gated >>> clocks)? >>> >>> Symon Brewer wrote: >>> 4) Have you had any bugs that 'fixed themselves' without you knowing >>> why? >>> (They always come back!) >>> 5) Any unterminated digital lines going off board and/or longer than >>> c.15cm? >>> >>> Philip Freidin wrote: >>> 6) Do you have any pet theories on how to fix metastables? >>> >>> 7) Do you use the async set and reset pins on FFs for other than >>> system initialization? >>> Thomas Rudloff wrote: >> > 8) Do you use pull up resistors on fast CMOS busses that require less > than 10ns/V rise / fall time? 9) In what situations might it be acceptable knowingly violate worst case timing specs?Article: 83831
Ben, See below, Austin Ben Twijnstra wrote: > Hi Peter Alfke, > > >>Nice try! >>ECC at the 64-bit parallel level eats only 8 extra bits, and our >>BlockRAMs had those traditional parity bits all the time. No extra >>storage cost. Just some clever partitioning... > > > There's addtitional bit lanes in Altera devices too. To do what? > > So what does this add then? Did you add optional hard ECC > generation/detection blocks to these 9th/18th bits? Or does the user have > to code this him/herself? We have hard ECC, 72/64 code, that can be instantiated to provide single bit error correction, and doulble bit error detection with no soft IP required. > > If it's an optional hard macro we're looking at 2 configurable muxes and an > ECC generator on the input side, and 2 configurable muxes and an ECC > checker on the output side for evey set of 9 bits. > > Also, do the V4s run continuous config sanity checks like Altera's devices? We allow the custoemr to decide what they want to do: they can do just a check, or a check and correct, or nothing at all. They pay the least possible because we only harden what we need to enable this feature, not the whole thing. What A offers is a "oh no!" bit: if it is set, you have no recourse but to reconfigure and start over. That is all A allows the customer to know, nothing more. The same IP also allows the customer to flip bits so that they can see what effect NSEUs would have without having to go to a neutron beam (which is very expensive,, and time consuming).Article: 83832
Preben Holm wrote: > What is the correct definition of clock delay or clock skew? > And what is the difference between those two things! > > > Thanks for your always good answers. > > / Preben http://www.edacafe.com/books/ASIC/Book/CH06/CH06.5.phpArticle: 83833
ma wrote: > Thanks. Where can I get a good and free simulator http://www.symphonyeda.com/proddownloads.htm -- Mike TreselerArticle: 83834
I do when it's buses I am shifting. It is a single bit then I do use assignment and concatination. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "Duane Clark" <dclark@junkmail.com> wrote in message news:DmMee.1737$X21.1613@newssvr21.news.prodigy.com... > John Adair wrote: >> Libraries Guide is always a good place to start for component >> instantiation. There are some component templates also available in ISE >> under the little light style button. >> >> If you want a simple shift then doing it in VHDL or Verilog is also easy. >> If write your code as the following style (VHDL shown), i.e. without a >> reset, most synthesisers will turn it into SRL16 based logic. >> >> process(clk) >> begin >> if clk'event and clk='1' then >> >> shift1 <= input; >> shift2 <= shift1; >> ... >> shift(n) <= shift(n-1); >> end if; >> end process; >> > > Yikes! I guess I don't know why you would write a shift register that way. > > signal shift : std_logic_vector(n downto 0); > > process(clk) > begin > if rising_edge(clk) then > shift <= shift(n-1 downto 0) & input; > end if; > end process;Article: 83835
On Sat, 07 May 2005 16:05:13 GMT, Jeff Cunningham <jcc@sover.net> wrote: >>>> Bob Perlman wrote: >>>> 1) Do you use capacitors on digital lines? >>>> 2) Do you use analog one-shots in your designs? >>>> >>>> Ray Andraka wrote: >>>> 3) do you connect logic outputs to clock inputs (or do you use gated >>>> clocks)? >>>> >>>> Symon Brewer wrote: >>>> 4) Have you had any bugs that 'fixed themselves' without you knowing >>>> why? >>>> (They always come back!) >>>> 5) Any unterminated digital lines going off board and/or longer than >>>> c.15cm? >>>> >>>> Philip Freidin wrote: >>>> 6) Do you have any pet theories on how to fix metastables? >>>> >>>> 7) Do you use the async set and reset pins on FFs for other than >>>> system initialization? >>>> >Thomas Rudloff wrote: >>> >> 8) Do you use pull up resistors on fast CMOS busses that require less >> than 10ns/V rise / fall time? > >9) In what situations might it be acceptable knowingly violate worst >case timing specs? Good question, Jeff, but we're looking for questions with yes/no answers. Bob Perlman Cambrian Design WorksArticle: 83836
Hi austin, >> There's addtitional bit lanes in Altera devices too. > To do what? Oh, for 9-bit video data, or parity checking, or ECC, whatever you like. >> So what does this add then? Did you add optional hard ECC >> generation/detection blocks to these 9th/18th bits? Or does the user have >> to code this him/herself? > We have hard ECC, 72/64 code, that can be instantiated to provide single > bit error correction, and doulble bit error detection with no soft IP > required. That's exactly what I wanted to know. So, to summarize: If activated, a 64-bit write to a BRAM will use 8 additional bits for error-checking and recovery. The read and write ports have optional dedicated hard logic that, when enabled, generate and check ECC data. By the way, does this ECC stuf work on narrower RAM widths? >> Also, do the V4s run continuous config sanity checks like Altera's >> devices? > We allow the custoemr to decide what they want to do: they can do just > a check, or a check and correct, or nothing at all. They pay the least > possible because we only harden what we need to enable this feature, not > the whole thing. What A offers is a "oh no!" bit: if it is set, you > have no recourse but to reconfigure and start over. That is all A > allows the customer to know, nothing more. In A, the config error pin will allow you to take any external action. Rebooting the device is the most common application, but more elaborate schemes are possible. Also, the internal logic is also able to respond to a config error. Then again, since the configuration cannot be trusted anymore, it would be best to bring the circuit offline as quickly as possible. The 'reloading-while-running' feature in X is cool, but if I were an FPGA and I knew I couldn't be trusted anymore, Asimov's first law would kick in and I'd disable myself ASAP (i.e. after sticking a Post-It to my forehead indicating that a service technician should look me over because I went crazy). > The same IP also allows the customer to flip bits so that they can see > what effect NSEUs would have without having to go to a neutron beam > (which is very expensive,, and time consuming). Very nice idea indeed. After getting the first documentation about A's sanity checking we actually had to go to a nuclear lab to test the feature (the lab was also quite interested in the feature). We didn't do any quantitative testing (how could we, as humble end users), we just stuck the PCB in a high-intensity neutron beam and waited. And waited. And waited. But, in the end we found out that it did work ;-) Best regards, BenArticle: 83837
Alexander Korff wrote: > I looked in the Quartus manual an read the chapter on "timing analysis", but > even the Webcast which is available from alter gave me no clue what to do. > Is there some more literautre about this problems or an practical example ? > I'm for example not sure at which time I would set the hold time ? > > Wit best regards. > > Alex > Sorry, was out of the country for a few days. The idea is that you need to tell Quartus when data at your input pins will change with respect to the external clock. In Quartus STA, this is called Tsu and Th assignments. There is some help available inside Quartus about the subject. But it's standard know-how, so I guess good books must teach it. I think Clive's nice and easy to read : "The Design Warrior's Guide to FPGAs" http://search.barnesandnoble.com/booksearch/isbnInquiry.asp?endeca=1&isbn=0750676043&itm=9 has a chapter about STA (OTOMH, I don't have the book at hand) In our 2-days Altera Design course, we spend over 3 hours (& 2 exercises) on STA and timing constraints. This is key to designs that work. The situation can become more complex when you deal with isosynchronous clocks at fractional frequencies (like F2 = F1 *4/5). QII STA does even know how to calculate this kind of timings ! (I would still recommend async Fifos to cross such boundaries though) Let me know if you really can't find the right information (which I doubt) Bert CuzeauArticle: 83838
Ben, See below, Austin Ben Twijnstra wrote: > Hi austin, > > > >>>There's addtitional bit lanes in Altera devices too. >> >>To do what? > > > Oh, for 9-bit video data, or parity checking, or ECC, whatever you like. > Yes we have an extra bit for evey 8 bits as well. Most folks just use it for parity. > >>>So what does this add then? Did you add optional hard ECC >>>generation/detection blocks to these 9th/18th bits? Or does the user have >>>to code this him/herself? > > >>We have hard ECC, 72/64 code, that can be instantiated to provide single >>bit error correction, and doulble bit error detection with no soft IP >>required. > > > That's exactly what I wanted to know. So, to summarize: > > If activated, a 64-bit write to a BRAM will use 8 additional bits for > error-checking and recovery. The read and write ports have optional > dedicated hard logic that, when enabled, generate and check ECC data. > Yup. > By the way, does this ECC stuf work on narrower RAM widths? > Nope. Customer has to insantiate whatever external muxes they would liek to use the ECC with other widths. We felt that this extra muxing was trivial for the customer, where if we had to do it, it would make the block less useful and bigger for all the customers who don't want or need ECC. Given the FIT/Mb rate of the BRAM is already 6 to 8 times better than commercial SRAM, many customers evaluate the risk, and decide to use simple parity rather than ECC. > >>>Also, do the V4s run continuous config sanity checks like Altera's >>>devices? >> >>We allow the custoemr to decide what they want to do: they can do just >>a check, or a check and correct, or nothing at all. They pay the least >>possible because we only harden what we need to enable this feature, not >>the whole thing. What A offers is a "oh no!" bit: if it is set, you >>have no recourse but to reconfigure and start over. That is all A >>allows the customer to know, nothing more. > > > In A, the config error pin will allow you to take any external action. > Rebooting the device is the most common application, but more elaborate > schemes are possible. Also, the internal logic is also able to respond to a > config error. Then again, since the configuration cannot be trusted > anymore, it would be best to bring the circuit offline as quickly as > possible. I'm A is so smart (sarcasm), and know exactly what to do for their customers. We, on the other hand do not presume to tell the customer what they must do. Since only 1 in 10 to 100 bit flips actually does anything at all, there is a 1 to 10% chance that the FPGA is still able to decide what to do. In fact, if you triplicate a "sanity check" monitor, and allow it to make the decisions, you do not have to tear down the whole chip for every hit. That takes very little extra logic. You see, A's "oh no" bit will trip 10 to 100 times more often than an actual functional failure: why take the system down 100 times more often that you really need to? Not very bright. Running around saying "I've been hit, I've been hit ...." Insteaad we offer that you can decide if you should flip just that one bit, and just continue on from there. If it is a video, voice, or packet application, what risk was taken? A bad pixel? A pop or click? One bad packet? Those things happen all the time for other reasons than SEU. No interruption. A's solution can not do that. "Help me, Help me! I've been hit, and I don't know where! I might be dying, (but I am probably OK, but you can't trust me anymore." I much prefer a more elegant solution: "Bit XYZ has flipped, do you want to flip it back?" > > The 'reloading-while-running' feature in X is cool, but if I were an FPGA > and I knew I couldn't be trusted anymore, Asimov's first law would kick in > and I'd disable myself ASAP (i.e. after sticking a Post-It to my forehead > indicating that a service technician should look me over because I went > crazy). Yes, I know, it is all A has to sell, so make sure there is lots of FUD associated with the X solution (since it can't be matched by A). I think it quite nice that their "solution" to SEUs is their hardcopy: less competition for FPGA vendors! Gartner-Dataquest removes all hardcopy revenue from A's balance sheet when comparing them with other FPGA vendors now. Their sales may be increasing, but their FPGA market share is decreasing. Too bad they just don't seem to be interested in playing with us anymore. No MGTs in S2, No processor. S2: 2 many upsets, 2 hot, 2 slow, 2 noisy; 2 little, 2 late, 2 bad. > > >>The same IP also allows the customer to flip bits so that they can see >>what effect NSEUs would have without having to go to a neutron beam >>(which is very expensive,, and time consuming). > > > Very nice idea indeed. After getting the first documentation about A's > sanity checking we actually had to go to a nuclear lab to test the feature > (the lab was also quite interested in the feature). We didn't do any > quantitative testing (how could we, as humble end users), we just stuck the > PCB in a high-intensity neutron beam and waited. And waited. And waited. > But, in the end we found out that it did work ;-) Does it? How do you really know? They could count ten errors, and then say "I've been hit" and you would never know the difference. How do you know that the ckecker wasn't hit? Do they provide a hearbeat so you are sure the checker is checking? We do. I say, have them prove that every single bit can be tracked. Upset rates are different for LUT, DFF, RAM, config. Do you know what is checked? On V4, it is very clear what is being monitored. And you know what is happening all the time. If you are really as paranoid as you claim (WCGW, WGW, AATWPM - what can go wrong, will go wrong, and at the worst possible moment), I would think not even knowing what is checked, and what flipped would drive you crazy.Article: 83839
ALuPin wrote: > The problem is that I have no time to register the incoming signals > so that I could work with the outputs of that register stages. > Instead I have to send data on the bus directly. Very unclear to me. In a bidir, you have two worries : - In data : this is Tsu & Th - Out data : this is Tco and nobody can guess without knowing precisely what you have on the other end. As of "having no time etc...", I fear the worst... (data used at several places in the design without any resynchronization : good luck in this case !) btw : Leave the "Cut of feedback from IO pins option" to "On" (default) unless you read from yourself (very unlikely !) -> don't use global constraints for your IOs since very likely only some pins will have these constraints. Bert CuzeauArticle: 83840
many thanks for these answers and advices. Some more questions: - How is the IP licence managed? I mean, in evaluation mode, is there a time limite (or whatever) in ISE web edition, is it downloadable or do I need to get in touch with Xilinx sales men? - When buying IP, are there royalties on each PCI board sold? What is the difference in the IP with those different licence? Are there some limitations? - Are IP availble in a complete set of VHDL code etc or is it a precompiled file set? - Could you give me a link to Xilinx PCI IP core, there are many available on their website, I don't know which you are talking about? My project is mainly an evaluation/learning project. I want to learn FPGA designs with a real and complete project (software, driver, digital design, hardware) that could be done in any company (I've studied VHDL/ Verilog years ago but only with simulations). Since my budget is not so large, I would like to least estimate my project costs (with commercial IP in evaluation mode first, then if the project is a succes, I plan to buy them) before starting and asking for funds to some company that would be interested in this project (some are ready to help me and wait for my budget estimation). Best regards John Adair a écrit : > If you are just looking to experiment then the Xilinx PCI Core can be run on > evaluation mode. Buy costs vary on license 32bit / 33MHz of the order > $2000-5000. If you are a student there are education licensing as well. I > believe there is one on opencores but it;s size may be quite large. > > $40 does not go far and Virtex and Stratix families are almost certainly out > of that range unless you happen to be an extremely large user or go for the > smallest parts in the range. For automotive applications Spartan-3 is a good > fit for your application although I'm a bit biased to Xilinx. It is getting > very difficult to get parts that are not BGA, or fine pitch like the QFN, > let alone larger parts in an easy to use package. We should have something > for hobby / student market in the shape of a low cost module in 2/3 months > to assist with this problem. > > For simple size comparision I would use number of raw LUTs and flip-flops > followed by memory size /organisation. The latter is not always simple as > block rams can sometimes be inefficient for given applications. Xilinx have > an advantage in this area with the ability to do local rams and shift > register elements SRL16s from LUTs. This resource is in addition to block > rams. > > Low cost processors I would look at opencores. Processors like MicoBlaze can > be evaluated free but the kit does cost $495 if you need to buy the license. > > If you need a very large memory then bear in mind that FPGA ram is > relatively expensive. However standalone Dual Port Memories are getting > expensive too. For the large FIFO consider using a single interface memory > ram, or dram, and use your FPGA as a controller to time multiplex access the > data reads and writes. Smaller FIFOs are good things to do in your FPGA. > > John Adair > Enterpoint Ltd. - Home of MINI-CAN, PCI and CAN Development Board. > http://www.enterpoint.co.ukArticle: 83841
Thanks for advice. I am actually a hardware designer. I graduate as an electronic engineer and did a lot of digital and analogue design (I even designed an RF system on silicon (.6micron technology CMOS)). I also wrote a lot of device driver and now I am writing device driver for FPGA boards and for this reason I have access to some advanced FPGA boards. The FPGA section normally designed by others and I only do the software section but I think I would learn VERILOG to find what they are doing and probably changing some part of their design so it will fit better to software that I design. I also have an old FPGA with Xilinx SPRATON which connects to PC by parallel port. I think I would start learning how to program it and then I can move to some boards that will be installed on PCI bus. I have ISE 6.3 but I don't have any simulator. Any suggestion for a good free simulator? Best regards <andyesquire@hotmail.com> wrote in message news:1115481403.348465.219980@g14g2000cwa.googlegroups.com... > Hello Ma, > > I started digital design as an experienced programmer. I'm sure other > people who have followed the same learning path will tell you that this > can actually be a real disadvantage. > > Your programming habits and developments methods will generally not > migrate well to digital design. > > Thinking VHDL or Verilog is a programming language is the first trap to > avoid, this leads you to think that you can use the same development > methods. For example, while it's easy to start small programming > projects by just hacking out a few classes, and modifying the design as > you go along (a bad habit of course) I personally found this approach > totally impractical for digital design work. > > I don't mean to dampen your spirits, simply to save you a lot of > frustating hours on the learning curve. Before you jump in head first I > would suggest reading some good books that include information on HDL > inference and synthesis if you haven't already, as this maybe > particulary hard to get to grips with for programmers. > > I'd suggest VHDL Design Representation and Synthesis, by Armstrong and > Gray, although I'd read this after one of Peter Asheden's books. > > As for tools, well both Xilinx and Altera have free tools so I'd start > there. > > Just my 2cents. > > Andy. >Article: 83842
Hope not being too much OT here. I think the cheapest PCI platform might well be the MaxII kit. Alas, the MaxII doesn't have the "guts" to be an SOPC platform, so if you absolutely want an embedded processor, you'll need another board. But if you first want to get familiar with PCI and test an actual solution, it might be an easy start. Bert CuzeauArticle: 83843
thanks, these board seems to be cheap but my goal is more designing digital around automotive busses than coding drivers and learn PCI bus. I bookmarked this board. info_ a écrit : > Hope not being too much OT here. > > I think the cheapest PCI platform might well be the MaxII kit. > Alas, the MaxII doesn't have the "guts" to be an SOPC platform, > so if you absolutely want an embedded processor, you'll > need another board. > But if you first want to get familiar with PCI and test an actual > solution, it might be an easy start. > > Bert Cuzeau >Article: 83844
Clock delay is the time elapsed between sending the clock and its arrival at a specific destination. Clock skew is the difference in arrival time at different destinations. Larger chips unavoidably have a longer clock delay. That's why DLLs, DCMs and PLLs are so important, for they can reduce the clock delay to zero, completely eliminating it. Clock skew cannot be reduced by DLLs and PLLs, it can only be minimized by careful clock routing structures and generous buffering. Excessive clock skew can lead to hold-time problems or to reduced performance, depending on the direction of the clock delay difference. If the clock is delayed in the direction of the data flow, there is the danger of hold-time violation. It the clock is delayed in the opposite direction, max performance is reduced. Modern FPGAs try to keep clock skew below a few hundred picoseconds. Peter AlfkeArticle: 83845
Piotr, A single chip solution that has 5v tolerant I/Os is the XPGA125 device from Lattice. This is an sram device with integrated E2 memory, so the device is totally secure. You can download the sw for free. http://www.latticesemi.com/products/fpga/xpga/index.cfm The newer XP device is not 5v tolerant, but more cost effective and still non volatile. Either way both devices are fully secure & reconfigurable. Piotr Wyderski wrote: > Hello, > > I need an FPGA chip which fulfills the following constraints: > > -- it has at least 64 IO lines; > -- it is not very fast, 133MHz is the highest possible internal frequency; > -- it contains about 500--1000 LE; > -- very important: it can directly communicate with 5V TTL devices, > this means that its inputs are 5V-tolerant, or better: its V_io = 5V; > -- the software can be easily obtained and is cheap or even free, > so perhaps only Altera and Xilinx should be considered as possible > vendors; > -- it is relatively cheap; > -- built-in configuration memory would be a great feature (because of > piracy). > > What would you recommend me? > > Best regards > Piotr WyderskiArticle: 83846
but where should I add the linker? Is it right that I right click the project name and then choose "set compiler options"-directories-filling the blanks of "link options": libm.a-lmArticle: 83847
What about the "search path"? Shall I fill the "library" with the install path of libm.a---...\gnu\powerpc-easi\nt\powerpc-easi\lib\ who knows, please? thank you for all your help!Article: 83848
"Simon Peacock" <simon$actrix.co.nz> wrote in message news:427c8dbc@news2.actrix.gen.nz... > Why not use Linux for the PPC.. its a standard port :-) > Thats what those links were for see http://www.denx.de/twiki/bin/view/DULG/ELDKSupportedTargetArchitectures and http://www.klingauf.de/v2p/index.phtml But it depends on what the person getting it running is more familiar with and has used before. AlexArticle: 83849
Hi Piotr, >> Maybe a CPLD instead of an fpga may be a better choice in your case. > > Hm, I don't think so, large (512+ cells) CPLDs are very expensive. > But an ACEX FPGA seems to be a reasonable candidate (250MHz, > 5V-tolerant, available in the TQFP100 and TQFP144 packages and > they have more than enough cells). FLEX6K are good too. If you are willing to use resistors/translator on inputs, you can also consider Altera's Max II family (specifically the EPM1270 in this case). You've stated a "133 Mhz" operation requirement, but the speed of operation is a combination of what your design is doing and the speed of the device. I'm sure you know this, but even though an ACEX can be clocked at 250 Mhz doesn't mean all designs will run that fast. The EPM1270 gives you 1270 4-input logic elements, integrated configuration memory, and very high operating speeds. Good luck, Paul Leventis Altera Corp.
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