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Please make that Princeton University Press.Article: 84276
"Candida Ferreira" <cferreira@seehomepage.com> writes: > "rickman" wrote: > > > I don't follow. Multiplexers are as complete as any logic element. > > I'm not sure what you mean by a 3-multiplexer, but I will assume you > > mean a 2 input mux with a single control input. You can get a NOT > > function by putting a 1 on the I0 input and a 0 on the I1 input and > > your signal on the sel input. > > That's true and does not contradict the definition of a ULM, but you need > the 1 and the 0 to create a NOT. Without them you cannot create a NOT with > the 3-multiplexer. But there are other functions, such as the NAND and the > NOR functions that, by themselves, can create any other function, without > needing the NOT, the ZERO and the ONE. These are the ULMs I want to > distinguish from the more ordinary ones. Do you mean, they are _generators_ for whole family of binary functions ? MB PS: there's a booklet by Emil Post on this subject of binary functions. Forgot the title, sorry. -- Michel BILLAUD billaud@labri.fr LABRI-Université Bordeaux I tel 05 4000 6922 / 05 5684 5792 351, cours de la Libération http://www.labri.fr/~billaud 33405 Talence (FRANCE)Article: 84277
The main difference is in whether you sample on negedge or posedge and similar for the other side. For low frequency (100M or lower) you can almost always simple choose the mode where both side transmit on the negedge and sample on the posedge (or vice versa). While this can help setup/hold issue this has the disadvantage of using only half of the period. Therefore on higher frequency system were you can't pass the information in half period you will need both side to transmit on (the same edge e.g) posedge and sample on the posedge and if you have setup/hold issue take care of them in other ways. Have fun.Article: 84278
Hello, I'm brand new to the world of FPGA's and would like to know if I can implement a gated oscillator using a NAND gate (the output tied back to one of the inputs, and the other input as the gate) within my Cyclone I device? Thanks for the newbie help! Len GArticle: 84279
On a sunny day (16 May 2005 20:52:12 +0200) it happened Michel Billaud <billaud@labri.u-bordeaux.fr> wrote in <7zu0l3hulf.fsf@serveur5.labri.fr>: >Well, Java could could be the common platform for the rest of the world. But it would start rotating at a very slow speed.Article: 84280
This is not an Altera vs Xilinx issue. It has the same problem and solution in any logic circuit: 1. This oscillator will be outrageously fast, unless you insert additional delay in the feedback path. 2. when you turn the oscillator off (by pulling the NAND input Low) you will abruptly force the output High. That might generate a "runt" clock pulse if the output was Low. Solution: insert a flip-flop such that its Q drives the NAND control input. Use the D input connected to the asynchronous (active High) Preset of this flip-flop as the oscillator enable input. The flip-flop must be clocked on the rising clock edge. De-activating the oscillator will now occur right after the clock has gone High. Peter Alfke, Xilinx ApplicationsArticle: 84281
Hi Peter, I didn't mean to infer any kind of Xilinx/Altera issue or comparison, just wanted to say which one I was using. Thanks for the flip flop input. When using discrete logic, I get a clock of about 1.65 MHz, but don't know what it would come out to inside the FPGA. (obviously I need to practice with some real hardware sometime REAL SOON ;) LenArticle: 84282
Len wrote: > Hello, > > I'm brand new to the world of FPGA's and would like to know if I can > implement a gated oscillator using a NAND gate (the output tied back to > one of the inputs, and the other input as the gate) within my Cyclone I > device? > > Thanks for the newbie help! > > Len G Hi Len, You probably won't like my answer: Don't do it. Sure, you can create a circuit that behaves that way (I would call it a glitch generator rather than an oscillator!) but there are pitfalls: you might 'tune' the circuit to work on one FPGA and then recompile for a different device family and suddenly have different timing, or change a synthesis/fitting option and get a different result. In summary it can certainly be done, but in general it is not a reccomended design practice, at least in how I learned to do things. Would it be possible just to use a built-in PLL instead to get the clock you exactly want? Jesse Kempa Altera jkempa at altera dot comArticle: 84283
Hi Jesse, Well, I think it would be easier to - at least take my glitch generator out of the chip! I'm just trying to generate a clock that I can gate with Horizontal sync. I would then feed the clock to a counter/comparator to be used to set horizontal position for a title. I sort of had worries about doing it this way, so will just take the noise and go "outside". A CD4093 gives me a nice (slower) clock frequency to use, and since it's gated on every Horiz line, it stays quite stable. I don't have much experience w/ PLL's, so think I'd better keep it simple, at least for now. Do you mind if I send you an email at altera.com? Thanks, LenArticle: 84284
I agree, im also very frustrated about the general quality of the EDK product.. I wasnt able to synthesize the reference design for the ml401 either.Article: 84285
Hi, Len. If you dislike external ICs, you can make any FPGA (or CPLD) implement a very stable and reliable oscillator, using two external resistors + one C. Click on http://www.xilinx.com/xlnx/xweb/xil_tx_home.jsp and look for "Six easy pieces #3" by yours truly. It's always a safe bet to warn against asynchronous and analog circuit tricks, but sometimes they are the only way out of a bind... But these tricks do require a good understanding of circuitry, not just VHDL or Verilog. Peter Alfke, Xilinx (from home)Article: 84286
Hi Austin, Well, things are getting a little less busy with my day job, so I finally have time to start replying again... I figured I'd start with an easy one. > The fact that their LVDS works up to 1.3 Gbs in simulation is nice, but > can it be used in a real application on a real board? Yes. Stratix II has LVDS running at 1.3 Gbps reliably across process, temperature, voltage. Beautiful eye diagrams. In simulation and on the board. And as noted here (http://www.altera.com/products/devices/stratix2/features/performance/st2-perf_improvements.html), we will be increasing the spec to 1.25 Gbps in an upcoming version of Quartus II. BTW, our simulations line up very will with board measurements. We offer accurate IBIS models that we proudly stand behind. Regards, Paul Leventis Altera Corp.Article: 84287
HI Friend... thanx for the replies... Plese tell me what all files need to be modified. Control_mem is for sure. and also will we have to modily control_asm also ??? Please elaborate .... Some more help is highly appreciated... thanx again...Article: 84288
Hi Robert, Question 1: The two functions you list are equivalent. The first uses the D port of the register to bring in the registered data. The second uses the "synchronous load/asynchronous load data" port of the register to bring in the data, and sets sload = vcc so the data always comes through this port (never through D). This is done by the fitter automatically when it benefits timing or routability. >> Post-synthesis logic equation : >> ZD1_RD_PTR[1] = DFFEAS(ZD1_RD_PTR[0], H1_rd_fifo_rd_clk, !PIN_RSTN, , >> , , , , ); >> Post-fitter logic equation : >> ZD1_RD_PTR[1] = DFFEAS( , GLOBAL(H1L39), !PIN_RSTN, , , >> ZD1_RD_PTR[0], , , VCC); Question 2: There isn't any user-visible way to turn this optimization off, but it's perfectly safe so there's no reason to turn it off either. Bert, this transoformation is not tied to physical synthesis -- this is a transformation that is purely structural and the fitter is always free to make it. You are defininitely correct that physical synthesis can make changes to the synthesis output when it is enabled though. Regards, Vaughn Betz Altera [v b e t z (at) altera.com]Article: 84289
Hi Andre, Virtual pins essentially turn into registers in the current implementation, and hence require a clock for (at least most) timing constraints and the associated timing analysis. The message below is harmless. It is telling you that you didn't assign a clock to the Virtual Pin via the "Virtual Pin Clock" assignment, and that Quartus can't find a reasonable clock to use as a default clock for this Virtual Pin. Quartus searches the fan-in and fan-out cone of the Virtual Pin to see if there's a clock the Virtual Pin feeds or is fed by -- if it finds one, that becomes the default clock for this Virtual Pin. In this case it couldn't find a clock, so this Virtual Pin presumably feeds / is fed by combinational logic only. The code simply gnds the clock. If you don't care about timing analysis of paths starting or ending on these virtual pins, you don't have to do anything. If you do care about their timing analysis, you can use the "Virtual Pin Clock" assignment to specify what clock domain you want them to be part of. Or, you can simply specify a "Maximum Delay" timing constraint to or from these virtual pins, if that's easier and matches what you want. Hope this helps, Vaughn Altera [v b e t z (at) altera.com] <ALuPin@web.de> wrote in message news:1115906917.218629.31260@z14g2000cwz.googlegroups.com... Hi, I have constrained some pins in my top-level design as virtual pins: (Altera QuartusII v. 4.2 SP1 To Assignment Name Value Enabled Pin_name Virtual Pin On Yes ... After fitting I get the following warning message for all constrained output pins: Warning : Can't fit auto-select clock for virtual pins "Pin_name1" -- setting clock to GND Warning : Can't fit auto-select clock for virtual pins "Pin_name2" -- setting clock to GND ... When looking at the Quartus Help it is said under ACTION : Assign the Virtual Clock Pin logic option to an appropriate clock signal in the design. But I have not chosen a Virtual CLOCK Pin assignment but Virtual Pins !!! So why do I get these warnings ? Rgds AndréArticle: 84290
One slight clarification: it isn't impossible to turn off the optimization I list below, but it is a bit painful. Just in case you want to experiment though: You can write routing constraints to force a certain port to be used on a block, such as the D-input to the FF, rather than the sync_data input. The entire Quartus router can be controlled on some or all signal nets by a routing language we call .rcf. You can write constraints that say "use any routing for this net, but you have to end on the data D port of this register." You can write pretty much any other constraint you can think of too. See "Understanding the .rcf file" in the Quartus help for a description of the file format and how to use it to control the router. Normally it is only very advanced users who go to this level of control for highly performance critical parts of a design, or who need perfectly delay balanced routing for a custom source synchronous interface or some such, though. Regards, Vaughn Altera [v b e t z (at) altera.com] "Vaughn Betz" <no_spam@altera.com> wrote in message news:Smeie.1741$dS3.443774@news20.bellglobal.com... > Hi Robert, > > Question 1: > The two functions you list are equivalent. The first uses the D port of > the register to bring in the registered data. The second uses the > "synchronous load/asynchronous load data" port of the register to bring in > the data, and sets sload = vcc so the data always comes through this port > (never through D). > This is done by the fitter automatically when it benefits timing or > routability.Article: 84291
Past: I did a lot of leading edge (in terms of size) FPGA designs for ASIC prototyping. Size, usability, and cycle-time is of the essense. In the past, I have used Orca (1996), Virtex , VirtexE, and V2. About 5 years ago, I looked at Altera and Quartus pretty much shot them in the foot. Current: In the new design, I once again evaluated state of the art FPGAs. For this cycle Virtex4's timeline was a little too late (by a couple of months), so I started in StratixII (2S130s and 2S180s). So far, I have been very impressed with the tools and results. Note: Altera's FPGA is not totally symmetric. Different types of memory, different type of PLLs, only certain PLLs can do feedback, vertical I/Os are different than horizontal I/Os. I thought this would be difficult to keep straight. However, I am getting to realize the design I am working on is very not symmetric, so this has not been a problem. Memory: I first thought that having to worry about the different types of memory (512, 4K, 512K) was going to cause a accounting nightmare, but you can actually set it to decide for you. Quartus decides for itself which one to use. I really like this. Synthesis: I have been impressed with the synthesis results. Not as good as Synplify Pro, but it comes with Quartus II. We are having a problem where Synplify is not finishing on one of the FPGAs and having the Quartus synthesis engine saved us. Also, synthesis in Quartus takes about 2x-3x more computer time than synthesis in Synplify. Physical Synthesis: I was incredibly impressed with this since it is a check box (vs. psuedo-floorplanning with Amplify or hand modification with Precision). For me, it is the difference between closing and not closing timing. One note though, some of my design grow by 20% when I turn this on, so make sure you have a lot of head room. Logic: I really like the ALM. It does cut down on the number of levels the logic has to go through. This helps with timing. Despite what either Altera or Xilinx have to say, I really don't need a 1:1 ratio of logic elements to FF. About 10:1 ratio for ASIC prototyping is a better ratio. I would really like to see what other designers see. I would really like to see future families have at least 2x more logic vs. FFs. PLLs: I like the analog PLLs vs. DPLLs of Xilinx. One warning, if you set QuartusII to decide the PLL type, you may not get to use all the ratios. Kind of bizarre, but that is the way I interpreted the tool. I just set to only use Enhanced and the problem went away. General: The tool flow is a little bit cleaner, but the Xilinx tool flow was pretty good, so that is a wash. I am not a tcl expert, so it takes a little getting used to. I do like when you finally get all the tcl scripts right, you don't have to remember any switches, but once again a wash. Support: I am getting great support both locally and from the factory. Of course your mileage will vary and may ultimately determine your choice and your success. Not used: I did not use processors, high speed transceivers, other IOs. Cons 1: I was playing around with some different partition and I had a design that was 85% full (in terms of logic) and Quartus II could no route it at all (with no timing constraints). To be fair, I have other partitions with more than 90% that did route. In previous Xilinx devices in the Virtex* family, I only had problems closing time (i.e. routing did not fail) at 95%, so budget your size appropriately. Cons 2: Currently, there is no flash part that could program more than 1 of these large devices. It really makes the JTAG chain on the board needlessly complicated. -EdwinArticle: 84292
"John Williams" <jwilliams@itee.uq.edu.au> schrieb im Newsbeitrag news:newscache$0szjgi$c86$1@lbox.itee.uq.edu.au... > Hi Antti, > > Antti Lukats wrote: > > > anyone has made it own microblaze soc (eg not using ML401 derivate) where > > PLB is connected to microblaze OPB over bridge and some peripherals live on > > the PLB bus? I am struggling with this and can find the problem, for testing > > I just connected PLB GPIO, it seems to be kind of visible over OPB2PLB > > bridge, but there is defenetly any writes working :( > > > > This can be done and is used in ML401 ref design, but there seem to be some > > 'special gotchas' that one has to know to make it work, so if anyone had > > some problem with similar design and has some hints I would be extremly > > thankful > > I'm not quite understanding you here - what "gotchas" are you > describing? I was able to easily modify the ML401 reference design for > example to make it uClinux-capable, there were no tricks there. The PLB > bus had the DDR controller and Xilinx TFT VGA controller. Adding > another core on the PLB bus is simple. > > One thing to note, that design is very very tight on timing at 100MHz. > I did have trouble meeting timing when I started adding and moving cores > around in the system. Is that what you are talking about? > > Regards, > > John Hi John, no I had (still have other issues). I did it the hardway - started a fresh new design and added the OPB2PLB bridge, PLB SDRAM etc.. I had some 'thinking' about how to connect the clock's etc.. for testing I added one PLB GPIO, after peeking at ML401 and editing my MHS I got the PLB GPIO to partially working, eg if I write 2 times to the data port then the output is actually updated. So the OPB2PLB bridge and PLB bus are at least partially working. But then I added SDRAM to the PLB and that did not work at all. I messed up something in the MHS I guess, so probably I need to go the safe route and take the ML401 design and start modifying it. The bad thing is that when I load ML401 reference design into EDK 7.1 then 'generate address' buttong will cause the XPS to terminate itself :( I am not yet as far as fighting with the timings yet :) AnttiArticle: 84293
In article <d66kr2$mmk$1@blue.rahul.net>, Ronald H. Nicholson Jr. <rhn@mauve.rahul.net> wrote: >Are there any FPGA design tools which will run under Mac OS X? > >I've found that the Icarus Verilog simulator and synthesis tool >will run under OS X, but I'm not sure whether that's actually useful >for programming any current FPGA part. > While I think that OSX would make a great FPGA (and EDA in general) platform, I wouldn't hold my breath for support from any of the FPGA companies. You could use open source simulators like Icarus and GHDL (for VHDL) on OSX (I use GHDL on my Powerbook) to verify your design, but when it comes to synthesis there really aren't any viable open source options and there won't likely ever be due to the proprietary nature of FPGAs (unless someone comes up with an open source FPGA architecture). BTW: Why do I think that OSX would make a great EDA platform? Less support issues than Linux because there aren't multiple distros to support. [Don't get me wrong, I like Linux (I'm using it right now :). However, I'm wondering if Linux makes a good platform for 'closed source software' (it could if companies understood the Linux platform better). It's definately great for open source software where you install by compiling source (./configure;make;make install); but when the source isn't available it can be a pain (static linking or shipping libraries could really help, but it doesn't seem to happen).] OSX is more solid than Windows as well. This is especially important when you're talking about very large designs which might need to simulate for days, for example. OSX is a flavor of BSD Unix, after all. Apple also makes some very nice 'workstation-like' hardware (Dual 2.7MHz G5 with 2GB RAM makes a nice workstation.) And when Apple releases Cell-based machines the performance will be way ahead of anything Intel/AMD based. ;-) ...also a lot of software developers seem to be moving to Macs these days. If you go to a conference like OSCON (O'Reilly Open Source Convention) one of the first things you notice is that about half of the attendees are using Powerbooks. These are your bleeding-edge developers and they seem to be on to something. But again, I doubt you'll ever see any support for OSX from Xilinx or Altera (or even from the EDA companies for that matter). PhilArticle: 84294
Dear all, when synthesizing my design with XST, i get some messages like this one; "Flip-flop ... has been replicated 1 time(s) to handle iob=true attribute". The replicated flip-flops have their output shared between internal logic and IO pins. I understand that this replication could improve IO performances and that is the reason for adding such flip-flops on IOB. Am I right ? Moreover, both XST and Precision RTL show the same behavior in synthesis (under the default synthesis settings), so it seems this replication is strongly recommended. Can someone clarify this point ? Thanks in advance, GiuseppeArticle: 84295
Hi Vaughn, >If you do care about their timing analysis, you can use the "Virtual Pin >Clock" assignment to specify what clock domain you want them to be part of. >Or, you can simply specify a "Maximum Delay" timing constraint to or from >these virtual pins, if that's easier and matches what you want. thank you for your answer. Where in the Assignment Editor (which column)do I assign the Virtual Pin Clock for the Virtual Pins ? Rgds Andr=E9Article: 84296
In article <pan.2005.05.15.11.54.37.465174@PleaseDontSpamMEpolybus.com>, B. Joshua Rosen <bjrosen@PleaseDontSpamMEpolybus.com> wrote: >On Sun, 15 May 2005 04:57:06 +0000, Ronald H. Nicholson Jr. wrote: > >> Are there any FPGA design tools which will run under Mac OS X? >> >> I've found that the Icarus Verilog simulator and synthesis tool >> will run under OS X, but I'm not sure whether that's actually useful >> for programming any current FPGA part. >> >> Thanks. > >Get yourself a Linux machine (x86 obviously, not Linux on PPC) to run your >FPGA development environment. But even doing that is no guarantee. Unfortunately, you need to be running a very specific Linux distro in many cases (ISE 7.1 is a case in point - I've yet to get it working acceptably well under Mandrake 10 or Debian. I'm told that it should work better under Mandrake 10.1 - when I get a chance I'll try it. > You can use the Mac as an X-Server, but >thats as close as you are going to be able to get. It's inconceivable that >the FPGA or CAE companies would add a third platform. Well Big EDA (your Mentors, Cadences, Synopsys-es :) support more than 3 platforms already depending on the tool (Solaris, HPUX, Linux, Windows). I would imagine that it would be a lot easier to support OSX than it would be to support HPUX ;-) (if you've ever had to support HPUX, you know what I mean) But in general, you're right, they won't support another platform (OSX) unless they suddenly find a financially compelling reason to do so. PhilArticle: 84297
In article <1116263307.387705.217740@z14g2000cwz.googlegroups.com>, Andy Peters <Bassman59a@yahoo.com> wrote: >Alex Gibson wrote: >> "B. Joshua Rosen" <bjrosen@PleaseDontSpamMEpolybus.com> wrote in >message >> news:pan.2005.05.15.11.54.37.465174@PleaseDontSpamMEpolybus.com... >> > >> > Get yourself a Linux machine (x86 obviously, not Linux on PPC) to >run your >> > FPGA development environment. You can use the Mac as an X-Server, >but >> > thats as close as you are going to be able to get. It's >inconceivable that >> > the FPGA or CAE companies would add a third platform. >> >> What you mean like windows , linux and solaris ? >> (Most current tools don't support solaris) >> >> Shouldn't take to much work to go from linux to OSX >> (depending on how they implemented the port) > >ModelSim runs under a wish shell on Windows and Linux and Solaris, so >it seems to me that the port would be rather painless. > Yes, the port for something which has a Tk GUI (like ModelSim) would be painless, however it would mean running QA on another platform and that wouldn't be painless. >Of course, look how long it took Mentor and Xilinx to support Linux. > >> I'd be happy to beta test. > >So would I. Me too. However, when it comes to simulators there are already options available for both Verilog (Icarus) and VHDL (GHDL) simulation on OS X. You can simulate your design just fine on OS X, but you can't get it synthesized and into your FPGA. PhilArticle: 84298
"Len" <LeonardGabrielson@adelphia.net> schrieb im Newsbeitrag news:1116286221.349685.128570@f14g2000cwb.googlegroups.com... > Hi Peter, > > I didn't mean to infer any kind of Xilinx/Altera issue or comparison, > just wanted to say which one I was using. Thanks for the flip flop > input. When using discrete logic, I get a clock of about 1.65 MHz, but > don't know what it would come out to inside the FPGA. (obviously I > need to practice with some real hardware sometime REAL SOON ;) > > Len > the PLD or FPGA implementation would run way faster. But you can tailor it to your need to using different resources. A gated osc on XC9500XL that uses IOPAD (but no external components) runs above 40MHz. So thumb rule. A small immersed in FPGA fabric ring oscillator would run way faster. as said already the actual frequency is very dependand on the mapping and routing (speciall in FPGA!) so you should make a 'hard macro' and lock it down if you somewhat repeatable frequency. Another approuch would be to make a ring oscillator that runs as fast as it cans and you have an NCO circuit that is calibrated with correct coefficent to produce the clock you need anttiArticle: 84299
sps schrieb: > i guess u won't be able to simulate inout signals....simulator won't > give error but the signal will be missing How can I solve this problem ? I must simulate inout signals ... Any alternative ? Rgds Andr=E9
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