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Mike Treseler wrote: > Candida Ferreira wrote: > > > NAND and NOR functions by themselves can be used to describe any other > > function, including NOT, ZERO and ONE. > > True. NCR once produced a computer using only NAND gates. > It's a good bet that they didn't use any NAND gates to generate ones or zeroes! This sounds like a mathematician kind of question rather than engineering...Article: 84326
<amir.intisar@gmail.com> wrote in message news:1116335338.372911.196360@g44g2000cwa.googlegroups.com... > Hello all, > i am using the Spartan 3 (XC3s200). I have a clock signal > coming into my FPGA expansion port and all i want to do is have the > exact same clock signal going out of my FPGA, just delayed by about 3 > micro seconds.I am using verilog and ISE 6.3. What is the best way to > do this ???????. Thanks !!!!!!!!!!! > The best way to do this depends a lot on the nature and frequency of the incoming clock, the aboutness of the 3 microseconds, and the degree of sameness required on the output (once we agree that the word exact in this context can never be achieved). One example might be a clock of > 10us with somewhere high and low times of > 1us and an acceptable edge accuracy of +- 100ns. For this particular example a 30 stage shift register running off another 10MHz clock might be the best solution. For another example, requiring 10ns accuracy, triggering alternate 3us counters clocked at 100MHz on rising and falling edges might be a better solution. Cheers, AlfArticle: 84327
Use the Horizontal sync as enable to your counter and feed the dot clk
to the counter
Aurash
Len wrote:
>Hi Jesse,
>
>Well, I think it would be easier to - at least take my glitch generator
>out of the chip! I'm just trying to generate a clock that I can gate
>with Horizontal sync. I would then feed the clock to a
>counter/comparator to be used to set horizontal position for a title. I
>sort of had worries about doing it this way, so will just take the
>noise and go "outside". A CD4093 gives me a nice (slower) clock
>frequency to use, and since it's gated on every Horiz line, it stays
>quite stable. I don't have much experience w/ PLL's, so think I'd
>better keep it simple, at least for now.
>
>Do you mind if I send you an email at altera.com?
>
>Thanks,
>Len
>
>
>
--
__
/ /\/\ Aurelian Lazarut
\ \ / System Verification Engineer
/ / \ Xilinx Ireland
\_\/\/
phone: 353 01 4032639
fax: 353 01 4640324
Article: 84328
Gabor wrote:
> It's a good bet that they didn't use any NAND gates to generate
> ones or zeroes! This sounds like a mathematician kind of question
> rather than engineering...
A rose by another name.
I read NOT, ZERO, and ONE as
inverter, tied low, tied high.
-- Mike Treseler
Article: 84329
what's the frequency (period) of this clock ?
Aurash
amir.intisar@gmail.com wrote:
>Hello all,
> i am using the Spartan 3 (XC3s200). I have a clock signal
>coming into my FPGA expansion port and all i want to do is have the
>exact same clock signal going out of my FPGA, just delayed by about 3
>micro seconds.I am using verilog and ISE 6.3. What is the best way to
>do this ???????. Thanks !!!!!!!!!!!
>
>
>
--
__
/ /\/\ Aurelian Lazarut
\ \ / System Verification Engineer
/ / \ Xilinx Ireland
\_\/\/
phone: 353 01 4032639
fax: 353 01 4640324
Article: 84330No problem. That is what all of the wonderful features are for in V4 (SSIO, IODLY, DCM, etc.). All of the above go a long way to support the fabric. Even though the fabric will run at 500 MHz, it is far easier to mux it down to 200 MHz, or 100 MHz (using the built in SSIO features) which makes place and route easier, and also provides a lot of margin. Just go buy the ML450 board (network interfaces), and you will get a fully working platform to test out all of your ~ 400 MHz up to 500 MHz DDR interfaces. AustinArticle: 84331
Paul Leventis (at home) wrote: > You make good points. If you need 66, what does it matter if you get 70 vs. > 75? The problem is at the time most customers select a part, they do not > have a complete (or even partial) design. True. Picking an FPGA footprint can defer to the simulation of its contents. Making a board used to be a high risk, critical path, long lead time task. Four or five spins was the norm. The fpga was a detail and getting the software guys something to play with was the priority. Today boards have fewer parts with more balls, and making a board is not such a big deal. There is little reason to make a quick board for the software guys because all the interesting registers are in the fpga. HDL simulation is a critical path item. > In my mind, speed matters most as a time-saving feature. If the CAD tools > and chip you are using enable you to hit your performance requirements using > plain, architecture-agnostic HDL, push-button in the CAD tools, you've saved > yourself a bundle of hurt. Amen to that. -- Mike TreselerArticle: 84332
hello, I have a microblaze system with a uart and a timer (both produce interrupt).The interrupts are handled by intc.Uart interrupt is the highest priority followed by timer interrupt. 1. can microblaze read only the required data from the uart at a time.like say i want to get a frame from uart i.e data from one flag to another flag and then stop reading the bytes fro uart.When i tried doing this i realised that I have to read the whole file that i am transferring from the hyperterminal to the uart.but i dont want this to happen.any suggestions? 2. if the above behavior is not possible then i can send just one frame at a time to uart from the hyperterminal.if i do this the what happens is that my timer is also running at the same time.when it expires it interrupts the microblaze.But now if i send a frame to uart,it interrupts microblaze and then i stop getting interrupts from the timer.if i send another file (data) from hyperterminal to uart,it interrupts the microblaze properly but the timer has stopped working or otherwise its interrupt is not getting recognised. I thought that probably when i am in the uart_int_handler probably my timer interrupt was genearted and it was missed since i was in int. routine.Is this a possibility.?is yes ,how can i avoid this?I want to service the timer interrupt after i return fro the uart handler.my intc driver does not have XIN_SVC_ALL_ISRS_OPTION defined.so it does not allow me to use it in the code. Please share some information regarding this problem. Thank you all.Article: 84333
Paul, I understand how frustrated you are. We are 40% better in SEUs than V2 Pro (or V2). You folks must be really scrambling since you did absolutely nothing to reduce your SEU FIT rate (by using 90nm 6T cells for config). Enjoy your ??? FIT/Mb 90nm 6T config memory. Compared to S2, V4 is probably at least twice as good, perhaps even three times better. Actel will probably hire IRoC again to test us both. It will be fun to see that report! Unfortunately, since you do not support customer readback, we can't test your part in the neutron beam, as we could not really be able to count all the upsets, and where they actually occur. Not knowing must really be a pain for you guys. No way to really know if ICDES has accomplished anything at all. Separate FIT rates for config, and BRAM are a requirment for our customers, as well as having a number of techniques that can be used to mitigate the SEU issue, and a design flow to achieve any desired system FIT rate. I'd like to see your numbers for config and BRAM, as we are very satisfied with our improvements. It will be fun to watch as this sinks in the minds of the customers out there .... Sorry you can not say "we are just like Xilinx" anymore. I was glad to do all the work, but I am afraid that we will derive all the benefits now that we thought through all of the issues. AustinArticle: 84334
I'm trying to get a new board up and running, and the first order of business is trying to program a Virtex-2 and two XCF04 proms with a parallel cable. It's not working -- I can only identify the chain correctly occasionally, and can only program and correctly verify the PROMs once in a blue moon. I understand this might be a noise or signal integrity problem, but my board has 2 ground planes, the JTAG lines are short, and the power supplies are all clean. I lifted the FPGA configuration part of the design directly from an old board so it isn't a problem with the schematic, which only leaves layout. This time around I used .005" thick wires to route the JTAG lines where on the old board I used .008" thick traces, this can't be the problem can it??? Another weird problem is that my reset button isn't working either. I have the button wired to /PROG on the FPGA which should make the FPGA reload its code from the PROMs. It doesn't, it just sits there. It works fine on the old boards. Any suggestions?Article: 84335
Paul, Yes, you can get the fastest speed grade. Really a cheap shot, that one. I sense some real desperation. And, stop with the low-K dielectric. All of the Toshiba parts are low K. Guess what? We do not speed grade or power grade them differently, because it just doesn't make that much of a difference! Perhaps an ASIC can take proper advantage of low K, but the FPGAs just do not show much of an improvement at all. And stop with the power "advantages of S2." The Japanese engineer who touched the S2 and V4 chips on our demonstrator said it all: "S2 hot! V4 cool..." AustinArticle: 84336
"Paul Leventis (at home)" <paulleventis-news@yahoo.ca> wrote in message news:PaudnRAmKPtWBhTfRVn-vA@rogers.com... > Hi Peter, > >> But Altera cannot stand to be left behind. They get creative and apply >> a mysterious 1.3 multiplier which brings their EP2S180 up to 186,576 >> "equivalent LUTs", thus even bigger than the Xilinx behemoth. > > I believe that there is a fair bit of literature explaining where the > multiplier comes from. Perhaps you (and others) do not believe the > Stratix II vs. Virtex-4 comparison. However, we also have data on Stratix > II vs. Stratix utilizaiton showing ~25% higher utilization than you would > expect from straight LUT/FF counting. I certainly hope we are capable of > measuring our own chips. And previous (Altera-published) results showed > that Stratix I achieves a higher logic density than Virtex-2. So the 1.3 > multiplier is at least consistant with other results. > > Here is a link to a white-paper comparing Stratix II and Virtex-4 logic > densities. http://www.altera.com/literature/wp/wpstxiixlnx.pdf. And here > is another white paper on the ALM > http://www.altera.com/literature/wp/wpstxiiple.pdf. > > There are also two academic papers published in respected, referred FPGA > conferences. Both are authored by individuals who have established > reputations in the FPGA industry. The first paper describes the Stratix > II architecture, including a section on the ALM (Lewis et al, "The Stratix > II logic and routing architecture", Proceedings of the 2005 ACM/SIGDA 13th > international symposium on FPGAs -- > http://www.eecg.toronto.edu/~jayar/pubs/lewis/lewisfpga05.pdf). The > second is specifically on the ALM (M. Hutton et al, "Improving FPGA > performance and area using an adaptive logic module", International > Conference on Field-Programmable Logic and Applications 2004). > > The short version is that Adaptive Logic Module (ALM) can do 2 4-LUTs > (like a Slice or 2 Stratix LEs), but also can do a 5-LUT + 3-LUT, 6-LUT, > and other more powerful combinations (such as 2 6-LUTs that share 4 > inputs, etc). When you technology map a design into a specific look-up > table (LUT) size, you get a variety of LUT sizes -- you can't map all the > logic to use exactly 4-inputs (for example). Since you have a > distribution of LUT sizes, the capability to pair more than just 2 4-LUTs > into a single ALM will result in a decrease in the number of ALMs > required. > > Regards, > > Paul Leventis > Altera Corp. > > P.S. Ours is bigger -- and we can use it better too! Well then when are you guys going to have a low cost board similar to the spartan3 (or 3e) starter kit ?Article: 84337
Hi Dear Xilinx and users of Xilinx FPGA devices, Q: is it possible to use: 1) Xilinx ISE/EDK 7.1 all latest service packs 2) Xilinx platform usb cable (pld updated by impact 7.1) 3) target device Xilinx V4 LX25 4) EDK XMD (I think I tried all variants of them!) All the above are Xilinx latest and greatest! To my understanding its not possible to get them to work, XMD fails to connect or crash terminates no matter what I use. I have a fresh new dual CPU PC workstation (with NO PARALLEL port), I assumed that to be ok, as Xilinx has now the new and better usb cable. I have at my use: 1) original Xilinx Cable III - 1 pcs 2) amontec cable emulating Cable III - 1 pcs 3) Xilinx parallel Cable IV - 3 pcs 4) Xilinx usb cable - 2 pcs and all that hardware is piece of junk !! except amontec cable that I use regularly to program Atmel AVR's, as I can not use them as the XMD crashes for the system I need to use it for. I am really really really getting upset again over Xilinx EDK, the amount of time wasted with the fights with it! So the question, is it possible or not to use EDK 7.1 XMD, V4 and platform usb cable? [Y/N] An simple authoritave NO would be great help, I would not longer struggle then trying the impossible, of course if there is some trick to make it all work the better AnttiArticle: 84338
<Chris> schrieb im Newsbeitrag news:ee8e533.-1@webx.sUN8CHnE... > I'm trying to get a new board up and running, and the first order of business is trying to program a Virtex-2 and two XCF04 proms with a parallel cable. It's not working -- I can only identify the chain correctly occasionally, and can only program and correctly verify the PROMs once in a blue moon. I understand this might be a noise or signal integrity problem, but my board has 2 ground planes, the JTAG lines are short, and the power supplies are all clean. I lifted the FPGA configuration part of the design directly from an old board so it isn't a problem with the schematic, which only leaves layout. This time around I used .005" thick wires to route the JTAG lines where on the old board I used .008" thick traces, this can't be the problem can it??? > > Another weird problem is that my reset button isn't working either. I have the button wired to /PROG on the FPGA which should make the FPGA reload its code from the PROMs. It doesn't, it just sits there. It works fine on the old boards. > > Any suggestions? one the bluemoon eh :) the board traces defenetly are not the problem! its not that critical no way. can you download the FPGA from impact correctly? does it work? http://gforge.openchip.org there is FPGA as frequency meter application that supports V2 and parallel cable, does it work on your board(s) ? if you make idcode looping in impact does it report errors? http://gforge.openchip.org there is also VERY raw jtag test application, it loops 10,000 times 2 different jtag enquiries, and reports any errors does it run without complaing? the layout isnt the problem for almost sure, unless you messed up some important connection. the platform flash are more sensitive to JTAG behavior than other devices, that is the reason why xilinx had to make special 'tricks' into their XSVF player in order to correctly program the platform flash devices. maybe those problems are not any more there with current platform flash revisions, but there have been problems. and in generic the platform flash tends to be more picky on jtag issues. the PROG button erratic behavior also indicates you have some problem, are you saying that you can program the FPGA, the done goes high, you press your prog button and FPGA is configured? there is one not so well documented xilinx fpga jtag config behaviour, namly if an attempt to program the FPGA over JTAG fails, then the FPGA may be left in a state where initiatin serial mode configuration is not possible (eg the prog pin pulldown will not inititate new configuration) http://wiki.openchip.org/index.php/JTAG:Tips:Xilinx some more xilinx jtag tips anttiArticle: 84339
Chris,
check the power for all the IO banks, and try so slow down the cable
speed a bit to see if has any effect (for SI) check if INIT pin is
toggling when tou press /PROGRAM button (use a scope of a fast TTL
probe) by identifying the JTAG chain (from time to time) means that your
connection are OK, but you can have a problem with the grounding of the
cable.
Aurash
Chris wrote:
>I'm trying to get a new board up and running, and the first order of business is trying to program a Virtex-2 and two XCF04 proms with a parallel cable. It's not working -- I can only identify the chain correctly occasionally, and can only program and correctly verify the PROMs once in a blue moon. I understand this might be a noise or signal integrity problem, but my board has 2 ground planes, the JTAG lines are short, and the power supplies are all clean. I lifted the FPGA configuration part of the design directly from an old board so it isn't a problem with the schematic, which only leaves layout. This time around I used .005" thick wires to route the JTAG lines where on the old board I used .008" thick traces, this can't be the problem can it???
>
>Another weird problem is that my reset button isn't working either. I have the button wired to /PROG on the FPGA which should make the FPGA reload its code from the PROMs. It doesn't, it just sits there. It works fine on the old boards.
>
>Any suggestions?
>
>
--
__
/ /\/\ Aurelian Lazarut
\ \ / System Verification Engineer
/ / \ Xilinx Ireland
\_\/\/
phone: 353 01 4032639
fax: 353 01 4640324
Article: 84340There is a reference circuit for the MGTVREF pin on page 132 of the Virtex-4 RocketIO MGT User Guide. There is a resistor Refdes=R5 with a formula for calculating its value as follows: R5=(2.5v-VREF)/100mA where 2.5V is the pullup voltage, and VREF is 1.235V I am assuming the 100mA is the current flowing through both the VREF Diode (NatSemi LM385-1.2) and into the MGTVREF pin on the V4. 100mA seems a lot though, especially considering the LM385 operated over the current range of 10uA to 20mA, so stating 100mA implies that the FPGA is sinking 80mA? Through a 1Kohm resistor?? This would also make R5=12.65 ohms. Can someone from Xilinx clarify this? Thanks JasonArticle: 84341
I forgot something, check the power supply going to _all_ power pins of
XCF04
Aurash
Aurelian Lazarut wrote:
> Chris,
> check the power for all the IO banks, and try so slow down the cable
> speed a bit to see if has any effect (for SI) check if INIT pin is
> toggling when tou press /PROGRAM button (use a scope of a fast TTL
> probe) by identifying the JTAG chain (from time to time) means that
> your connection are OK, but you can have a problem with the grounding
> of the cable.
>
> Aurash
> Chris wrote:
>
>> I'm trying to get a new board up and running, and the first order of
>> business is trying to program a Virtex-2 and two XCF04 proms with a
>> parallel cable. It's not working -- I can only identify the chain
>> correctly occasionally, and can only program and correctly verify the
>> PROMs once in a blue moon. I understand this might be a noise or
>> signal integrity problem, but my board has 2 ground planes, the JTAG
>> lines are short, and the power supplies are all clean. I lifted the
>> FPGA configuration part of the design directly from an old board so
>> it isn't a problem with the schematic, which only leaves layout. This
>> time around I used .005" thick wires to route the JTAG lines where on
>> the old board I used .008" thick traces, this can't be the problem
>> can it???
>>
>> Another weird problem is that my reset button isn't working either. I
>> have the button wired to /PROG on the FPGA which should make the FPGA
>> reload its code from the PROMs. It doesn't, it just sits there. It
>> works fine on the old boards.
>>
>> Any suggestions?
>>
>>
>
>
--
__
/ /\/\ Aurelian Lazarut
\ \ / System Verification Engineer
/ / \ Xilinx Ireland
\_\/\/
phone: 353 01 4032639
fax: 353 01 4640324
Article: 84342Hallo all, I'm trying to implement Jam Byte-Code player using the source code(8051 Jam byte code player) provided by Altera. The code only supports version 1 Jam byte-code. But the Quartus II tool generates Version 2 Jam byte-code. What to do? Thanks a lot in advance. DaniArticle: 84343
"dani" <user100@bluewin.ch> schrieb im Newsbeitrag news:1116347285.812416.305220@g14g2000cwa.googlegroups.com... > Hallo all, > > I'm trying to implement Jam Byte-Code player using the source code(8051 > Jam byte code player) provided by Altera. The code only supports > version 1 Jam byte-code. But the Quartus II tool generates Version 2 > Jam byte-code. What to do? > > Thanks a lot in advance. > > Dani > there are even more 'variants' of the JAM/STAPL code, and even more issues. Unfortunatly it seems that while Altera is still using JAM internally it has completly dropped any support of JAM for 3rd party developers. I guess they where pissed off when the attemp to promote JAM as JEDEC standard failed. So Altera decided to "show off" and stopped publishing uptodate versions of the JAM tools. So basicall you are on your own, with no support from Altera, grab the latest what they have for download (what is ages old ASFAIK) and start updating the player to support whatever Quartus thinks the current JAM should support. You may have even to reverse engineer Q generated JAM files on that path. of course it all depends what you need todo, I implemented a simple JTAG bitstream loader for AVR, the all program code occupies less than 200 code words and uses very simple bytecode player. my 3cents AnttiArticle: 84344
<amir.intisar@gmail.com> wrote in message news:1116335338.372911.196360@g44g2000cwa.googlegroups.com... > Hello all, > i am using the Spartan 3 (XC3s200). I have a clock signal > coming into my FPGA expansion port and all i want to do is have the > exact same clock signal going out of my FPGA, just delayed by about 3 > micro seconds.I am using verilog and ISE 6.3. What is the best way to > do this ???????. Thanks !!!!!!!!!!! > Make the clock frequency 1MHz (say). Then just connect the clock straight through. It'll look just like it's been delayed by 3us. HTH, Syms.Article: 84345
> And, stop with the low-K dielectric. All of the Toshiba parts are low > K. Guess what? We do not speed grade or power grade them differently, > because it just doesn't make that much of a difference! So the long delay in getting the -12 speed grade out had nothing to do with this fab transition? It must be fun characterizing one product produced in two fabs with two different processes (one low-k, one not, and who knows what else is different). > Perhaps an ASIC can take proper advantage of low K, but the FPGAs just > do not show much of an improvement at all. I wish we had this "defie the laws of physics" technology you use on Virtex-4. First you claim your devices do not draw more current with increased voltage. Then you claim that increased metal capacitance has no impact on speed or power. I'm waiting for you to claim that I/O pin capacitance doesn't matter for performance, signal integrity or power... > The Japanese engineer who touched the S2 and V4 chips on our > demonstrator said it all: "S2 hot! V4 cool..." A very scientific test! Let's do some quick math here... Even if you found some demo with a 1W VccInt difference, this should only translate to ~10 C difference in chip temperature (still air, no heat sink on 2S60 --> Theta-JA = 10.4 C/W), which would hardly be discernable to the touch. Why was this demo so much hotter to the touch then? My educated guess (based on the analysis of one of our customers) is that you had unequal I/O settings, causing lots more I/O dissipation in our chip. Really, that is rather low. Regards, Paul Leventis Altera Corp.Article: 84346
If you happen to be using an "old" cable like Parallel Cable3, or some others like Digilient cable, can have problems, like you describe, if the voltage on the JTAG header is too low. I would check the level of the voltage as a starting point and see if that has changed. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan-3 Development Board. http://www.enterpoint.co.uk <Chris> wrote in message news:ee8e533.-1@webx.sUN8CHnE... > I'm trying to get a new board up and running, and the first order of > business is trying to program a Virtex-2 and two XCF04 proms with a > parallel cable. It's not working -- I can only identify the chain > correctly occasionally, and can only program and correctly verify the > PROMs once in a blue moon. I understand this might be a noise or signal > integrity problem, but my board has 2 ground planes, the JTAG lines are > short, and the power supplies are all clean. I lifted the FPGA > configuration part of the design directly from an old board so it isn't a > problem with the schematic, which only leaves layout. This time around I > used .005" thick wires to route the JTAG lines where on the old board I > used .008" thick traces, this can't be the problem can it??? > > Another weird problem is that my reset button isn't working either. I have > the button wired to /PROG on the FPGA which should make the FPGA reload > its code from the PROMs. It doesn't, it just sits there. It works fine on > the old boards. > > Any suggestions?Article: 84347
Paul, I am sure the newsgroup is getting really bored with this. I certainly am. Short and sweet: Two fabs: It is a challenge, but then having two qualified sources of supply is a definite advantage for our customers. Low-K: Don't get me wrong, I like low K, I like low pin capacitance too. I also like fine wine, and a good meal. I had already asked you to fab the S2 without low-K and measure it. We did that for V2 and V2P, and again for V4 at Toshiba and UMC. We know. You guess. Low power: What is low, is our power dissipation. The static leakage kills you folks as the part gets hot. And what FPGA in the high end isn't running hot? Yours just run even hotter due to the leakage (or require more expensive heatsink solutions). This one is so easy to prove it is silly for you to even try to compete on total power. AustinArticle: 84348
> Low-K: Don't get me wrong, I like low K, I like low pin capacitance too. > I also like fine wine, and a good meal. I had already asked you to > fab the S2 without low-K and measure it. We did that for V2 and V2P, > and again for V4 at Toshiba and UMC. We know. You guess. Do you like Spice too? Try taking a routing path and re-spicing with 20% lower metal capacitance. Either your chips have no metal in them or you'll see an improvement in delay with low-k. And yes, we have measured the difference in silicon. We fabbed Stratix in FSG and low-k; this was part of our qualification and testing of low-k. We didn't ever ship these low-k Stratix devices because we had sufficient yield into our fast devices. But we measured a performance advantage matching our expectations. > Low power: What is low, is our power dissipation. The static leakage > kills you folks as the part gets hot. And what FPGA in the high end > isn't running hot? Yours just run even hotter due to the leakage (or > require more expensive heatsink solutions). This one is so easy to > prove it is silly for you to even try to compete on total power. At worst we're talking about a 1W difference in 2S180-sized part, for worst-case leakage. How much dynamic power is being consumed in a chip that size? In the vast majority of applications it will be a fair bit -- somewhere in the 5-10W vacinity wouldn't surprise me. Our dynamic power advantage on logic/routing, RAMs, DSPs, and especially I/Os will cover the difference in static power. And where are those V4 worst-case leakage specs? It seems that you don't really have a handle on static power if a year after a product introduction you still don't know how bad it can be. BTW, did you notice that the 2S60/LX60 devices used in your recent net seminar had the same static power (extrapolate from the dynamic power data)? And I love how you imply that our 2S90 chip you tested is out-of-spec on leakage, when in fact it falls between our "typical" and "worst-case" spec. Regards, Paul Leventis Altera Corp.Article: 84349
Hi Alex, There are two Cyclone kits sold by partners of ours that are in the same price range: Future $49 Cyclone/Nios II eval kit: http://www.altera.com/products/devkits/partners/kit-future-badge.html Altium $99 kit: http://www.altera.com/products/devkits/partners/kit-alt-live-design.html With Cyclone II now available, I can assure you there will be low-cost Cyclone II dev kits available in the near future. Sorry, but I can't comment on exact dates. Regards, Paul Leventis Altera Corp.
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