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Messages from 84375

Article: 84375
Subject: Re: Help needed!!interrupt handling in microblaze system
From: =?ISO-8859-1?Q?G=F6ran_Bilski?= <goran.bilski@xilinx.com>
Date: Wed, 18 May 2005 09:53:14 +0200
Links: << >>  << T >>  << A >>
fpga00@gmail.com wrote:
> hello,
> 
> 
>   I have a microblaze system with a uart and a timer (both produce
> interrupt).The interrupts are handled by intc.Uart interrupt is the
> highest priority followed by timer interrupt.
> 1. can microblaze read only the required data from the uart at a
> time.like say i want to get a frame from uart i.e data from one flag to
> 
> another flag and then stop reading the bytes fro uart.When i tried
> doing this i realised that I have to read the whole file that i am
> transferring from the hyperterminal to the uart.but i dont want this to
> 
> happen.any suggestions?

The interrupt from uartlite is set when Receive FIFO goes from empty to 
non-empty. If you are not emptying the FIFO in your interrupt handler, you will 
not get any more receive interrupt.

> 2. if the above behavior is not possible then i can send just one frame
> 
> at a time to uart from the hyperterminal.if i do this the what happens
> is that my timer is also running at the same time.when it expires it
> interrupts the microblaze.But now if i send a frame to uart,it
> interrupts microblaze and then i stop getting interrupts from the
> timer.if i send another file (data) from hyperterminal to uart,it
> interrupts the microblaze properly but the timer has stopped
> working or otherwise its interrupt is not getting recognised.
> I thought that probably when i am in the uart_int_handler probably my
> timer interrupt was genearted and it was missed since i was in int.
> routine.Is this a possibility.?is yes ,how can i avoid this?I want to
> service the timer interrupt after i return fro the uart handler.my intc
> 
> driver does not have XIN_SVC_ALL_ISRS_OPTION defined.so it does not
> allow me to use it in the code.
> Please share some information regarding this problem. 
> Thank you all.

Timer interrupts and uart interrupts can of course be handled at the same time.
The interrupt controller will keep track on what interrupts are active. You have 
to clear the interrupts serviced in your interrupt handler.
EDK includes a default interrupt handler where you attach normal C function to 
handle each interrupt. More of this can be found in the documentation.

Göran Bilski

Article: 84376
Subject: Re: VHDL array question
From: "randomdude@gmail.com" <randomdude@gmail.com>
Date: 18 May 2005 00:53:58 -0700
Links: << >>  << T >>  << A >>
Thanks, I'll have  a read through it. I did search for the answer to my
problems via google - my apologies if i've asked a really simple
question.

Ta anyway :)


Article: 84377
Subject: Re: Auto-select clock for virtual pins
From: ALuPin@web.de
Date: 18 May 2005 00:58:03 -0700
Links: << >>  << T >>  << A >>
I have tried the following:

To               Assignment Name        Value         Enabled

Pin_name1         Virtual Pin               On             Yes
Pin_name1         Virtual Pin Clock   clk_90_sys    Yes

clk_90_sys is the clock net name of the clock coming out
of the Cyclone PLL. This clock is not routet to IOs, it is an internal
clock.

And yet I get the warning:
#WARNING: Virtual pin clock "CLK_90_SYS" for virtual pin "Pin_name1"
does not exist in the design - auto-selecting clock

In the HELP of Quartus I read the following:
CAUSE: You assigned the Virtual Pin Clock logic option to the specified
pin. However this pin does not exist in the current design. When this
condition occurs, Analysis & Synthesis automatically selects an
appropriate virtual pin clock.
ACTION: No action is required. To avoid receiving this message in the
future, assign the Virtual Pin Clock assignment to an existing clock
signal in the design.

But "clk_90_sys" DOES exist. So what I am still doing wrong?

Interesting thing: Some virtual pins do get an external clock coming
into the FPGA. For these
pins I do not get any warnings.

Best regards
Andr=E9


Article: 84378
Subject: Re: Which Simulators
From: "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk>
Date: Wed, 18 May 2005 09:34:25 +0100
Links: << >>  << T >>  << A >>
I would concur. We do exactly the same with a combination of licenses from 
these two vendors. ActiveHDL is very good at sorting file order out 
automatically and has in-built libraries that you don't need to compile to 
get going. The detachable waveform windows are very nice especially when you 
run multi-monitor machines like we do at Enterpoint. The cut and paste 
between these windows is also useful.

In the last couple of years Mentor have improved the user interface of 
Modelsim and I hope they will continue the trend. I think they got a bit 
complacent. Five years ago I would have said Modelsim was the best but now 
I'm not so sure.

Both these companies give out evaluation licenses so go try them out and see 
which you like best.

John Adair
Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development 
Board.
http://www.enterpoint.co.uk


"Ray Andraka" <ray@andraka.com> wrote in message 
news:uxyie.11092$jj.3577@lakeread06...
>I use a combination of Aldec and Modelsim PE.  Aldec is more user friendly 
>and is really a complete design entry suite where Modelsim is a simulator. 
>I prefer Aldec for ease of use.  Some customers insist on Modelsim, so I 
>have it.  Modelsim is about the fussiest VHDL parser you'll find, and it is 
>absolutely true to the LRM, so it does serve as a decent VHDL code check to 
>make sure you aren't doing something that is slipping past your other tools 
>but might get you in trouble down the road.  It is also useful to run on a 
>second machine while I'm, doing more design entry on Aldec.  If I were to 
>buy just one, my choice would be Aldec for the more complete design entry 
>suite, the better customer support and the lower price.
>
> -- 
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com  http://www.andraka.com
> "They that give up essential liberty to obtain a little temporary safety 
> deserve neither liberty nor safety."
>                                          -Benjamin Franklin, 1759
>
> 



Article: 84379
Subject: Re: Jam Byte-Code Player for 8051
From: "dani" <user100@bluewin.ch>
Date: 18 May 2005 01:37:33 -0700
Links: << >>  << T >>  << A >>
Thanks Antti,

Altera always talking about how successful the Jam Player is. I thought
this is the right way to implement CPLD update in field using software.
They publish the source code for Jam Byte-Code Player. But I'v never
found a description of the Jam Byte-Code format. And the source code
from Altera is also not well commented. If they do not really support
the Jam player, they shouldn't promote it as an easy using, portable
stuff.

Regards

Dani


Article: 84380
Subject: Re: Jam Byte-Code Player for 8051
From: "Antti Lukats" <antti@openchip.org>
Date: Wed, 18 May 2005 10:40:07 +0200
Links: << >>  << T >>  << A >>
"dani" <user100@bluewin.ch> schrieb im Newsbeitrag
news:1116405453.598651.58950@o13g2000cwo.googlegroups.com...
> Thanks Antti,
>
> Altera always talking about how successful the Jam Player is. I thought
> this is the right way to implement CPLD update in field using software.
> They publish the source code for Jam Byte-Code Player. But I'v never
> found a description of the Jam Byte-Code format. And the source code
> from Altera is also not well commented. If they do not really support
> the Jam player, they shouldn't promote it as an easy using, portable
> stuff.
>
> Regards
>
> Dani
>

oh well they promote it :)
just not updating the user resources and no support.

there are several non altera uses of JAM as well, as example FS2 and Actel
are using JAM, Xilinx tools can generate JAM (STAPL) but there is always a
potential problem that the versions do have mismatch or something prevents
the JAM useage. If you are working only with JAM files from single tool you
should be ok though.

Antti
PS several FPGA vendors promote their JTAG stuff, Altera JAM, Xilinx XSVF,
Lattice ispVM, etc.. all of them have problems. XSVF is changed with every
new version of impact, the old player doesnt accept the new commands...
everywhere about the same story



Article: 84381
Subject: Xilinx IP: PCI Express
From: "Andreas Loew" <fpgahardware@gmx.net>
Date: Wed, 18 May 2005 01:56:03 -0700
Links: << >>  << T >>  << A >>
Hi, we recently bought the PCI Express Endpoint Core from Xilinx and implemented it into a Virtex 2 Pro 50 device.

We have some experience with MGT connections and never had problems.

But up to now we could not get the core running. We expect that the core will be detected by the BIOS of our PCI Express PC - but nothing happened.

We could measure a stable reset pulse at boot-up of the PC. We expect that the signal trn_lnk_up_n will go high during link training and then goes low to indicate link up. But this signal stays low all the time.

BTW: We heard that the Spread-Spectrum feature of some mainboards is critical, but as far we can measure there is no modulation of the 100MHz mainboard provided clock.

Does anybody here have any experience with the usage of PCIexpress in FPGA ? Any suggestions welcome !

Regards Andreas

Article: 84382
Subject: Re: Xilinx IP: PCI Express
From: "Antti Lukats" <antti@openchip.org>
Date: Wed, 18 May 2005 11:06:42 +0200
Links: << >>  << T >>  << A >>
"Andreas Loew" <fpgahardware@gmx.net> schrieb im Newsbeitrag
news:ee8e58f.-1@webx.sUN8CHnE...
> Hi, we recently bought the PCI Express Endpoint Core from Xilinx and
implemented it into a Virtex 2 Pro 50 device.
>
> We have some experience with MGT connections and never had problems.
>
> But up to now we could not get the core running. We expect that the core
will be detected by the BIOS of our PCI Express PC - but nothing happened.
>
> We could measure a stable reset pulse at boot-up of the PC. We expect that
the signal trn_lnk_up_n will go high during link training and then goes low
to indicate link up. But this signal stays low all the time.
>
> BTW: We heard that the Spread-Spectrum feature of some mainboards is
critical, but as far we can measure there is no modulation of the 100MHz
mainboard provided clock.
>
> Does anybody here have any experience with the usage of PCIexpress in FPGA
? Any suggestions welcome !
>
> Regards Andreas

both nital and dinigroup have working xilinx PCIe FPGA boards. try dini
first see if they would be willing to help.

Antti



Article: 84383
Subject: Re: Jam Byte-Code Player for 8051
From: "dani" <user100@bluewin.ch>
Date: 18 May 2005 03:05:11 -0700
Links: << >>  << T >>  << A >>
Do you have any other information source which could be insteresting
for me? You can just drop me the links which I find on the Web.

Thanks

Dani


Article: 84384
Subject: Re: delays
From: amir.intisar@gmail.com
Date: 18 May 2005 03:11:27 -0700
Links: << >>  << T >>  << A >>

Gabor wrote:
> amir.inti...@gmail.com wrote:
> > Hello all,
> >             i am using the Spartan 3 (XC3s200). I have a clock
signal
> > coming into my FPGA expansion port and all i want to do is have the
> > exact same clock signal going out of my FPGA, just delayed by about
3
> > micro seconds.I am using verilog and ISE 6.3. What is the best way
to
> > do this ???????.  Thanks !!!!!!!!!!!
>
> Do you really mean 3 microseconds?  That's a *LONG* time in a
Spartan3.
> What is your input clock frequency?  Do you have another clock
running
> at a much higher frequency?
>
> If you really mean 3 microseconds, and you have a higher frequency
> clock
> I would suggest using a shift register.  If you meant 3 nanoseconds,
> you
> need to use a DCM, preferably with external feedback, and use the
phase
> shift of the DCM to get your delay.


hi,
    sorry, i should have mentioned the clock frequencies. Basically,
the signal coming in is an "adcbusy" signal from an ADC converter. 1 -
Busy
0 - not busy (take data). This positive cycle on the adcbusy signal
lasts for about 1 micro second, followed by an 8 micro second negative
cycle and so on.. This is the signal i want to reproduce on the output
but with a slight delay. My Spartan3 is working at a woping 50 Mhz
(20ns) however.

I need to transmit the data to the PC in 1 micro second bursts, the
same time as the adcbusy poitive cycle. Thats why i am trying to
reproduce it at the output, but a delayed version.

....Cheers!!!!!


Article: 84385
Subject: Re: FPGA design under Mac OS X ?
From: "B. Joshua Rosen" <bjrosen@PleaseDontSpamMEpolybus.com>
Date: Wed, 18 May 2005 07:09:33 -0400
Links: << >>  << T >>  << A >>
On Tue, 17 May 2005 17:55:45 -0700, Simon wrote:

> B. Joshua Rosen wrote:
>> On Sun, 15 May 2005 04:57:06 +0000, Ronald H. Nicholson Jr. wrote:
>> 
>> Get yourself a Linux machine (x86 obviously, not Linux on PPC) to run your
>> FPGA development environment. You can use the Mac as an X-Server, but
>> thats as close as you are going to be able to get. It's inconceivable that
>> the FPGA or CAE companies would add a third platform.  
> 
> Well, that's nice in theory, but certainly with the Wind/U toolkit it's 
> a no-go. Some X widgets (especially pulldown menus) are rendered in the 
> top-left corner of the screen, and the first choice is unavailable. In 
> other cases, the program simply crashes with a BadAccess error.

That's curious because running the Xilinx tools with a Linux X-server
works just fine, that's how I run it, I wonder what's broken in the OS-X
implementation of X.


Article: 84386
Subject: CORDIC bit-serial vs. bit-parallel
From: m_oylulan@hotmail.com
Date: 18 May 2005 04:16:01 -0700
Links: << >>  << T >>  << A >>
Hello,

I'm trying to write a CORDIC macro for a polar transmitter FPGA design.
I've used the parallel approach, but when I do a timing estimation the
longest delay path is through the CORDIC routine, and limits the
maximum clock rate of the whole design to about 40MHz. Other parts of
the design on the same board need to run at much faster rate so I'm
considering using a bit-serial version.

As I understand it, the bit-parallel implementation has low latency and
therefore high throughput, but because of the the word-wide shifts it
clocks at a slower rate. Conversely, the bit-serial
routine has a high latency and low throughput rate, but allows the
board to run at a faster clock rate. Is this right?

My question is:

In the bit-serial implementation, you still need to perform the shift
operation on the entire word to select the right bit to send to the
bit-serial adder/subtractor, so how does this solve the problem of a
slow clock rate due to the shift operation?

Thanks,

Mees


Article: 84387
Subject: Re: VHDL array question
From: "Marc Randolph" <mrand@my-deja.com>
Date: 18 May 2005 04:34:52 -0700
Links: << >>  << T >>  << A >>

randomdude@gmail.com wrote:
> Thanks, I'll have  a read through it. I did search for the answer to
my
> problems via google - my apologies if i've asked a really simple
> question.
>
> Ta anyway :)

Howdy Alan,

Don't forget to search in groups.google.com... I found several
discussions on strings (which probably aren't what you think they are),
good VHDL books, and arrays - mostly in comp.lang.vhdl.

To answer your "compiler" question, if the schematic tool generates
moderately decent VHDL, then most synthesis tools (which is our term
for compiler) will generate decent stuff.  The last schematic tool I
used was one made by Mentor (before it changed its name several times
[the tool, not Mentor]).  I was pretty happy with its output, but I'm
sure it is way out of your price range.  You can search in
google.groups.com for more dicussion on this as well (in
comp.arch.fpga).

BTW, from the wording of your original question (especially the
que(0)='a' part), it seems like you are approaching VHDL as a typical
programming language.  You know that it is not, right?  When coding in
an HDL (either VHDL or Verilog), you have to think in terms of the
physical hardware you want (FF's, memories, counters, shift registers,
and individual bits being OR'ed or AND'ed together).

Have fun,

   Marc


Article: 84388
Subject: Linux on Xilinx ml310
From: Henning Zabel <henning@c-lab.de>
Date: Wed, 18 May 2005 13:59:56 +0200
Links: << >>  << T >>  << A >>
Hallo,

i try to install debian (woody) for ppc on the xilinx ml310, but without 
success.
It seems that the powerpc build in the fpga can't execute the binaries 
of the installer.

Has someone tried to install a complete debian or suse linux on the 
ml310 board ?

Greetings




Article: 84389
Subject: Re: FPGA design under Mac OS X ?
From: "JJ" <johnjakson@yahoo.com>
Date: 18 May 2005 05:35:01 -0700
Links: << >>  << T >>  << A >>
One other old solution would be to put a x86 board inside, atleast
thats what people did with earlier Macs, it was always a bit slower
than regular PC but then the heat would be quite a extra burden.

Don't know if Orange & the other guys are still in that business though.


Article: 84390
Subject: For accessing my SDRAM,what should i do?
From: ARRON <mlpei279@gmail.com>
Date: Wed, 18 May 2005 06:22:43 -0700
Links: << >>  << T >>  << A >>
I try to access the SDRAM in my program, and wait for enough time before writing data to SDRAM,but i find the value of SDRAM is FF,what should i do ? what is wrong?

Article: 84391
Subject: Re: For accessing my SDRAM,what should i do?
From: "Antti Lukats" <antti@openchip.org>
Date: Wed, 18 May 2005 15:35:41 +0200
Links: << >>  << T >>  << A >>
"ARRON" <mlpei279@gmail.com> schrieb im Newsbeitrag
news:ee8e5aa.-1@webx.sUN8CHnE...
> I try to access the SDRAM in my program, and wait for enough time before
writing data to SDRAM,but i find the value of SDRAM is FF,what should i do ?
what is wrong?

give more info in first place!
what board
what device
what sdram controller IP core
how its wired
etc..

there could zilions of problems.

the readout FF itself means nothing and is not enough to give you an answer

Antti




Article: 84392
Subject: Re: About back annotated simulations...
From: Mike Treseler <mike_treseler@comcast.net>
Date: Wed, 18 May 2005 06:52:58 -0700
Links: << >>  << T >>  << A >>
Vaughn Betz wrote:

> I definitely agree that STA provides 100% coverage, if you get all the 
> constraints correct.  But there are many designs where the constraints are 
> incomplete, or may not be completely correct, and in those cases timing 
> simulation provides some level of back-up test.

I agree a time sim can be a useful diagnostic
when design rules go wrong. However, it is not
an alternative to design rules.
A timing sim covers function and timing too
poorly to make a it an economical part of my
standard development loop.

> In designs with multicycles & cut paths set that I think there's value to 
> simulating to double-check you didn't cut or multicycle something you 
> shouldn't have.

One of my design rules is no multicycle paths.
I prefer pipelining.

> Generally such constraints are set manually, and hence there 
> is the possibility of an error in entering them.

True, but in a design composed of clocked processes,
and synchronized inputs, fmax is often the only setting.
It is impossible to verify synchronizers in simulation, so
I don't try.

> Of course, a timing 
> simulation is not guaranteed to catch a problem even if you did make a 
> mistake, but if you can afford the time, it may catch an issue.

It might. When a design does not operate in the lab as
it did in simulation either I violated a design rule
or I need to add one. In this rare event, a timing
sim is a useful tool.

> Most designs I see use asynchronous clears, and don't set a recovery and 
> removal timing constraint to make sure the reset release occurs sufficiently 
> far from a clock edge for the design to come out of reset cleanly.

That's a case of a design rule violation.
I'd rather fix the design than see
if it happens to work this time.

> Timing simulation provides some level of back-up, although 
> it's definitely a poor substitute for a disciplined reset strategy and a 
> static timing analysis on it.

I agree.

        -- Mike Treseler
> 
> 

Article: 84393
Subject: Q, BRAM initializing using INIT_0X
From: "pasacco" <pasacco@gmail.com>
Date: 18 May 2005 07:09:51 -0700
Links: << >>  << T >>  << A >>
Hi

I have consulted the following link to initialize BRAM.
http://www.fpga-faq.org/FAQ_Pa=ADges/0031_How_to_initialize_Blo=ADck_RAM.htm

and it works fine for one BRAM module.

Problem is when I use 2 RAMB4_S4 components (each address 9 to 0, data
3 to 0), thus totally 1024 addresses and 8 bit data width.

Goal to initialize as follows

address 0 : X"08"  -- opcode
address 1 : X"71"
address 2 : X"34"
address 3 : X"95"

I am trying but MODELSIM simulation is showing unsatisfactory result so
far .....
Could experienced one give comment for this?


--------------------------------------------------------------------
.=2E..
-- RAMB4_S4 declared ONCE as below
component RAMB4_S4
generic (
  INIT_00 : BIT_VECTOR :=3D
X"0000000000000000000000000000000000000000000000000000000000000000";
   INIT_01 : BIT_VECTOR :=3D
X"0000000000000000000000000000000000000000000000000000000000000000";
   INIT_02 : BIT_VECTOR :=3D
X"0000000000000000000000000000000000000000000000000000000000000000";
   INIT_03 : BIT_VECTOR :=3D
X"0000000000000000000000000000000000000000000000000000000000000000"
        )

.=2E..
-- 2 components of RAMB4_S4 are instantiated TWICE as below
RAM0: RAMB4_S4
generic map(
    INIT_00 =3D>
X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_01 =3D>
X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_02 =3D>
X"0000000000000000000000000000000000000000000000000000000000000000",
 INIT_03 =3D>
X"0000000000000000000000000000000000000000000000000000000000000000"
        )
port map(WE=3D>we, EN=3D>en, RST=3D>rst, CLK=3D>clk, ADDR=3D>addr, DI=3D>di=
(3
downto 0), DO=3D>do(3 downto 0));

RAM1: RAMB4_S4
generic map(
   INIT_00 =3D>
X"0100000000000000000000000000000000000000000000000000000000000000",
INIT_01 =3D>
X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_02 =3D>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 =3D>
X"0000000000000000000000000000000000000000000000000000000000000000"
        )
port map(WE=3D>we, EN=3D>en, RST=3D>rst, CLK=3D>clk, ADDR=3D>addr, DI=3D>di=
(7
downto 4), DO=3D>do(7 downto 4));


Article: 84394
Subject: Re: About back annotated simulations...
From: Fred C <fcez05@free.fr>
Date: Wed, 18 May 2005 16:41:11 +0200
Links: << >>  << T >>  << A >>
Hi,

I want to thank you for this discussion.
This highlights the criticity of static timing analyse, with a strong 
constraint coverage.
The fact is that the design I'm working on requires a high level of 
safety, as mentionned Phil Hays. This means the cleanest design, well 
constrainted. But even with 100% cov. I will also use back annotated 
simulations, but more to cross checking a bug in the timing analyser 
tool/or a miss in the timing constraints as you mentionned through your 
experiences.

Regards,

Fred Cezilly


Mike Treseler a écrit :
> Vaughn Betz wrote:
> 
>> I definitely agree that STA provides 100% coverage, if you get all the 
>> constraints correct.  But there are many designs where the constraints 
>> are incomplete, or may not be completely correct, and in those cases 
>> timing simulation provides some level of back-up test.
> 
> 
> I agree a time sim can be a useful diagnostic
> when design rules go wrong. However, it is not
> an alternative to design rules.
> A timing sim covers function and timing too
> poorly to make a it an economical part of my
> standard development loop.
> 
>> In designs with multicycles & cut paths set that I think there's value 
>> to simulating to double-check you didn't cut or multicycle something 
>> you shouldn't have.
> 
> 
> One of my design rules is no multicycle paths.
> I prefer pipelining.
> 
>> Generally such constraints are set manually, and hence there is the 
>> possibility of an error in entering them.
> 
> 
> True, but in a design composed of clocked processes,
> and synchronized inputs, fmax is often the only setting.
> It is impossible to verify synchronizers in simulation, so
> I don't try.
> 
>> Of course, a timing simulation is not guaranteed to catch a problem 
>> even if you did make a mistake, but if you can afford the time, it may 
>> catch an issue.
> 
> 
> It might. When a design does not operate in the lab as
> it did in simulation either I violated a design rule
> or I need to add one. In this rare event, a timing
> sim is a useful tool.
> 
>> Most designs I see use asynchronous clears, and don't set a recovery 
>> and removal timing constraint to make sure the reset release occurs 
>> sufficiently far from a clock edge for the design to come out of reset 
>> cleanly.
> 
> 
> That's a case of a design rule violation.
> I'd rather fix the design than see
> if it happens to work this time.
> 
>> Timing simulation provides some level of back-up, although it's 
>> definitely a poor substitute for a disciplined reset strategy and a 
>> static timing analysis on it.
> 
> 
> I agree.
> 
>        -- Mike Treseler
> 
>>
>>

Article: 84395
Subject: Re: VHDL array question
From: "randomdude@gmail.com" <randomdude@gmail.com>
Date: 18 May 2005 07:45:32 -0700
Links: << >>  << T >>  << A >>
Yeah, I'm trying very hard to visualise how the statements I make will
map to hardware. Finding it kind of hard though, so I'm hoping some
nice books will help me out.
Ta for the searching-google-groups tip, btw!

So are schematics compiled to VHDL which is then synthesised? I always
assumed the HDL was 'compiled' into a schematic which was then mapped
into the chip.

I'm determined to master this fpga marlarkey.. even if it takes me a
log time.. :) Thanks.

-Alan


Article: 84396
Subject: Re: Which Simulators
From: Ray Andraka <ray@andraka.com>
Date: Wed, 18 May 2005 11:21:10 -0400
Links: << >>  << T >>  << A >>
I use a combination of Aldec and Modelsim PE.  Aldec is more user 
friendly and is really a complete design entry suite where Modelsim is a 
simulator.  I prefer Aldec for ease of use.  Some customers insist on 
Modelsim, so I have it.  Modelsim is about the fussiest VHDL parser 
you'll find, and it is absolutely true to the LRM, so it does serve as a 
decent VHDL code check to make sure you aren't doing something that is 
slipping past your other tools but might get you in trouble down the 
road.  It is also useful to run on a second machine while I'm, doing 
more design entry on Aldec.  If I were to buy just one, my choice would 
be Aldec for the more complete design entry suite, the better customer 
support and the lower price.

-- 
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  

 "They that give up essential liberty to obtain a little 
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 84397
Subject: Re: An FPGA eval board at $49!!
From: "Gabor" <gabor@alacron.com>
Date: 18 May 2005 08:58:57 -0700
Links: << >>  << T >>  << A >>

Tommy Thorn wrote:
> At $49 it starts looking good for small throw-away prototypes.  It's
> hard to tell, but it looks like the PCB has two unpopulated spots.
SRAM?
>

I got one.  There are two unpopulated spots labeled "CY7C1041CV33"
which is a 4Mb (256Kx16) async SRAM.

It came with the ByteBlaster II Parallel Port download cable, 9- and
25-pin serial cables, a 9V 500mA "wall-wart" supply and a CD-ROM
with Quartus-II Web edition.

At $49.00 I can guarantee Altera is giving these things away to
win new design-ins.

The manufacturer is "Axiom Manufacturing" at http://www.axman.com
but you won't see this product on their website as it is private
labeled for Future Electronics.


Article: 84398
Subject: re:Registers replication on Xilinx IOBs
From: bigboytemp@hotmail-dot-com.no-spam.invalid (Big Boy)
Date: Wed, 18 May 2005 11:16:14 -0500
Links: << >>  << T >>  << A >>
It doesn't do it because the signal would take longer to travel that
path than if it's replicated, but also for more obvious reasons, and
I exaplin...

The signal at output of IOB register is not garanteed to be the signal
that would get to the input, after it passed via the IO pad net. 
There's a lot of external interference that can occur, such as noise,
..  Another example is if the output is sink-only (open-drain
output).  The IOB register may output a 1, while the IO pin is driven
a zero (by an external driver sharing the same trace).  This can even
also occur with push-pull output, if there's (for some reason)
contention on the IO pin.

So, for those reasons, if a register need feedback to the FPGA fabric,
but also require low output skew, then register replication is the
only solution.  To avoid warning, you could replicate the register in
your source code, but this could make the code more obscure.  You
could always put a comment that specify that this extra register is
for FPGA IOB register, the other for feedback.


Article: 84399
Subject: Re: FPGA design under Mac OS X ?
From: "Andy Peters" <Bassman59a@yahoo.com>
Date: 18 May 2005 09:28:43 -0700
Links: << >>  << T >>  << A >>
JJ wrote:
> One other old solution would be to put a x86 board inside, atleast
> thats what people did with earlier Macs, it was always a bit slower
> than regular PC but then the heat would be quite a extra burden.
>
> Don't know if Orange & the other guys are still in that business
though.

Not really cost-effective, what with throwaway $300 PCs!

-a




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