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Hi Peter, > But Altera cannot stand to be left behind. They get creative and apply > a mysterious 1.3 multiplier which brings their EP2S180 up to 186,576 > "equivalent LUTs", thus even bigger than the Xilinx behemoth. I believe that there is a fair bit of literature explaining where the multiplier comes from. Perhaps you (and others) do not believe the Stratix II vs. Virtex-4 comparison. However, we also have data on Stratix II vs. Stratix utilizaiton showing ~25% higher utilization than you would expect from straight LUT/FF counting. I certainly hope we are capable of measuring our own chips. And previous (Altera-published) results showed that Stratix I achieves a higher logic density than Virtex-2. So the 1.3 multiplier is at least consistant with other results. Here is a link to a white-paper comparing Stratix II and Virtex-4 logic densities. http://www.altera.com/literature/wp/wpstxiixlnx.pdf. And here is another white paper on the ALM http://www.altera.com/literature/wp/wpstxiiple.pdf. There are also two academic papers published in respected, referred FPGA conferences. Both are authored by individuals who have established reputations in the FPGA industry. The first paper describes the Stratix II architecture, including a section on the ALM (Lewis et al, "The Stratix II logic and routing architecture", Proceedings of the 2005 ACM/SIGDA 13th international symposium on FPGAs -- http://www.eecg.toronto.edu/~jayar/pubs/lewis/lewisfpga05.pdf). The second is specifically on the ALM (M. Hutton et al, "Improving FPGA performance and area using an adaptive logic module", International Conference on Field-Programmable Logic and Applications 2004). The short version is that Adaptive Logic Module (ALM) can do 2 4-LUTs (like a Slice or 2 Stratix LEs), but also can do a 5-LUT + 3-LUT, 6-LUT, and other more powerful combinations (such as 2 6-LUTs that share 4 inputs, etc). When you technology map a design into a specific look-up table (LUT) size, you get a variety of LUT sizes -- you can't map all the logic to use exactly 4-inputs (for example). Since you have a distribution of LUT sizes, the capability to pair more than just 2 4-LUTs into a single ALM will result in a decrease in the number of ALMs required. Regards, Paul Leventis Altera Corp. P.S. Ours is bigger -- and we can use it better too!Article: 84301
Hi, > I want a ROM in FPGA which is 85 bits wide, is it possible to have one? Yes. In Altera's devices, you just use the "lpm_rom" megafunction described in http://www.altera.com/literature/ug/ug_lpm_rom.pdf. The LPM_ROM lets you build a ROM of up to 256 bits wide by whatever depth you want; the Quartus II software will auotmatically figure out the best way to implement your ROM in the available memory blocks for the family you are targeting. For example, if you want to make a 96-bit wide by 32-bit deep ROM, the software might map it into three memory blocks, each 32-bits wide by 32-bits deep. For very shallow ROMs, you might be better off mapping to logic -- a 4-LUT is just a 16-bit deep by 1-bit wide ROM after all. I don't know the best way to do this (LPM_ROM only targets RAMs, I believe), but please ask if you are interested and I'll ask around to find out. Regards, Paul Leventis Altera Corp.Article: 84302
Hi, > If you have a true dual-port RAM, but need only a single port, you can > divide the RAM in two (evenly or non-evenly divided) pieces, and > address each from its own port. Now these two RAMs are completely > independent, but are each single-port. I should point out that Quartus II will do this for you automatically when additional RAM packing density is needed -- two unrelated single-port memories can be combined into one true dual-port RAM. Also, while it is true that in concept a "Simple Dual-Port" is just a "True Dual-Port" with one port set to always read and one set to always write, there are some electrical and modeling differences between the two. This difference results in different timing and power consumption. If you only need a simple dual-port RAM (one read, one write), you are best off instantiating the RAM as such. Regards, Paul Leventis Altera Corp.Article: 84303
Hi Austin, > For atmospheric upsets, it is a relatively easy process to change all > memory cells to SERT or DICE single upset hardened cells, with an increase > in area as you go from 6T cells to 12T and 16T cells in the ASMBL columnar > architecture which is actually trivial to do. Without the ASMBL > architecture, it requires a complete relayout. No offence, but this sounds like bull to me. So you are claiming that since you have columns of blocks (er, ASMBL architecture), you can suddenly tolerate changing the fundamental layout of your configuration RAM cells without touching anything else? This would imply that not only are your various blocks floorplanned as columns, but that the memory cells sprinkled throughout those blocks also line up perfectly and that no other circuitry would need to be adjusted. Regards, Paul Leventis Altera Corp.Article: 84304
Austin: > I am suprised at you. Their white paper clearly shows the simualtion is > done with the external termination, and not the internal one. > Use the internal one, and the capacitance does not matter (do the sim > yourself if you do not believe me). According to our engineer who ran the sims, we did use on-chip termination for both V4 and Stratix II. I read the whitepaper again (http://www.altera.com/literature/wp/signal-integrity_s2-v4.pdf) and I can't find anywhere where it says we didn't use on-chip termination. > The fact that their LVDS works up to 1.3 Gbs in simulation is nice, but > can it be used in a real application on a real board? Sorry to hammer on this again, but the above mentioned whitepaper does show some beautiful eye diagrams for SII and some ugly ones for V4. It also shows how nicely our lab measurement (of 1.3 Gbps LVDS on Stratix II) compares to the IBIS simulation. Regards, Paul Leventis Altera Corp.Article: 84305
Thanks for your suggestions,
I have used the option to strip the sections from the .elf file and it
worked fine.
Frank
"Peter Ryser" <peter.ryser@xilinx.com> wrote in message
news:d62scn$2vm1@cliff.xsj.xilinx.com...
> Use "-Wl,--section-start,.boot0=0x80000000" and start address 0x80000010
> for your environment.
>
> A third option: strip the .boot and .boot0 sections from the ELF file as
> they provide the means to jump anywhere in the 4GB address range,
> something you do not need in your case because you have your own
> bootloader.
> Example:
> $ powerpc-eabi-objcopy -R .boot -R .boot0 original.elf new.elf
>
> - Peter
>
>
> Peter Ryser wrote:
>
>> Frank,
>>
>> you have two options when you compile your application to reduce the
>> address range it spans ("its size"):
>> - write your own linker script. In that linker script map the .boot and
>> the .boot0 sections with the .text sections to the location of your
>> external memory
>> - use "-Wl,--section-start,.boot0=<address>" as a compiler option to map
>> the .boot0 section to your desired location. For example in XPS set the
>> start address of your application to 0x10 and use
>> "-Wl,--section-start,.boot0=0" if your external memory is mapped to
>> address zero.
>>
>> - Peter
>>
>>
>> Frank van Eijkelenburg wrote:
>>
>>> Hi,
>>>
>>> I have made a bootloader which runs from BRAM on a PPC. Now I want to
>>> download an application into external RAM and execute it. If I build my
>>> application and convert the .elf file into a binary file, the result is
>>> a 2 GB binairy file. This is because my external RAM starts at
>>> 0x80000000 and the startup up code contains a section called boot0,
>>> which is laid at 0xFFFFFFDC.
>>>
>>> AFAIK, the boot0 section contains a jump to my application (0x80000000).
>>> But, I think, the boot0 section is not needed. At startup the boot0
>>> section (in BRAM) contains a jump to my bootloader program and I don't
>>> want to overwrite it. How can I create a .elf file (or .bin file)
>>> without the boot0 section (but with initialisation/startup code)? In
>>> that case I can simply download my application through the bootloader
>>> into external RAM and jump to it.
>>>
>>> TIA,
>>> Frank
>>>
>>
>
Article: 84306Hi Joseph, First, I must stress that comparing "micro parameters" is difficult at best and dangerous at worst. There are fairly arbitrary decisions made during timing modeling about where you lump various delays. For example, where does "LUT delay" begin and end -- is it at the output of the 1st stage buffer after the multiplexor before the LUT? Or is that multiplexor's delay included as part of LUT delay? The Stratix/Stratix II/Cyclone/Cyclone II/Max II timing models are sufficiently complicated that there is little point to making datasheet entries for various internal timing parameters. For example, the ALM is fairly complicated and depending on how your logic is synthesized and exactly how the router chooses to hook it up, your delay can vary considerably. So your best bet is to look at real circuits with real timing constraints, since Quartus II will do its best to put the critical signals on the fastest paths. That said... As some posters have already pointed out, RAM speeds have increased in Quartus 5.0. The latest comparison I've seen shows us with a Tco advantage vs. Virtex-4 when the RAM output registers are used, and a slight disadvantage when the RAM is unregistered -- in either case a few hundred ps difference. As for LUT delays, here are the latest numbers I've got for a fastest speed grade 7-input LUT (ALM can do some inputs of 7-inputs, and all functions of 6-inputs), as well as for a 4-LUT (the ALM can do two independent 4-LUTs). Input 7-LUT 4-LUT A 378 ps 366 ps B 357 ps 228 ps C 240 ps 225 ps D 240 ps 53 ps E 144 ps F 53 ps G 234 ps According to Austin's post, Virtex-4 (fastest speed grade -- I dare you to try to buy one ;-)) shows 165 ps across-the-board (seems bogus to me, but what do I know). So which LUT is faster based on this data? Well, it depends on how we lumped our delays into logic vs. routing (see above). It also depends on how often Quartus II will manage to route your critical signal on the fast LUT inputs -- usually it does a very good job of this. The other critical component for logic fabric performance is the routing. Based on an analysis of routing delay between registers placed a varying distance apart in the X- and Y-directions, we've found that we have a ~20% delay advantage (fastest speed grade vs. fastest speed grade). Of course, even this type of study has its caveats -- how do you normalize distance to take into account differences in logic density? Stratix II employs a low-k inter-metal diaelectric (k = 2.9) vs. Virtex-4's "reduced-k" diaelectric (k = 3.6), given us a ~20% metal capacitance advantage. If you set aside architectural and circuit differences, to first order you'd expect this to translate into a performance advantage for Stratix II. Regards, Paul Leventis Altera Corp.Article: 84307
Here is one more opinion from a person that only does FPGAs from time to time. I guess that makes me a non-professional :) (The rest of the work time is spent doing hardware design and writing code.) Long time ago I was impressed by the Altera tools when I needed to do a simple CPLD, but found out that the A parts were much more difficult to get than X parts. So I ended up using 95xx. Mostly for this historic reason when it came to finding cheap FPGAs I have looked at the Spartan 2/3 line first. The free picoblaze was a big bonus too. Then I had to do another desing on a Cyclone and took another look at the A tools. A number of pleasant surprises. I wish the two giants would take the best features from the other one! So here is my list of great thing in one that is not in the other in no particular order. 1. Quartus has a fantastic tool to do both built-in logic analysis and modify the BRAM on the fly. ChipScope appears to be harder to use unless I'm missing something. For example it won't work unless all the inputs are connected to valid signals. No way to have spare inputs and do late routing. No way to read/write BRAM unless you write a JTAG utility yourself. Big plus to A. 2. Neat table view of the build results all in one place. 3. Timing results easier to track. On the other hand: 1. No free CPU. Had to make my own: Nios may be great but one hell of an overkill for my project. 2. Not enough BRAM in Cyclone. Does the Cyclone 2 exist outside the lab yet? 3. Very few development boards with A chips. So that project done I'm mostly back in the X camp. Wish they could add the memory access tool...Article: 84308
> Then there is the interconnect. V4 is 500 ps faster for full chip routes, > 400 ps faster for 1/2 chip routes, 100-200 ps faster for a few CLBs, LABs, > and 100-200ps for neighbor routes. Some very short routes are 30ps better > in S2. I would guess that you did not normalize to take into account packing density. How do you define a "short" route? Do you multiply the # of CLBs and # of LABs by the right ratio of logic? I'd argue that 1 LAB = 8 ALMs = ~10-10.5 slices (based on our density analysis). Anyway, the average distance of a hop in a critical path is roughly 3 LABs, so short connections are the most important. Our data shows a performance advantage in hops of this length. > Of course, anythign you can direct into the DSP48s will just scream, and > outperform anything S2 has. That's interesting... did you miss the news that we've increased Stratix II DSP performance to 550 Mhz in Quartus II 5.0? Not to mention that the S2 DSP can do 36-bit multiplies in hardware (vs. 18-bit for DSP48)... but I will not digress into a feature pissing contest. > I think that the newsgroup here will basically tell you to try a design in > both architectures, and play with the constraints to see how well it does. On this, I agree with Austin. Kick the tires. Just be sure to set timing constraints before doing so, and also make sure not use "toy" designs (neither tool is particularly well optimized for very small designs in very large chips). And beware numerical noise -- placement & routing is a heuristic. If you perturb any aspect of the input, the output can change due to random differences in algorithm outcome. Regards, Paul Leventis Altera Corp.Article: 84309
Answered last question by myself. I have made the virtual clock pin assignment in the Assignment Editor. To Assignment name Value Enabled clk_90_sys Virtual Pin Clock clk_90_sys Yes And yet when compiling the design I get the warnings described in my first post. The problem is that I NEED the virtual pins to be registered and therefore clocked because I want to have a look at them with SignalTapII. Or is that a problem because of using virtual pins ? Rgds Andr=E9Article: 84310
> Warning: Ranty, opinionated (and quite probably wrong): Those are the best kind of kind of posts... > How much does performance really matter? You make good points. If you need 66, what does it matter if you get 70 vs. 75? The problem is at the time most customers select a part, they do not have a complete (or even partial) design. You know your Mhz requirement, but have no idea if you will hit it. If you select a faster part, you are more *likely* to hit your Fmax target. How much more likely? Its hard to say. But consider the downside to missing performance. At best, you have to push the tools, or floorplan, or re-pipeline, or restructure your HDL. At worst, you need to respin your board, select a new product, maybe get a faster speedgrade, or change other aspects of your system design to accomodate a lower clock speed. All of this costs time, and time-to-market is one of the big FPGA sales points. Not all clock domains are defined by external requirements. Sometimes the faster you can run your core, the better the performance of your system (example -- graphics processor) even though your bus and memory speeds are still the same. Also, if you get fast enough in your internal clock domains, you might be able to cut the data width or multiplicity of your internal logic, allowing you to migrate into a smaller (and thus cheaper) part. In my mind, speed matters most as a time-saving feature. If the CAD tools and chip you are using enable you to hit your performance requirements using plain, architecture-agnostic HDL, push-button in the CAD tools, you've saved yourself a bundle of hurt. Its interesting -- we see the results of having fast chips and good out-of-the-box software performance, as these features translate into lower support costs of the "I need help meeting my timing" variety. Having speed is not enough. We have to have the features you need, but not too many as to exceed your cost requirements (is a feature that costs 3% but is only used by 1% of designers worth it?). Our software and support have to be up to your needs. And so on. But that won't stop us from discussing speed, or power, or SI in isolation of these other design requirements. Regards, Paul Leventis Altera Corp.Article: 84311
Hi Alex, Glad to hear you had a (mostly) postive Altera experience. I've sent your feedback on to the planning folks. And if you need a CPLD in the future, take a peak at Max II. > 2. Not enough BRAM in Cyclone. Does the Cyclone 2 exist outside the lab > yet? Yes, Cyclone II is available. The EP2C35 is shipping and the EP2C70 and EP2C20 will be shipping very soon (May and June respectively according to http://www.altera.com/products/devices/cyclone2/overview/cy2-overview.html). The product roll-out is going very well and devices are rolling out ahead of schedule. Regards, Paul Leventis Altera Corp.Article: 84312
inout simulations work fine in simulator. just simulate your code. There is no direction for your "t_Bidir_data". its local to TB.Article: 84313
> Do you mean, they are _generators_ for whole family of binary functions ?
Yes, exactly like NAND and NOR. Just to give another example, you can also
do that with the function a'c'+b'c.
Candida
---
Candida Ferreira, Ph.D.
Chief Scientist, Gepsoft
http://www.gene-expression-programming.com/author.asp
GEP: Mathematical Modeling by an Artificial Intelligence
http://www.gene-expression-programming.com/gep/Books/index.asp
Modeling Software
http://www.gepsoft.com/gepsoft/
Get APS 3.0 Std free with the book!
Michel Billaud wrote:
> "Candida Ferreira" <cferreira@seehomepage.com> writes:
>
> > "rickman" wrote:
> >
> > > I don't follow. Multiplexers are as complete as any logic element.
> > > I'm not sure what you mean by a 3-multiplexer, but I will assume you
> > > mean a 2 input mux with a single control input. You can get a NOT
> > > function by putting a 1 on the I0 input and a 0 on the I1 input and
> > > your signal on the sel input.
> >
> > That's true and does not contradict the definition of a ULM, but you
need
> > the 1 and the 0 to create a NOT. Without them you cannot create a NOT
with
> > the 3-multiplexer. But there are other functions, such as the NAND and
the
> > NOR functions that, by themselves, can create any other function,
without
> > needing the NOT, the ZERO and the ONE. These are the ULMs I want to
> > distinguish from the more ordinary ones.
>
> Do you mean, they are _generators_ for whole family of binary functions ?
>
> MB
>
> PS: there's a booklet by Emil Post on this subject of binary
> functions. Forgot the title, sorry.
>
> --
> Michel BILLAUD billaud@labri.fr
> LABRI-Université Bordeaux I tel 05 4000 6922 / 05 5684 5792
> 351, cours de la Libération http://www.labri.fr/~billaud
> 33405 Talence (FRANCE)
Article: 84314Hi, I am currenty trying to write a definition file for the board we are developing. Our FPGA (XC2V6000) is connected to a ISSI SRAM with a data width of 8 bit. The OPB External Memory Controller datasheed says I have controll over the parameter C_MEMX_WIDTH which describes the width of the x-th memorybank data bus. Unfortunately the EDK ports (in the .mhs file) my interface on a 32 bit data bus, like this: PORT Mem_DQ = 0b000000000000000000000000 & fpga_0_SRAM_256Kx8_Mem_DQ Synthesising this fails. Any idea how to tell EDK that it shall generate a 8-bit SRAM-Interface? Thank you anyway, C. LauerArticle: 84315
Hi, do you mean control_fsm (not control_asm) ? But no. When you want to add some FSRs you only have to change "control_mem_rtl.vhd" control_fsm is the controlling FSM (core-control) which controls the opcode execution process. You only have to modify this file when you want to change the behaviour of some instructions. => There are already two small bugs at the latest version provided by Oregano (CJNE Ri,# Instruction does not update Carry, RETI Intruction does not work correctly at some cases) I can send you an fixed version of control_fsm if you want.Article: 84316
On Tue, 17 May 2005 07:14:34 +0000, Phil Tomson wrote: > In article <pan.2005.05.15.11.54.37.465174@PleaseDontSpamMEpolybus.com>, > B. Joshua Rosen <bjrosen@PleaseDontSpamMEpolybus.com> wrote: >>On Sun, 15 May 2005 04:57:06 +0000, Ronald H. Nicholson Jr. wrote: >> >>> Are there any FPGA design tools which will run under Mac OS X? >>> >>> I've found that the Icarus Verilog simulator and synthesis tool >>> will run under OS X, but I'm not sure whether that's actually useful >>> for programming any current FPGA part. >>> >>> Thanks. >> >>Get yourself a Linux machine (x86 obviously, not Linux on PPC) to run your >>FPGA development environment. > > > But even doing that is no guarantee. Unfortunately, you need to be > running a very specific Linux distro in many cases (ISE 7.1 is a case in > point - I've yet to get it working acceptably well under Mandrake 10 or > Debian. I'm told that it should work better under Mandrake 10.1 - when I > get a chance I'll try it. > >> You can use the Mac as an X-Server, but >>thats as close as you are going to be able to get. It's inconceivable that >>the FPGA or CAE companies would add a third platform. > > Well Big EDA (your Mentors, Cadences, Synopsys-es :) support more than 3 > platforms already depending on the tool (Solaris, HPUX, Linux, Windows). > I would imagine that it would be a lot easier to support OSX than it would > be to support HPUX ;-) (if you've ever had to support HPUX, you know what I > mean) But in general, you're right, they won't support another platform > (OSX) unless they suddenly find a financially compelling reason to do so. > > Phil They support HPUX and Solaris for historical reasons. Until Linux became mainstream those were the primary platforms for doing serious CAE work. They will continue to support them as long as they have important customers using them, when their big customers tell them that it's OK to drop support for one of those platforms they will do it in a heart beat. It cost a lot to support a platform. It's not the development costs it's the cost of verifying that the software works on the platform and of supporting customers. From a technical standpoint anything that runs on Linux & Solaris & HPUX would be trivial to port to OSX, it's probably just a recompile. The cost is in supporting users of yet another platform. There is absolutely no compelling reason for anyone to support OSX, Linux already provides a quality *nix environment on commodity hardware, so it's not going to happen.Article: 84317
"Phil Tomson" <ptkwt@aracnet.com> wrote in message news:d6c62k2h44@enews3.newsguy.com... > In article <1116263307.387705.217740@z14g2000cwz.googlegroups.com>, > Andy Peters <Bassman59a@yahoo.com> wrote: >>Alex Gibson wrote: >>> "B. Joshua Rosen" <bjrosen@PleaseDontSpamMEpolybus.com> wrote in >>message >>> news:pan.2005.05.15.11.54.37.465174@PleaseDontSpamMEpolybus.com... >>> > >>> > Get yourself a Linux machine (x86 obviously, not Linux on PPC) to >>run your >>> > FPGA development environment. You can use the Mac as an X-Server, >>but >>> > thats as close as you are going to be able to get. It's >>inconceivable that >>> > the FPGA or CAE companies would add a third platform. >>> >>> What you mean like windows , linux and solaris ? >>> (Most current tools don't support solaris) >>> >>> Shouldn't take to much work to go from linux to OSX >>> (depending on how they implemented the port) >> >>ModelSim runs under a wish shell on Windows and Linux and Solaris, so >>it seems to me that the port would be rather painless. >> > > Yes, the port for something which has a Tk GUI (like ModelSim) would be > painless, however it would mean running QA on another platform and that > wouldn't be painless. > >>Of course, look how long it took Mentor and Xilinx to support Linux. >> >>> I'd be happy to beta test. >> >>So would I. > > Me too. > > However, when it comes to simulators there are already options available > for both Verilog (Icarus) and VHDL (GHDL) simulation on OS X. You can > simulate your design just fine on OS X, but you can't get it synthesized > and into your FPGA. > > Phil I'd be happy with commandline tools + a decent simulator. Or even having to use eclipse as the ide. AlexArticle: 84318
hi AVG....
yep .. i will be delighted if u can send me the fixed one (the one
that has the SFR expansion capabilities also). Do u need my email ID or
u can get that from this site itself?? Once again Thanx a lot..........
Article: 84319Wait a minute - don't oversimply the original design critera - 720Mbps DDR LVDS is only a part of my question. The design also needs to run the internals at 360Mhz, and that include portion of the fabric, not just DSP48, etc. Five years ago, I don't think so. Maybe in the lab somewhere, but not as an available product.Article: 84320
I will send the modified vhdl-files to Puneetsingh81@gmail.com Is this ok ?Article: 84321
Geogle wrote: > Error:cannot run process - > /path/Webpack/.xinstall/install_driver_installscript > > insmod: error inserting '/lib/modules/misc/windrvr6.o': -1 Invalid > module formatinsmod: error inserting '/lib/modules/misc/windrvr6.o': -1 > Invalid module format > > > Thanks, > George > The windrvr is used by the programming tools to access the parallel and usb ports. Without this driver, it will be impossible to program any devices. I had to patch / recompile the drivers. I used the method outlined in this article: http://www.fpga-faq.org/FAQ_Pages/0044_Xilinx_Parallel_on_Linux.htm There were some unnecessary parts, and some necessary parts that were a little foggy. Hint: don't bother with the Xilinx drivers - use the windrvr from http://www.jungo.com/ You'll also probably need to edit your /etc/rc.local to remove the two previous references to windrvr and add a /sbin/modprobe/windrvr line. JasonArticle: 84322
Hello all,
i am using the Spartan 3 (XC3s200). I have a clock signal
coming into my FPGA expansion port and all i want to do is have the
exact same clock signal going out of my FPGA, just delayed by about 3
micro seconds.I am using verilog and ISE 6.3. What is the best way to
do this ???????. Thanks !!!!!!!!!!!
Article: 84323Thats right.........Thank u.....Article: 84324
amir.inti...@gmail.com wrote: > Hello all, > i am using the Spartan 3 (XC3s200). I have a clock signal > coming into my FPGA expansion port and all i want to do is have the > exact same clock signal going out of my FPGA, just delayed by about 3 > micro seconds.I am using verilog and ISE 6.3. What is the best way to > do this ???????. Thanks !!!!!!!!!!! Do you really mean 3 microseconds? That's a *LONG* time in a Spartan3. What is your input clock frequency? Do you have another clock running at a much higher frequency? If you really mean 3 microseconds, and you have a higher frequency clock I would suggest using a shift register. If you meant 3 nanoseconds, you need to use a DCM, preferably with external feedback, and use the phase shift of the DCM to get your delay.
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