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Paying $200.00 mailto:tod.adamson@starband.netArticle: 83526
"Tod Adamson" <tod.adamson@starband.net> schrieb im Newsbeitrag news:6fb14$427614e0$943fc5b9$2419@STARBAND.NET... > Paying $200.00 > > mailto:tod.adamson@starband.net > Why do you need 6.2 ? Because the RoR team released a full key generator for it and there is no keygen for newer releases? Or is there some other reason for the 6.2 version ? AnttiArticle: 83527
I am doing some evaluation on a possible XC4VFX20 design and had a question about the Xilinx Power Calculator on the web. This design is over industrial temperature, and when I change the temperature in the calculator some of the power values don't change. For example, changing the temperature alone (from 25 to 85 degrees C) causes the VCCINT to go from 88mW to 226mW (as is expected) but VCCAUX stays at 88mW. The PowerPC cores do the same thing (no change over temp). Any experiences with the accuracy of this are appreciated, as I need to size this for power. Even though the PowerPC is a hard core it should still vary at least somewhat over temperature, correct? I assumed the same for VCCAUX as well. Any previous experience and knowledge appreciated. Thanks, Jim Davis JDDCArticle: 83528
If in the wizard it shows only 100MHz for Bus frequency when the CPU frequency is 300MHz. Do that mean I cannot increase the Bus frequency to 300MHz, in the .MHS file. The timing constraints document from Xilinx says that I can have the same CPU frequncy and the Bus frequency, as explained with the 1:1 frequency ratio "Peter Ryser" <peter.ryser@xilinx.com> schrieb im Newsbeitrag news:42717C02.7070003@xilinx.com... > The relationship between the processor core and the OCM port needs to be > an integer multiple. You cannot run the processor at 300 MHz and the OCM > at 200MHz. > > Valid combinations are 300/100 (what you have up and running), 300/150, > or 200/200. > > Don't forget to change PARAMETER C_DSCNTLVALUE to the correct value > dependent on your clock settings. > > - Peter > > > Joey wrote: > > Hi everyone !! > > > > Could anybody tell me how to change the On-Chip Memory clock frequency. I > > have the Power PC running at 300MHz and the OCM at 100MHz. What all I did to > > double the OCM frequency was that I added the CLK2X port of the Digital > > Clock Module (DCM) and connect it to the powerpc port BRAMDSOCMCLK and the > > dsocm port DSOCM_Clk. Did I do any mistake, or is it something more that I > > need to do here!! > > > > Well, I am using a Virtex II Pro device. I will add the relevant (changed) > > part of the MHS file here: > > > > BEGIN dcm_module > > PARAMETER INSTANCE = dcm_0 > > PARAMETER HW_VER = 1.00.a > > PARAMETER C_CLK0_BUF = TRUE > > PARAMETER C_CLKFX_BUF = TRUE > > PARAMETER C_CLKFX_DIVIDE = 1 > > PARAMETER C_CLKFX_MULTIPLY = 3 > > PARAMETER C_CLKIN_PERIOD = 10.000000 > > PARAMETER C_CLK_FEEDBACK = 1X > > PARAMETER C_EXT_RESET_HIGH = 1 > > PORT CLKIN = dcm_clk_s > > PORT CLK0 = sys_clk_s > > PORT CLKFX = proc_clk_s > > PORT CLKFB = sys_clk_s > > PORT RST = net_gnd > > PORT LOCKED = dcm_0_lock > > PORT CLK2X = dcm_0_CLK2X ########## WHAT I ADDED!! END > > > > BEGIN dsocm_v10 > > PARAMETER INSTANCE = docm > > PARAMETER HW_VER = 2.00.a > > PARAMETER C_DSCNTLVALUE = 0x85 > > PORT DSOCM_Clk = dcm_0_CLK2X ### WHAT I CHANGED !! Before it was sys_clk_s > > PORT sys_rst = sys_bus_reset > > END > > > > BEGIN ppc405 > > PARAMETER INSTANCE = ppc405_0 > > PARAMETER HW_VER = 2.00.c > > BUS_INTERFACE JTAGPPC = jtagppc_0_0 > > BUS_INTERFACE DSOCM = docm > > BUS_INTERFACE IPLB = plb > > BUS_INTERFACE DPLB = plb > > PORT PLBCLK = sys_clk_s > > PORT C405RSTCHIPRESETREQ = C405RSTCHIPRESETREQ > > PORT C405RSTCORERESETREQ = C405RSTCORERESETREQ > > PORT C405RSTSYSRESETREQ = C405RSTSYSRESETREQ > > PORT RSTC405RESETCHIP = RSTC405RESETCHIP > > PORT RSTC405RESETCORE = RSTC405RESETCORE > > PORT RSTC405RESETSYS = RSTC405RESETSYS > > PORT BRAMDSOCMCLK = dcm_0_CLK2X ##### WHAT I CHANGED !!Before it was > > sys_clk_s > > PORT CPMC405CLOCK = proc_clk_s > > END > > > > Somebody please help !!! > > > > Regards, > > Joe > > > > > > >Article: 83529
I am trying to perform a readback (for the first time) from ISE (impact) on my Virtex II device. For some reason that feature is not enabled (even after I enabled readback feature while programming it.) I tried finding docs which discuss this, but failed. I did find some resources on how to readback (but not from ISE). I never got a reply from Xilinx Customer service when I filed a webcase! It would be great if someone can help me. Thanks.Article: 83530
Hi Antii, Obviously my free hotmail a/c has expired again, sorry about that. What you say is true, I should have expected to be dissapointed in my search because it seemed too easy a solution to save the cost of an PCI-X IP core. Andy.Article: 83531
"design" <vasus_ss@yahoo.co.in> wrote in message news:1115024955.101343.101000@z14g2000cwz.googlegroups.com... > I am using the ASYNC fifo by Xilinx coregenerator. and that is where > the signal crosses clock domains. I cannot really apply MAXDELAY > constraints I believe. I have included BRAMS portb constraints also > from the beginning. its the same no change. > Hi Vasu, Try using the floorplanner to find out the 'real' names of the instances and/or nets you want included in your timing groups. You can also use the timing analyser to "query timegroups" to find out if you've succeeded. > one thing i did try is to remove LOWSKEWLINES and try to use clock > buffers. still no difference. Don't just try to use them. Actually use them. You can use the FPGA editor tool to confirm this. > > i am wondering that peter spoke about the FIFO in general and didnt > give any suggestions on why there are no items analyzed. and regarding > the low requirement. I have read about the low requirement before but > then the time period i am mentioning is in even number and i believe > the DCM takes care of the rest of the timing requirements because all > of the clocks used in the design are outputs of DCM. > It depends. You say you use the CLKFX outputs? So the frequency and phases of the clocks can be different. > However thank you both for the suggestions. > ...although they did a fat lot of good!! ;-) So, FWIW and for next time this type of design crops up, allow me to tell you how I try to do designs with multiple clocks. As each clock and it's associated data enter the device, I connect them to the input of a 'self addressing fifo' from XAPP291. I then make a new fast(ish) clock rate which clocks the core of the design, i.e. all the logic that processes the incoming data. This master clock clocks the output of the aforementioned SA fifo. The fifo provides an enable in the master clock domain. Likewise, as each different clock and data leave the device, another SA fifo converts from the master clock domain to the output domain. The SA fifo provides an enable to the masterclock domain. The evil clocks are limited to single pins on a BRAM, so no skew problems, everything 'inside' runs at some master clock rate, enabled at the correct rates. There's more effort up front, but it works for me >trillions of times a day! YMMV, Syms.Article: 83532
The original generalization should have read as follows: Designing an Async FIFO may prove too hard for some junior engineers. Not a blanket statement that designing one is not to be entrusted to junior engineers. That implies that "anyone" who is a junior engineer cannot design an async FIFO(and bulletproof is always implied). So I would say he is just as thick.Article: 83533
Take a look at XAPP802 (overview) and XAPP702 (memory interfaces) and XAPP700 (network interfaces) Just enter these names in the upper right hand corner search window on the Xilinx website. Here is a (not so short) description of a powerful approach: Capturing the Input Data Valid Window. Let's assume a continuously running clock and a 16-wide data input bus. Let's assume the clock is source-synchronous, i.e. its rising transition is aligned with the data transitions, and all these transitions have little skew. The user faces the problem of aligning the clock with respect to the data in such a way that set-up- and hold-time specs are obeyed and (hopefully) data is captured close to the center of the data valid window. Given the fairly wide spread between worst-case set-up- and hold-time as specified by the IC manufacturer, a carefully worst-cased design will achieve only modest performance, since the designer is forced to accomodate the specified extreme set-up and hold time values of the input capture flip-flops. Typical values are positive 300 ps set-up time, negative 100 ps hold time, which implies a 200 ps window. The actual capture window is only a small fraction of a picosecond, but, depending on temperature, supply voltage or device processing, it might be positioned anywhere inside the specified wide window. Here is a self-calibrating design approach that achieves much better performance by largely eliminating the uncertainty of the flip-flop characteristics. This approach assumes reasonable tracking of the input flip-flops driven by the data and clock inputs, and assumes programmable delay elements at each input buffer. The incoming clock is buffered and used to clock all data input flip-flops. The incoming clock is also used as if it were data, run through its own delay element X, then driving the D input of a clocked flip-flop. Its output is then used to control a state machine that manipulates X to find the two edges of the valid window, where the flip-flop output changes. Note that changing X has no impact on the bus data capture operation, it only affects the control flip-flop. Once both edges are found, the state machine calculates the center value, and applies this in common to all data input delays. This auto-calibration circuit can run continuously (or non-continuously), since it does not interfere with normal operation. It means that the user can completely ignore the flip-flop set-up and hold time specifications, the spread between set-up and hold-times, and their possible variation with temperature and Vcc. This circuit does not compensate for skew between data lines, or any skew between data and clock, and it assumes good tracking between all input flip-flops, and relies on a reasonably fine granularity in the delay adjustments. Fundamentally, this auto-calibration reduces the data capture uncertainty from a first-order problem, to a second order issue, thus permitting substantially higher data rates and/or higher reliability of operation. Virtex-4 programmable input delays have 75 picosecond granularity. A low-skew data bus can thus be captured at bus data rates in excess of 1Gbps, even when the data valid window is smaller than 200 ps. Peter Alfke 3-31-05Article: 83534
First personal opinion I don't generally like the word expert or average or what ever. The fact someone did something in the past not make him expert just as the fact if someone design dozen of chip's don't make him an Asic Guru. The only thing it does make one is have experience which a new designer should listen to but as always with a bit of skepticism as even the most experienced Eng can be wrong and even if not the newer Eng might have better idea. As for Async topic, the first step to simulate any clock domain crossing is to have FF that are not just reg which you put in always @ (posedge ... but one with timing referance. What I would suggest as first step is write something very simple with clock crossing even a simple req/ack which is done in full handshake something which is very simple, and than synthesis and place and route it. Once you have the post place and route netlist if you look on assume you use xilinx the abc_timesim.v or if you use altera it will be abc.vo you will see that the FF's are now coming from xilinx or altera library file/directories, More over there is time overwrite in the sdf file they both generate. If now you will simulate your design you will have FF that have setup and hold timing requirement to met and failing to do so will generate "x" which is what you actually want to test and simulate. Of course you can argue that this don't cover all the timing issue but only catch some of them meaning let say the setup/hold is total of 2n compare to 20n period than you might argue that not all the 2n are checked but for that I will answer that this is not important as the important thing is to hit this time frame and get the X and see that your system handle it properly. Just like when you test a counter that can count up to let say 100 you verify the 0 the 100 the freq on high and low but even if the counter is for let say 100M you are not testing it for ALL freq from 0Hz to 100MHz so 0.00000...01 Hz and than 0.000000...02 Hz and so on. Later on you can write your own FF with whatever timing you want and optimize it to what ever you want to test. The big drawback in using post place and route as you probably aware is time, those simulation run much slower compare to the code you wrote however even in very large design the relative size of the cross domain part is very small and so a good approach is have quick test of this part separately and only when happy move to simulate the complete design. This don't come to tell Spice simulation are not needed of course they do but they are needed to verify the operation and characteristic of the FF itself inside the FPGA (or the Asic for that matter) the digital designer can rely on the above and not go into the Spice modeling if he assume which is a reasonable assumption that those FF was tested by the vendor and that the timing characteristic etc are giving properly in the library files. As for the URL for the FIFO in Xilinx site, while it is very nice article with lots of color, unless I miss something it is basically useless and the reason I say it is that as I see it good article explain the theory and when it refer to "basic staff" which FIFO is one of them it should be such that a new Eng that know how to write code will be able to make the design base on this article and I believe this is not the case with this article, and regretly this is true to too many article out there. Some how I got the feeling long ago that many time Eng believe they have great design and want to tell everyone about it but on the same time are concern someone will know how they did it so the write it in a way you get some idea but not the whole solution, and for me unless we are talking on break through technology where one is going to write patent it is simple mean a very poor article which don't benefit the Eng groups, and as a whole don't even benefit the writer as if the complete detail was to be given, MAYBE someone would come with enhancement that would make the design even better. Many years back I had to design my first design that require a CRC and at that time I tried to find answer to how it work how it was done and so on. All I found was few article that talk about the idea and general abstract as how to do it but with no real implementation until after some more research I finally found one article which show exactly how it should be done, sure it was for only one bit of data but after this article I had the path and could expand it to more bit as I needed. The first articles I would probably give mark from poor to excellent but they was all what I refer as "university articles", the last one probably would get a C grade in the university but it got A from me as Eng. Finally for the first time I not only understood what and why but also the how, sure math equation are great but it might not be so straightforward to figure from them that all you really need at the end are some Xor's and FF's at least it was not clear to me at that time. Back to the Article and this tread I saw mention to the some difficult empty have but for example I didn't saw any mention as for how it is done in the URL (if I missed it do let me know where it mention as I went through it quickly) and assume there was indeed no explanation to how it was done than what does this article add to the Eng knowledge base expect few more papers. On the other hand if there is clear explanation and if this article is such that new Eng can take it and write its own Async FIFO than there is a reason and justification for this article.Article: 83535
No need to apologize the whole issue as I see it, is that if someone have question we should try to give as much answer so he can use it and not just vague detail. We are here for the fun so lets not make it a competition of who did more, as it serve nothing. If someone is very knowledgeable and give answers to all difficult question Eng in this group or any other group community etc will know he is knowledgeable and no need to go and say "I'm" or "can you do this and that" as it only bring "the bad out of us" instead of the good. And again FIFO while have its own complication is not something that should be put aside or consider as "black magic" like EMI. IF you are new designer the leader of your group will not give you huge design and if there is Async FIFO he will no doubt check your design so go ahead and try and learn so when you are the leader you know how it is done and can teach the next gen of Eng. Take a moment and think how long it will take you as someone who knows how to design Async FIFO to teach someone knew the idea and concept as well as the drawback. No need to do it for all flavor of FIFO's enough to go with one as a start. Let say it will take you a whole day (again I refer to the digital part without going into the physics of the Metastable etc) than next FIFO will be 4 hour and nextw ill be 2 hour and before you know this Eng know how to design Async FIFO and give better productivity as he is no more one more in the herd of IP copy/paste Eng's. Sure if the Async FIFO is deep enough and the freq is high enough you might have eventually to do also some hand placement and you might figure let use the vendor IP or any other reason but this should not be in my opinion the first solution when it come to BASIC block of the digital design. On the other hand if you look for let say PCI and don't want to get into understand how the PCI work than go ahead and use the IP core for PCI but PCI is not BASIC block of digital design and this is the main difference.Article: 83536
Hi, I want to write my bitstream into the eeprom of my V2 Board. In my jtag chain in impact a xcf04s gets listed. However I can do only things like erase, get device id, etc... There is an option "assing new configuration file", but I don't know where I can find one. For the FPGA it was possible to assign a *.bit file, which I have. But the eeprom only accepts mcs,exo,isc and bsd files, which I don't have. regards, BenjaminArticle: 83537
Hi, I am glad to tell you, that my LCD via LVDS works now :) However it works only up to a lvds clock rate of about 200 MHz. I am not sure yet, if the 200 MHz limit originates from the fpga or the cable. Has anybody put more than 200 MHz through a 0,4m SCSI cable? What is approximately the frequency limit of the (50 pin) scsi connector on my board? (assuming my cable is perfect) regards, BenjaminArticle: 83538
Hi, I think you guys have scared Andre away(how do you do that tick mark on top of the e?). I havn't seen him in this discussion since he first started this thread. I'm currently working on my senior design project and came accross this thread. I'm not sure what's all big hoopla is all about? I've actually have an ASYNC FIFO in my design. The design is targeted for a Spartan eval board. I've decode my EMPTY flag off the read clock and the FULL flag off the write clock using grey-code counters. Targeting a Xilinx device with clock buffers will minimize clock skew. My design seemed to be running fine. It took me about a day to come up with this design. Are there more to it than what I have done? If I had ran acrross this thread sooner, I dont think I would have tried to do the design myself. With all the expert opinions on how hard all of this is, I would have been scared to attempt it myself. Maybe my design was not done correctly. I would be happy to send my schematics to you guys for reviews. So when I graduate from school, I'm sure my title will have "junior engineer" in it. I will definitely wait until I get promoted to senior engineer before I attempt to do my first ASYNC FIFO. Seemed like my best bet is to go ahead and cut and paste from one of Xilinx already proven design. Would I have to learn VHDL now too? Does Xilinx have a schematic version?Article: 83539
Praveen, Readback of FPGAs using iMPACT is not supported - never has been :-(. You can, however, do a "verify" in which the contents of the FPGA is compared against the source bitstream file. Praveen wrote: > I am trying to perform a readback (for the first time) from ISE > (impact) on my Virtex II device. For some reason that feature is not > enabled (even after I enabled readback feature while programming it.) > > I tried finding docs which discuss this, but failed. I did find some > resources on how to readback (but not from ISE). I never got a reply > from Xilinx Customer service when I filed a webcase! > > It would be great if someone can help me. > > Thanks. >Article: 83540
Benjamin,
To program a PROM you must first convert your source bitstream to a PROM
file. You can do this using iMPACT. Use the wizard to guide you
through the process to generate a programming file and then create a
PROM file (typically MCS format). When you have that file, go back to
configuration mode and assign the MCS file to the device
Benjamin Menküc wrote:
> Hi,
>
> I want to write my bitstream into the eeprom of my V2 Board. In my jtag
> chain in impact a xcf04s gets listed. However I can do only things like
> erase, get device id, etc...
>
> There is an option "assing new configuration file", but I don't know
> where I can find one.
>
> For the FPGA it was possible to assign a *.bit file, which I have. But
> the eeprom only accepts mcs,exo,isc and bsd files, which I don't have.
>
> regards,
> Benjamin
--
*CAUTION:* Shameless self-promotion follows...
Article: 83541Hi, If you have the following code: if (count < 255) begin en_ram <= 1'b1; if (count != last_data) begin incorrect_data_count <= incorrect_data_count + 1; state <= FUNSTATE; end else begin correct_data_count <= correct_data_count + 1; state <= FUNSTATE; end count <= count + 1; end How do you force the count to only increment AFTER correct_data_count or incorrect_data_count increases? Because right now it happens simultaneously, and that's very problematic for me. Thanks, ALArticle: 83542
Hi, If you have the following code: if (count < 255) begin en_ram <= 1'b1; if (count != last_data) begin incorrect_data_count <= incorrect_data_count + 1; state <= FUNSTATE; end else begin correct_data_count <= correct_data_count + 1; state <= FUNSTATE; end count <= count + 1; end How do you force the count to only increment AFTER correct_data_count or incorrect_data_count increases? Because right now it happens simultaneously, and that's very problematic for me. Thanks, ALArticle: 83543
Hi Glenn, thank You. It works like a charm. regards, BenjaminArticle: 83544
Hi newsgroup, I have got problems using Signal Tap with the Altera USB Blaster download cable. Sometimes the data collected is correct, sometimes not, sometimes I get a jtag communication error. When I use the Altera Byteblaster MV download cable, I don't get those incorrect data nor jtag communication errors in Signal Tap and everything works fine. In Quartus timing analyzer there are no failed paths. As suggested in a newsgroup, I have set all unused pins to "inputs tristated". I use Quartus 4.2 SP1 on windows 2000 SP4. PC ist a 2,4GHz Fujitsu Siemens Amilo D. I tried a different USB cable and a different USB port. The target hardware is our own board with a EP1C12F256C8, VCCIO is 3,3V. TMS and TDI have a 10k Pullup to VCCIO, TCK has a 10k pulldown to gnd. The jtag connector is less than 2 inches away from the cyclone and this part of the schematic is from the altera nios board. It seems linke the problem has something todo with the faster timing on jtag when using the USB Blaster. Is it possible to adjust the jtag frequency? When I look at the JTAG signal "TCK" with the scope, I have the following results: 1.: Using Byteblaster MV: The signal edges reach 3,3V and are looking good. 2.: using USB Blaster: The signal edges reach 3,3V but they break down to about 2,5V. It looks like a sawtooth. I hope someone can help me in this newsgroup. It would be nice if someone could look at the TCK signal with the scope on his USB Blaster running Signal Tap. I didn't get an answer from altera mysupport within 1 week. Best regards MarkusArticle: 83545
Thanks Glenn. Why list that option when we can't use it? ;). I read in the Impact help file that it can be used when using desktop configuration mode. But, I read elsewhere (in Xilinx help file) that suggested it can be used in SMAP and JTAG config modes. Doesn't make any sense.Article: 83546
Hi Markus, > I have got problems using Signal Tap with the Altera USB Blaster > download cable. > Sometimes the data collected is correct, sometimes not, sometimes I get > a jtag communication error. Do you have a Revision A USB Blaster (with standard ribbon cable to the PCB) or a Revision B USB Blaster (with flex-pcb cable)? The Rev A cables have signal integrity problems, so in that case, contact your disti for a replacement if you such a cable. This should cost less than a new cable. Before Dec 1st, 2004 Altera would have swapped your cable for shipping cost, but now the offer has expired, unfortunately. Best regards, Ben TwijnstraArticle: 83547
Jim George wrote:
>
>> The problem with attaching RLOC to a gate, even if the gate is
>> instantiated rather than inferred, is that the mapper will not
>> necessarily keep the gate by itself in the final design. Usually
>> several gates can be lumped into a single LUT. The tools might
>> have allowed an RLOC constraint on gates that don't get grouped
>> together, but unfortunately they don't. If you have a combinatorial
>> function that needs to end up with a particular placement, the
>> only way is to instantiate a LUT instead of gates or gate primitives.
>>
>> Instantiated flip-flops don't have this problem.
>>
>
> OK... thanks. I guess Xilinx has their reasons.
You can also use the xc_map attribute (synplify, although I think XST
also added that attribute) if you put the gates into a separate entity
and put the xc_map attribute on that entity.
--FMAP'd or2
library IEEE;
use IEEE.std_logic_1164.all;
entity fmap_or2 is
port ( a, b : in std_logic;
z : out std_logic);
end fmap_or2;
architecture rtl of fmap_or2 is
attribute xc_map : STRING;
attribute xc_map of rtl : architecture is "lut";
attribute syn_hier: string;
attribute syn_hier of rtl:architecture is "hard";
begin
z <= a or b;
end rtl;
The synthesizer synthesizes to LUTs, and doing this forces the contained
logic into a LUT. You can then put an RLOC on the instantiated component.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 83548Generally if you can follow the pyramid of values and numbers it is great. You will also find recommendations power plane structure and via structures if you dig. If you have not seen it yet have a look at Xilinx application note XAPP623 on power distribution as a starting point. I would agree that reaching the numbers required is very difficult.You can get to the stage where the vias for the power capacitors effectively blocks the fanout of signals from the FPGA very significantly. You can help a bit by using capacitor arrays but even then board area of the packages and the vias is significant. We use a 0508 package containing 4 capacitors on our Broaddown2 and MINI-CAN products to help in this respect. You might be able to see them if you look at our website pictures of these products and how the capacitor layout forces the routing on the top surface tracking. I would recommend at least roughly following the pyramid of values with smaller values closest to power pins and larger values further away. We did this on the products mentioned above with groupings at corners and centre row positions of the FPGA. If your product is already double sided then you can fit capacitors underneath the FPGA to ease the routing blockage but check that your board assembler is happy to do this. Some don't like parts straight underneath BGA or will claim a cost/yield impact on your assembly. John Adair Enterpoint Ltd. - Home Of Low Cost FPGA Development Board MINI-CAN. http://www.enterpoint.co.uk "Thomas" <res0rsef@verizon.net> wrote in message news:TRTce.1736$db7.1382@trnddc01... >I am little confused with the V2P decoupling guidelines. I am using a >V2p7-ff896 part. It has 32 VCCINT pins and the the XST 7.1 suggest using a >power rail scheme: > .001uf - 34% > .01uf - 31% > .04uf - 18% > .47uf - 9% > 4.7uf - 3 % > 470uf - 3% > > The user guide and the Xilinx ml320 reference design use a .1uf for each > pin and a bulk cap near the regulator. Similar with VCCAUX and VCCO. Which > is the best way to follow? > > Thanks for any help. >Article: 83549
Markus Knauss schrieb: > Hi newsgroup, > > I have got problems using Signal Tap with the Altera USB Blaster > download cable. > Sometimes the data collected is correct, sometimes not, sometimes I get > a jtag communication error. > > When I use the Altera Byteblaster MV download cable, I don't get those > incorrect data nor jtag communication errors in Signal Tap and > everything works fine. > > In Quartus timing analyzer there are no failed paths. > > As suggested in a newsgroup, I have set all unused pins to "inputs > tristated". > > I use Quartus 4.2 SP1 on windows 2000 SP4. > PC ist a 2,4GHz Fujitsu Siemens Amilo D. > I tried a different USB cable and a different USB port. > > The target hardware is our own board with a EP1C12F256C8, VCCIO is 3,3V. > TMS and TDI have a 10k Pullup to VCCIO, TCK has a 10k pulldown to gnd. > The jtag connector is less than 2 inches away from the cyclone and this > part of the schematic is from the altera nios board. > > It seems linke the problem has something todo with the faster timing on > jtag when using the USB Blaster. Is it possible to adjust the jtag > frequency? > > When I look at the JTAG signal "TCK" with the scope, I have the > following results: > > 1.: Using Byteblaster MV: The signal edges reach 3,3V and are looking good. > > 2.: using USB Blaster: The signal edges reach 3,3V but they break down > to about 2,5V. It looks like a sawtooth. > > I hope someone can help me in this newsgroup. It would be nice if > someone could look at the TCK signal with the scope on his USB Blaster > running Signal Tap. > > I didn't get an answer from altera mysupport within 1 week. > > Best regards Markus Hi Markus, I use 1k pullup ,pulldown. I had some problems with 10k pulldown on TCK. The following is from "ALTERA Support Find Answers": .. Problem Are there any known errors in the Stratix and Cyclone Configuration chapters with reference to the external pull-down resistor value recommended for the JTAG TCK signal? Solution Yes. The JTAG TCK pull-down resistor value is incorrectly specified as 10k-ohms in the Stratix and Cyclone Configuration chapters. The correct external pull-down resistor value is 1k-ohm. This stronger resistor ensures that the TCK signal is biased at a logic low level despite the weak internal pull-up on this pin. The internal pull-up ranges from 20k-ohms to 40k-ohms across process, voltage and temperature. Future versions of the Stratix and Cyclone Handbooks will be updated accordingly. ...
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