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I would definitely put some protection diodes on the lines. Multiple years ago, a company I worked at had problems with video RamDacs blowing out randomly. We finally realized it only happened when we plugged a monitor into the card. There would somtimes be enough voltage on the lines that the parts were zapped even though voltage levels were fine after things had been plugged together. John PArticle: 83476
Thanks to you all for some excellent advice. I now know exactly what I'm doing!! Rog. "johnp" <johnp3+nospam@probo.com> wrote in message news:1114894992.585043.40310@o13g2000cwo.googlegroups.com... >I would definitely put some protection diodes on the lines. Multiple > years ago, a company I worked at had problems with video RamDacs > blowing out randomly. We finally realized it only happened when we > plugged > a monitor into the card. There would somtimes be enough voltage on > the lines that the parts were zapped even though voltage levels were > fine > after things had been plugged together. > > John P >Article: 83477
That just means if he didn't work for fairchild back then it would have been Bob Smith that put the first FIFO to IC. That line convinces you he was the first person to invent a FIFO? > "In 1970, Alfke invented the first FIFO integrated circuit, the Fairchild > 3341"Article: 83478
There are no USB specs on the distance between a PHY and its controller. You need to meet the specs of the PHY manufacturer. There are specs that relate to the traces from the PHY to the USB connector. Marc Reinig UCO, Lick Observatory Laboratory for Adaptive Optics "praveen" <praveenkumar1979@rediffmail.com> wrote in message news:ff8a3afb.0503080548.22206a27@posting.google.com... > Hello guys, > I wanted to know far i can keep by USB PHY from USB core (inside the > fpga)　so that i am within the USB standard????　how do i > calculate the maximum trace length from fpga to Usb PHY. > > Thanks in advance > Regards > PraveenArticle: 83479
Hi Mike,
Mike Treseler wrote:
> "if then else elsif elsif ... "
> only implies priority if cases overlap.
if A(7) = '1' then Q <= "111";
elsif A(6) = '1' then Q <= "110";
etc...
do overlap, but even then, it does not necessarily
require or imply a priority-based implementation.
> I agree that std_ulogic_vector is usually
> more trouble than it's worth.
> However std_ulogic has no such downside.
> I use std_ulogic as my default bit type.
> It port maps directly to std_logic without conversion.
Seems I was a bit too quick to burry std_ulogic...
I still won't use it, nor RTL procedures, but this is more
a matter of habits and personal taste. I once suspected that
you were using both as a hidden signature to copyright your code
;-)
Cheers,
Bert Cuzeau
Article: 83480Bryan wrote: > That just means if he didn't work for fairchild back then it would have > been Bob Smith that put the first FIFO to IC. That line convinces you > he was the first person to invent a FIFO? > > >>"In 1970, Alfke invented the first FIFO integrated circuit, the > > Fairchild > >>3341" Nowhere did I claim that he was the first person to invent a FIFO. There appear to have been some discrete implementations as discussed a few years ago on this newsgroup. Fortunately during that discussion, people regarded accomplishment and years of expertise as worth something. You appear to claim that "anyone" can design a bulletproof asynchronous FIFO and that anyone who believes that the discipline is difficult is trying to pull the wool over other engineers' eyes to make themselves look "holier than though." Well, though art thick. Accomplished. Published. Insightful. Helpful. What are you?Article: 83481
I am little confused with the V2P decoupling guidelines. I am using a V2p7-ff896 part. It has 32 VCCINT pins and the the XST 7.1 suggest using a power rail scheme: .001uf - 34% .01uf - 31% .04uf - 18% .47uf - 9% 4.7uf - 3 % 470uf - 3% The user guide and the Xilinx ml320 reference design use a .1uf for each pin and a bulk cap near the regulator. Similar with VCCAUX and VCCO. Which is the best way to follow? Thanks for any help.Article: 83482
LENNART KIRKEVIK wrote: > I have a flex10k10lc84-4 and have just bulit a test circuit for it. I am > using the MAX+plusII software. I made a simple AND port and compiled and > programmed it with a byteblaster II cable. I got no error messages, just the > "configuration complete". When testing, the output was low regardless of the > state of the inputs. The flex 10k10 seems to be dead except when programming > it. > > Does someone have an idea ? > > Lennart Kirkevik Forgot : Check you JTag + programming + special inputs pins : you must use pullups or pulldowns, carefully follow the documentation.Article: 83483
Brian, you are really getting obnoxious when you write about something you do not understand. Yes, the FIFO-IC was my original idea, and I cajoled Fairchild management for a whole year to let me design it, because I thought it would become a good product, but Marketing had a hard time understanding. The 3341 became very successful, and later was second-sourced by AMD. And there had never been an integrated FIFO before it. It may be difficult for you to understand, but many products can still be born out of one person's idea, conviction, and drive. And one person can make a difference. I hope you also will do some time... Peter AlfkeArticle: 83484
"Thomas" <res0rsef@verizon.net> wrote in message news:TRTce.1736$db7.1382@trnddc01... >I am little confused with the V2P decoupling guidelines. I am using a >V2p7-ff896 part. It has 32 VCCINT pins and the the XST 7.1 suggest using a >power rail scheme: > .001uf - 34% > .01uf - 31% > .04uf - 18% > .47uf - 9% > 4.7uf - 3 % > 470uf - 3% > God, this old chestnut again! So, in the old days, people used different values of capacitor in a decoupling scheme because they came in different types (ceramic, Al electrolytics etc.)and packages and so a combination provided a low impedance across a wide range of frequencies. For some reason, there are still people who think that it's a good idea to have a range of values, even though all the caps are the same size and type. Including, by the looks of it, the person who wrote the above recommendation. It's total nonsense. Some of these guys claim that using a range of caps is good because of the spread of self resonant frequencies. Bless them, they don't seem to understand that in the real world the caps are soldered onto a board and so the SRF effect is completely changed by the layout, the connections to the device etc. I use a lot of 0402 1uF X5R caps. I use a fair number of 0805 22uF X5R caps. Try reading this http://www.sigcon.com/Pubs/news/1_17.htm And this tool will calculate impedances for you. http://www.murata.com/designlib/mcsil.html > The user guide and the Xilinx ml320 reference design use a .1uf for each > pin and a bulk cap near the regulator. Similar with VCCAUX and VCCO. Which > is the best way to follow? > This is the way to go. The ML320 designers knew what they were doing. Have fun, Syms.Article: 83485
Hi Bert,
info_ wrote:
> if A(7) = '1' then Q <= "111";
> elsif A(6) = '1' then Q <= "110";
> etc...
> do overlap, but even then, it does not necessarily
> require or imply a priority-based implementation.
I agree. Synthesis is free to make
any netlist that sims like the code.
I have found that coding style has a
negligible effect on utilization
for equivalent descriptions.
My point was that the logical idea
of priority does not apply to all
problems. Some are pieces of pie
and some are Olympic rings.
> I still won't use it, nor RTL procedures, but this is more
> a matter of habits and personal taste. I once suspected that
> you were using both as a hidden signature to copyright your code
> ;-)
Yes. It's a little like changing the
spelling of my name on magazine
subscriptions to see where it goes.
> Cheers
Hey howdy,
-- Mike Treseler
Article: 83486Just trying to figure out what the rough price of V4 FX12/FF668 part is... AVNet and NuHorizons aren't showing any prices or stock atm, and digikey don't do anything even vaguely recent :-( Anyone bought any (quantity 1-10) recently and want to give me a ball-park figure ? Cheers, Simon.Article: 83487
"Simon" <news@gornall.net> schrieb im Newsbeitrag news:I4OdnQ3Pm-Iy6enfRVn-rw@comcast.com... > > Just trying to figure out what the rough price of V4 FX12/FF668 part > is... AVNet and NuHorizons aren't showing any prices or stock atm, and > digikey don't do anything even vaguely recent :-( > > Anyone bought any (quantity 1-10) recently and want to give me a > ball-park figure ? > > Cheers, > Simon. the ball-park figure is $100 if you get a very very very good deal, if not then multiply by the tambov's constant* to get your price. Antti *tambov's constant: a constant multiplier that when applied always gives the correct result for any equation.Article: 83488
Hi Everyone. I am using XCF16 PROM in our boards. Those chips are Eng. Samples . from some reason in some boards we can detect all the JTAG chain and load configure the FPGA sucssefuly. But on the other boards IMPACT detects only the FPGA in the JTAG chain, I try to reduce the TCK frequency but it doesn't seem to do any good. note that i have the latest software updates. any idea? Thanks. HarelArticle: 83489
Hi everyone I had a question earlier regarding some timing-issues, but I came to the question how the optional delay element with an input flip-flop was able to help me? What I don't understand is - how the extra delay can help me? Even more delay causes bad timing? But combining this with an input flip flop should help? I only see this input flip flop helps me, if it's controlled by another clock? I tried searching Xilinx and google around but nothing but the same texts appears in several explanations other than it simply helps? And still - why is a delay good when having the flip-flop? I think that the 1ns (Spartan 3) non-obtional delay is before the input flip-flop and not after it - or am I wrong about that? Can somebody please explain how this input-path really works and not just that it helps - cause I cannot personally accept that it helps if I don't know why? Thanks, PrebenArticle: 83490
After extensive Googling I'm unable to find a PCI-X target chip with a simple backend interface that would act as cost effective glue logic between a FPGA (Xilinx) and a PCI-X local bus. Surely there is a requirement for such a ASSP device in the market place, given the alternative is to purchase a PCI-X IP target core, typically costing over $10,000. I'm aware that PLX Technology offer such a device, but alas only for PCI. Does anybody know of a vendor? Thanks, Andy.Article: 83491
I am looking for the cheapest PowerPC G4 PCI coprocessor board for the PC. All boards I have found are for military/medical applications and they sell for very inflated prices compared to a Mac Mini. When a Mac Mini can sell for 500 USD, shouldn't it be possible to have a PCI card with a 1 GHz G4 available for 300 USD? Volume and R&D cost is the issue here of course.. Anyonecould point me to the cheapest G4 PowerPC board(s) available? (1000 USD would be my limit). Thanks, Frank de GrootArticle: 83492
Hi all, Would appreciate a lot if i could get some help on this. Got a couple of questions and have read a lot of those messages on this group on cross clock domain design. Infact I have changed my design to include asynchronous fifo in my design. Now data crossing happens only by the fifo. But first the clocks. There are three clocks. And the three clocks are getting generated from three DCMs using CLKFX outputs. with the same input clock to three of them Presently my design works but not always. Sometimes there is the wrong output when i reset the design. i dont think this is the problem of the reset. Also the design is stable at lower frequencies. The things I have done and experimented are 1.)used LOWSKEWLINES constraint on all the clocks and reset.(my design started working only after this.)oh yeah as well i am using 92% of the slices that is after i included the FIFO. this is ok. 2.)have mentioned the period constraint for the input clock to the DCM as well as the PERIOD constraints on the output clocks of the DCM. 3.) included the BRAMS_PORTA constraint for the FIFO. and then associated the clock nets for each of the ports of the FIFO. i think this is how to do it. but in this none of the nets nor instances are included and analyzed. here is the output of the timing analyzer Timing constraint: TS_groupa1 = PERIOD TIMEGRP "clk_fpga" 18.182 nS HIGH 50.000000 % ; 0 items analyzed, 0 timing errors detected. 4.) I think the only timing problem affecting my design is the cross clock domain in the FIFO itself. Slack: -11.613ns (requirement - (data path - clock path skew + uncertainty)) Source: receiver/buffercatch/fifo/BU545 (FF) Destination: receiver/buffercatch/fifo/BU216 (FF) Requirement: 0.001ns Data Path Delay: 6.132ns (Levels of Logic = 5) Clock Path Skew: -5.482ns Source Clock: clk_fpga rising at 478487.558ns Destination Clock: clk_datain rising at 478487.559ns Clock Uncertainty: 0.000ns I am not sure on how to constrain this. The from to constrain and the multicycle constraint will not work with my design because the clocks are not related and there is not a definite time period after which the other clock appears. the clocks are 55,34and 40MHZ. If anyone feels this problem has been addressed before in a tech document like the xilinx app or anything please let me know the same. Thank you cheers vasuArticle: 83493
Antti Lukats wrote:
> "Simon" <news@gornall.net> schrieb im Newsbeitrag
> news:I4OdnQ3Pm-Iy6enfRVn-rw@comcast.com...
> >
> > Just trying to figure out what the rough price of V4 FX12/FF668
part
> > is... AVNet and NuHorizons aren't showing any prices or stock atm,
and
> > digikey don't do anything even vaguely recent :-(
> >
> > Anyone bought any (quantity 1-10) recently and want to give me a
> > ball-park figure ?
> >
> > Cheers,
> > Simon.
>
> the ball-park figure is $100 if you get a very very very good deal,
if not
> then multiply by the tambov's constant* to get your price.
>
> Antti
>
> *tambov's constant: a constant multiplier that when applied always
gives the
> correct result for any equation.
Pretty funny, Annti! And true. I've found in the correct volume,
nearly everything is about $100 (except the stuff that is already under
$100 :-).
But to directly answer the OP's question:
http://groups-beta.google.com/groups?hl=en&q=XC4VFX12
Marc
Article: 83494Hello Somehow I am not able to find in any Xilinx documentation a detail description of the FSL interface. I am especially looking for the read and write timing diagrams. Anyone knows where I can find them? Cheers PhilippArticle: 83495
Hi,Philipp If you have the EDK,you could find the datasheet of FSL and MicroBlaze in it.Actually,there are all datasheets of the IP cores which are offered by EDK. bugjayArticle: 83496
I've heard a few painful stories about implementing Xilinx Virtex4 designs (bad SDF, bad bitfiles, power supply requirements, etc...) Are the parts and tool flows really ready for production designs with the V4? Should I bet the farm on getting a V4 design into production by July? Our vendor promises industrial-temp parts by June. We're merging 3 mid-size V2Pro chips into one V4. The only tricky part is our 12-bit DDR deserializers on the front end: 5 interfaces at 360 MHz (times four 720 Mbps data streams on each interface). How accurate/reliable is the back-annotated SDF out of ISE (v7.1.01i)? How accurate/reliable are the timing reports from trce? If trce generates the SDF, they should correlate well, but do they? Is either one really trustworthy for analyzing/debugging? (I'm still trying to understand some of what I'm seeing on the V2Pro designs.) If I use the timing prorate options (max voltage, coldest temperature) in an attempt to anaylze min timing, are the trce reports and SDF output realistic? With fast DDR inputs, hold times are important too. The additional IOB delay element (~1.1ns if enabled?) also adds uncertainty to the setup/hold requirements, making for tighter data valid window requirements, and appears to do more harm than good in this case. OTHER TOOLS: Does anyone have specific comments regarding Synplicity (Synplify Pro) or Synopsys (DC-FPGA and PrimeTime) on a Virtex4 design? Thanks very, very much for your help. mjArticle: 83497
Preben. the extra delay is there to avoid a hold-tme requirement on the input data. Here is how: When you use a global clock to clock in the data, that clock has to be able to drive thousands of destinations. That means a "significant" clock delay, more than the data delay to the input flip-flop. Whenever the clock delay is longer than the data delay, there is a hold-time requirement: Assume a perfect flip-flop with zeo set-up time. The data must then be held valid for some time after the clock. This is ugly, since the data source sees no reason to keep the old data valid after the new clock. Increasing the data delay to make it match the clock delay reduces the hold-time requirement, hopefully to zero or a negative value. The extra delay increases the set-up time, and thus reduces the max clock rate a little. But it avoids failure when the data source isvery fast. "Better to sacrifice some top speed, but avoid unreliable operation at all (even slow) clock rates". Peter Alfke, Xilinx Applications (from home)Article: 83498
I should have said: The data must then be held valid for some time after the INCOMING EDGE ON THE clock PIN. Just to avoid confusion. PeterArticle: 83499
Symon, Thanks for your help. The murata capacitor selection tool is of great help. Thomas "Symon" <symon_brewer@hotmail.com> wrote in message news:42741a73_1@x-privat.org... > "Thomas" <res0rsef@verizon.net> wrote in message > news:TRTce.1736$db7.1382@trnddc01... >>I am little confused with the V2P decoupling guidelines. I am using a >>V2p7-ff896 part. It has 32 VCCINT pins and the the XST 7.1 suggest using a >>power rail scheme: >> .001uf - 34% >> .01uf - 31% >> .04uf - 18% >> .47uf - 9% >> 4.7uf - 3 % >> 470uf - 3% >> > God, this old chestnut again! So, in the old days, people used different > values of capacitor in a decoupling scheme because they came in different > types (ceramic, Al electrolytics etc.)and packages and so a combination > provided a low impedance across a wide range of frequencies. > For some reason, there are still people who think that it's a good idea to > have a range of values, even though all the caps are the same size and > type. Including, by the looks of it, the person who wrote the above > recommendation. It's total nonsense. Some of these guys claim that using a > range of caps is good because of the spread of self resonant frequencies. > Bless them, they don't seem to understand that in the real world the caps > are soldered onto a board and so the SRF effect is completely changed by > the layout, the connections to the device etc. > I use a lot of 0402 1uF X5R caps. I use a fair number of 0805 22uF X5R > caps. > Try reading this http://www.sigcon.com/Pubs/news/1_17.htm > And this tool will calculate impedances for you. > http://www.murata.com/designlib/mcsil.html > >> The user guide and the Xilinx ml320 reference design use a .1uf for each >> pin and a bulk cap near the regulator. Similar with VCCAUX and VCCO. >> Which is the best way to follow? >> > This is the way to go. The ML320 designers knew what they were doing. > > Have fun, Syms. >
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Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z