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HB schrieb:
> Hi,
>
> Do you have experience with nios2 and a specific terminal (hyperterminal,
> tera pro, or others) ?.
> I have problem to only have an easy printf message !!....
>
> I 'm using Stratix(10) Altera Develop KIT with UART "console" DB9.
> I'm using example 'standart' (this example have an uart)
> In the Nios software I'm using example 'hello_word".
>
> jtag_uart is OK, I receive this message 'hello_word' in the NIOS IDE
> console.
>
> How could I obtain this result with "uart" and a terminal.
> How can I do choices ('jtag_uart' and/or 'uart') to write this message ('IDE
> console' and/or 'terminal') ?.
> (for example options in properties of system library => std_out, std_err,
> std_in)
>
> When I'm trying this example with UART, I have two result :
>
> => if I don't connect first the COM of the terminal:
> nios2-terminal: connected to hardware target using UART on
> /dev/com1 at 115200 baud
> nios2-terminal: (Use the IDE stop button or Ctrl-C to terminate)
> => if I connect first the COM of the terminal :
> nios2-terminal: can't open uart: Permission denied
> (So I'm using COM2 as terminal, and I connect the cable to this COM2, and I
> configure the properties of system library as COM1. )
>
> (no hardware problem with RS232 cāble, loopback test is OK with pin 2 and 3
> of DB9).
>
> Regards,
>
> H.
>
>
check also niosforum.com
normal printf goes to stdout, this depends on the settings
in system library properties (stdout).
if a special device should be used then use
fopen("device_name") and fprintf(filepointer,...)
in your debug settings ( use Run-> debug... ) tab "Target connection",
"NiosII Terminal Communication device" and set it to the device the
integrated terminal should use.
e.g. set it to none if you want to use hyperterminal.
Article: 86101Hi Adam, Adam Megacz wrote: > If there is sufficient support, I will RFD the matter over on > news.announce.newgroups and reference this thread as justification. > The call for votes will be crossposted here. I say "nay" c.a.fpga is sufficiently low volume, and high SNR that this isn't really justified, for the inevitable dilution that it would create. Most of the problems you suggest as reasons for a change are better handled by a decent newsreader client that can ignore threads. The <mfr> split is unnecessary - threads are usually quickly identified either from the subject or the first post, and same for soft-CPU threads. comp.arch.fpga.cpu would not stop e.g. C programming questions in c.a.fpga anyway... - in the same way that comp.lang.vhdl still gets FPGA synthesis questions and so on. c.a.fpga is the best technical newsgroup I know - the SNR is remarkable, even with the occasional inter-vendor marketing war. Don't try to fix what's not broken. Regards, JohnArticle: 86102
Yes, keep us together. Where else could we ventilate our sibling rivalry? No audience, how boring! But I do think we should make it more entertaining and informative, less argumentative and poisonous. Peter Alfke, you-know-whith-whomArticle: 86103
Hi Philip, > So when you look at a legacy CPUs, you are looking at a design that > has been crafted to take advantage of the medium it was designed to > be implemented in. Hum. Some, perhaps...but "crafted" and 8088/8086 in the same paragraph, much less sentence one doesn't see much. There is such a thing as simply a bad and/or poorly implemented architecture. > ...8088 mode, > with silly 1 MB address space, and those inane segment registers. May be not so "crafted" after all, eh? Parlez-vous 68k? ;-) Regards, AustinArticle: 86104
Hi Rick, > Hmm..actually t80 performance degraded continiously > in Altera Quartus since version 4.1 with same > standard settings (and no automatic RAM block placing). > Same is true for other similar CPU cores as well... We do not observe this degradation. Which family are you compiling to, are you using (tight) timing constraints, and do you have any data you can post? Regards, PaulArticle: 86105
Came across this http://www.terasic.com/english/fpga_01.htm Just wondering if anyone has one or has tried one? Designed for multimedia. EP1C6Q248C8 vga , tvout , audio out(line out) , ps2 , rs232 , usb programming cf card , config prom , 16 bit audio , 1MB flash + 8MB ram. Looks quite good for US$149 AlexArticle: 86106
Alex Gibson wrote: > Came across this > http://www.terasic.com/english/fpga_01.htm > > Just wondering if anyone has one or has tried one? > > Designed for multimedia. EP1C6Q248C8 > vga , tvout , audio out(line out) , ps2 , rs232 , usb programming > cf card , config prom , 16 bit audio , 1MB flash + 8MB ram. > Looks quite good for US$149 I dare say. Run through the getting started manual and it doesn't seem to shabby. On page 46 they even remind you to take a rest :-) Too bad it's such a tiny FPGA and so little memory. TommyArticle: 86107
yaseenzaidi@NETZERO.com wrote: > Greetings, > > I have a situation where Post Translate timing is significantly > different from behavioral/RTL simulation. I am not not speaking of > simple delays, the outputs/data are different than what they should be. > > > What is interesting is that the design works on the FPGA board. > I implemented a serial port in loopback mode in Xilinx, if I type a > character on Hyperterm I get the same returned from the FPGA. > > I have set timing constraints but to no effect. > > YZ > In a real design where correctness matters, I wouldn't discard this discrepancy without taking a closer look... It could mean that your design does't work at worst case timing, or it could hide some unwelcome asynchronous feature or incorrect clock domain crossing etc... A couple of characters through Hyperterminal is not a good "proof" of design correctness. If you use Quartus, you could take a look at the Design Assistant's report, or investigate the problem a bit further. A potential error might create havoc much later. Bert CuzeauArticle: 86108
"Jedi" <me@aol.com> schrieb im Newsbeitrag news:cT_te.335$N23.291@read3.inet.fi... > Jedi wrote: > > hello > > > > > > Is there any example of how to add JTAG port support into > > own non-SOPC builder design like I can directly access > > SPI config port? > > > > For example I want to read/set own register word from > > an own JTAG tool. > > > > Okay..getting some own defined bitstream out of JTAG port > when assigning something to "tdouser"... > > But still unclear now what those JTAG IR exactly do: > > 0000001100 > 0000001101 > 0000001110 > > Any more documentation about this? > Or is this some high-security risk NDA stuff? > > thx > rick > the documentation is almost non existant, I documented some useage of the altera bscan with some examples should be somewhere in http://gforge.openchip.org I was thinking that ony C (..001100) is the USER functions but hm you say D , E are as well ? no information about the D, E instructions, the quartus memory programmer uses C instruction that where I found it by doing trace on JTAG anttiArticle: 86109
Hello, A customer of ours is using one of our IPs and reports that DC (for synthesis) complains about two things : *A* wouldn't support 'pos as in character'pos ?? (which is very handy for cahacter to slv conversion) *B* wouldn't support booleans in generic ?? I emailed the Synopsys hotline, but got the answer that only Synopsys customers can ask such questions... A pointer to a document stating the current limitations of DC would be very appreciated :-) Thx in advance, Bert CuzeauArticle: 86110
"Jedi" <me@aol.com> schrieb im Newsbeitrag news:cT_te.335$N23.291@read3.inet.fi... > Jedi wrote: > > hello > > > > > > Is there any example of how to add JTAG port support into > > own non-SOPC builder design like I can directly access > > SPI config port? > > > > For example I want to read/set own register word from > > an own JTAG tool. > > > > Okay..getting some own defined bitstream out of JTAG port > when assigning something to "tdouser"... > > But still unclear now what those JTAG IR exactly do: > > 0000001100 > 0000001101 > 0000001110 > > Any more documentation about this? > Or is this some high-security risk NDA stuff? > > thx > rick > http://wiki.openchip.org/index.php/Altera:JTAG uups I used 1110 0x0E instruction not 0x0D as I previously posted AnttiArticle: 86111
Hi all! I'm starting a PhD project in the field of design of SoC systems on FPGA. I would like to buy an FPGA board with the following features: -Sufficient FPGA for small to middle SoCs (OpenCores based cores: OR1200+Sound+LCD/VGA+USB+UART+Custom cores) -Sufficient input/output units (USB/PS2/VGA/LCD). -Ressources for testing. for minimizing the use of lab equipments => this card will be for use at home. -Sufficient Flash+RAM. All the variants are welcome. Another requirement ... I will have to work with the jbits system (for partial reconfiguration) ... are there any requirements for FPGA boards ?? Thanks !Article: 86112
I forgot to say that I'm interested by Virtex/VirtexII based boards.Article: 86113
"GaLaKtIkUsT" <taileb.mehdi@gmail.com> wrote in message news:1119422261.960138.174990@g43g2000cwa.googlegroups.com... > Hi all! > I'm starting a PhD project in the field of design of SoC systems on > FPGA. > I would like to buy an FPGA board with the following features: > -Sufficient FPGA for small to middle SoCs (OpenCores based cores: > OR1200+Sound+LCD/VGA+USB+UART+Custom cores) > -Sufficient input/output units (USB/PS2/VGA/LCD). > -Ressources for testing. for minimizing the use of lab equipments => > this card will be for use at home. > -Sufficient Flash+RAM. > > All the variants are welcome. > > Another requirement ... I will have to work with the jbits system (for > partial reconfiguration) ... are there any requirements for FPGA boards > ?? > > Thanks ! > http://www.digilentinc.com/info/XUPV2P.cfm virtex2pro takes cf cards and uses standard computer ddr ram http://www.xilinx.com/univ/xupv2p.html board can output xsga(1600 by 1200) , ethernet , sata , audio (ac97), etc has a usb2 port for programming Should also take a look at http://www.xilinx.com/univ/overview.html Our xupv2pro board finally got ordered today(hopefully). Looking forward to getting to use it. Can run linux or uclinux on the board. For uclinux http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux AlexArticle: 86114
I'll work on OpenRisc based systems ... the VII pro is not adequate.Article: 86115
I'll work on OpenRisc based systems ... the VII pro is not adequate. Thanks !Article: 86116
Antti Lukats wrote: > "Jedi" <me@aol.com> schrieb im Newsbeitrag > news:cT_te.335$N23.291@read3.inet.fi... > >>Jedi wrote: >> >>>hello >>> >>> >>>Is there any example of how to add JTAG port support into >>>own non-SOPC builder design like I can directly access >>>SPI config port? >>> >>>For example I want to read/set own register word from >>>an own JTAG tool. >>> >> >>Okay..getting some own defined bitstream out of JTAG port >>when assigning something to "tdouser"... >> >>But still unclear now what those JTAG IR exactly do: >> >>0000001100 >>0000001101 >>0000001110 >> >>Any more documentation about this? >>Or is this some high-security risk NDA stuff? >> >>thx >>rick >> > > http://wiki.openchip.org/index.php/Altera:JTAG > > uups I used 1110 0x0E instruction not 0x0D as I previously posted > Correction (o; instruction 0000001101 is CONFIG_IO as documented in BSD file... Used 0000001100 last night for shifting out own shift register content successfully... As the TCK/TMS/TDI signals are also available in the module... probably this would mean I could also use unused IR codes with own TAP controller? Now have to wait for EBV Finland returning my other NIOS board for signal capturing (o; greets rickArticle: 86117
Jedi wrote: > Antti Lukats wrote: > >> "Jedi" <me@aol.com> schrieb im Newsbeitrag >> news:cT_te.335$N23.291@read3.inet.fi... >> >>> Jedi wrote: >>> >>>> hello >>>> >>>> >>>> Is there any example of how to add JTAG port support into >>>> own non-SOPC builder design like I can directly access >>>> SPI config port? >>>> >>>> For example I want to read/set own register word from >>>> an own JTAG tool. >>>> >>> >>> Okay..getting some own defined bitstream out of JTAG port >>> when assigning something to "tdouser"... >>> >>> But still unclear now what those JTAG IR exactly do: >>> >>> 0000001100 >>> 0000001101 >>> 0000001110 >>> >>> Any more documentation about this? >>> Or is this some high-security risk NDA stuff? >>> >>> thx >>> rick >>> >> >> http://wiki.openchip.org/index.php/Altera:JTAG >> >> uups I used 1110 0x0E instruction not 0x0D as I previously posted >> > > Correction (o; > > instruction 0000001101 is CONFIG_IO as documented in BSD file... > > Used 0000001100 last night for shifting out own shift register content > successfully... > > As the TCK/TMS/TDI signals are also available in the module... > probably this would mean I could also use unused IR codes with > own TAP controller? > > > Now have to wait for EBV Finland returning my other NIOS board > for signal capturing (o; > One strange thing...jtag discovery tool reports DR chain length of "7" for IR 0x00E: Detecting DR length for IR 0000001110 ... 7 For 0x00C and 0x00D it shows normal "has to be defined" behaviour: Detecting DR length for IR 0000001100 ... -1 Detecting DR length for IR 0000001101 ... -1 rickArticle: 86118
"GaLaKtIkUsT" <taileb.mehdi@gmail.com> wrote in message news:1119424549.144806.286650@g44g2000cwa.googlegroups.com... > I'll work on OpenRisc based systems ... the VII pro is not adequate. > Thanks ! > Well, have you had a search for boards on <http://www.xilinx.com/xlnx/xebiz/search/boardsrch.jsp?sGlobalNavPick=null&sSecondaryNavPick=null&category=&iLanguageID=1&ProgramType=XilinxOnBoard> ? Maybe look at http://www.xilinx.com/products/tables/fpga.htm http://www.xilinx.com/products/tables/virtex4.htm work out minimum size fpga you need and look for a board with that. Not going to be cheap. AlexArticle: 86119
Hello,
I made an Entity with an Process using Xilinx 7.1 .
Then made:
GEN_A : GenInt
port Map (
clk_prg_i => clk_prg_i ,
res_i => res,
high_o => high_Gen,
low_o => low_Gen);
In UCF-File:
inst "GEN_A" AREA_GROUP=Group_A;
AREA_GROUP "Group_A" RANGE=SLICE_X3Y1:SLICE_X33Y33;
and became the following error:
NgdBuild:753 - Line 41 in 'LFSR_CS_Test.ucf': Could not find instance(s)
GEN_A' in the design. To suppress this error specify the correct instance
name or remove the constraint.
I need Help with this Error.
Thanks
Peer
Article: 86120
> I don't think
> that FPGA would ever be the right choice for this type of volume
> applications. If I plan to sell one million of units, I don't care much if
> I have to spend one million dollars for ASIC setup, if then one chip will
> cost one dollar (ASIC) instead of ten (FPGA).
Look at the trend in the cost of ASIC setup. Compare that with
the trend in FPGA gates-per-dollar. Look five years ahead. Now
consider a choice between ASIC setup of $2M and an FPGA
costing $3. Which would you choose? Once you've had to do a
couple of re-spins because your design wasn't quite right first time,
your FPGA is looking very cheap. And that's before you factor in
the time-to-market advantage.
Making chips is really hard, and is getting harder. More and more
companies are realizing that it makes good business sense to let
somone else take the hit on sub-micron design, qualification and
testing. This leaves their engineers more time for inventing things
that actually add value.
Me? I think FPGAs will kill cell-based ASIC within ten years.
How's that for optimism? :-)
-Ben-
Article: 86121Al Clark wrote: > > All Altera really needed to do was discuss the Vih threshold issue in the > first place. > I think Altera's part in this issue is to tell you about the device, and not to educate you ! Karl.Article: 86122
"Jedi" <me@aol.com> schrieb im Newsbeitrag news:xn8ue.45$K76.41@read3.inet.fi... > Jedi wrote: > > Antti Lukats wrote: > > > >> "Jedi" <me@aol.com> schrieb im Newsbeitrag > >> news:cT_te.335$N23.291@read3.inet.fi... > >> > >>> Jedi wrote: > >>> > >>>> hello > >>>> > >>>> > >>>> Is there any example of how to add JTAG port support into > >>>> own non-SOPC builder design like I can directly access > >>>> SPI config port? > >>>> > >>>> For example I want to read/set own register word from > >>>> an own JTAG tool. > >>>> > >>> > >>> Okay..getting some own defined bitstream out of JTAG port > >>> when assigning something to "tdouser"... > >>> > >>> But still unclear now what those JTAG IR exactly do: > >>> > >>> 0000001100 > >>> 0000001101 > >>> 0000001110 > >>> > >>> Any more documentation about this? > >>> Or is this some high-security risk NDA stuff? > >>> > >>> thx > >>> rick > >>> > >> > >> http://wiki.openchip.org/index.php/Altera:JTAG > >> > >> uups I used 1110 0x0E instruction not 0x0D as I previously posted > >> > > > > Correction (o; > > > > instruction 0000001101 is CONFIG_IO as documented in BSD file... > > > > Used 0000001100 last night for shifting out own shift register content > > successfully... > > > > As the TCK/TMS/TDI signals are also available in the module... > > probably this would mean I could also use unused IR codes with > > own TAP controller? > > > > > > Now have to wait for EBV Finland returning my other NIOS board > > for signal capturing (o; > > > > One strange thing...jtag discovery tool reports DR chain length > of "7" for IR 0x00E: > > Detecting DR length for IR 0000001110 ... 7 > > For 0x00C and 0x00D it shows normal "has to be defined" behaviour: > > Detecting DR length for IR 0000001100 ... -1 > Detecting DR length for IR 0000001101 ... -1 > > > > rick jtag discovery tool? which one do you mean? the 0x0E is defenetly "the" USER instruction it should be 'Open' when device is unconfigured.. the JTAG pins are not all directly accessible so you can not add your own Instructions but on the Altera you can monitor full traffic on the JTAG that passes by (that is not available on Xilinx at least pre V4) anttiArticle: 86123
Hi: I am going to work with FPGAs inside the Cray XD1. My question is, wether there exists an implementation of the Cray Application Acceleration API (which is needed in order to access the FPGA) in Fortran 77. Thanks in advance. AndreasArticle: 86124
Antti Lukats wrote: > "Jedi" <me@aol.com> schrieb im Newsbeitrag > news:xn8ue.45$K76.41@read3.inet.fi... > >>Jedi wrote: >> >>>Antti Lukats wrote: >>> >>> >>>>"Jedi" <me@aol.com> schrieb im Newsbeitrag >>>>news:cT_te.335$N23.291@read3.inet.fi... >>>> >>>> >>>>>Jedi wrote: >>>>> >>>>> >>>>>>hello >>>>>> >>>>>> >>>>>>Is there any example of how to add JTAG port support into >>>>>>own non-SOPC builder design like I can directly access >>>>>>SPI config port? >>>>>> >>>>>>For example I want to read/set own register word from >>>>>>an own JTAG tool. >>>>>> >>>>> >>>>>Okay..getting some own defined bitstream out of JTAG port >>>>>when assigning something to "tdouser"... >>>>> >>>>>But still unclear now what those JTAG IR exactly do: >>>>> >>>>>0000001100 >>>>>0000001101 >>>>>0000001110 >>>>> >>>>>Any more documentation about this? >>>>>Or is this some high-security risk NDA stuff? >>>>> >>>>>thx >>>>>rick >>>>> >>>> >>>>http://wiki.openchip.org/index.php/Altera:JTAG >>>> >>>>uups I used 1110 0x0E instruction not 0x0D as I previously posted >>>> >>> >>>Correction (o; >>> >>>instruction 0000001101 is CONFIG_IO as documented in BSD file... >>> >>>Used 0000001100 last night for shifting out own shift register content >>>successfully... >>> >>>As the TCK/TMS/TDI signals are also available in the module... >>>probably this would mean I could also use unused IR codes with >>>own TAP controller? >>> >>> >>>Now have to wait for EBV Finland returning my other NIOS board >>>for signal capturing (o; >>> >> >>One strange thing...jtag discovery tool reports DR chain length >>of "7" for IR 0x00E: >> >>Detecting DR length for IR 0000001110 ... 7 >> >>For 0x00C and 0x00D it shows normal "has to be defined" behaviour: >> >>Detecting DR length for IR 0000001100 ... -1 >>Detecting DR length for IR 0000001101 ... -1 >> >> >> >>rick > > > jtag discovery tool? which one do you mean? Using the jtag tools from the openwince project at sf.net. Great for boundary scan flashing and testing since you can add your own ir/dr definitions and get/set/reset individual boundary scan registers. > > the 0x0E is defenetly "the" USER instruction it should be 'Open' when device > is unconfigured.. Hmm..might be NIOS2 config gets switched back residing in SPI during discovery (o; > > the JTAG pins are not all directly accessible so you can not add your own > Instructions > but on the Altera you can monitor full traffic on the JTAG that passes by > (that is not available on Xilinx at least pre V4) How about Lattice? rick
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