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"GMM50" <george.martin@att.net> wrote in news:1119375054.622966.257160@o13g2000cwo.googlegroups.com: >> I am using a MAX II part in a new design with 3.3V supplies. >> I understand why the inputs might not be 5 volt tolerant. > > Be careful with your terms. 5 volt tolerant means that the device can > survice and operate connected to other 5 volt devices. Typically it's > used when a 3.3 or lower voltage device is connected to a 5 volt > device and means that the 5 vold device won't damage the 3.3 volt > device. > > 5 volt compatible means that the 3.3 volt device will receive and > transmit 5 volt voltage levels ignals. TTL compatible means TTL > signal levels and CMOS compatible means CMOS voltage levels > >> Altera states that the outputs are not 5 volt tolerant when driving >> CMOS but are OK for TTL. Since TTL is essentially dead, I'm not sure >> this is of any real benefit, however this is not my main concern. > > Change your word tolerant to compatible and perhaps your sentence > becomes clearer. > >> I don't see why there would be any problem driving a CMOS input >> provided that the CMOS input will accept 3.3V signals as high. There >> certainly isn't going to be any significant current flow into the >> CMOS gate. > > Hope this helped. > > gm > > I don't have any issue with your terminology. I think the reason I suggested 5 volt tolerant was because Altera goes to great length talking about pullup resistors and clamping diodes for output signals which implied that there might be a "tolerance issue" . I think that Altera could have been clearer by stating that the part can drive TTL compatible inputs rather than simply stating TTL. TTL parts are members of families such as the 74LS. TTL compatible are parts like the members of the 74HCT family (and many others). All Altera really needed to do was discuss the Vih threshold issue in the first place. -- Al Clark Danville Signal Processing, Inc. -------------------------------------------------------------------- Purveyors of Fine DSP Hardware and other Cool Stuff Available at http://www.danvillesignal.comArticle: 86076
Mirko Roller wrote: > Hi, > > Iam designing a little cpu board with an fbga-289-14x14 chip. > > Where can i get a dru file for eagle, so i can design the board. > > greetings, Mirko > You must make it yourself, mirroring the specifications of your board house. SylvainArticle: 86077
Last week-end you were watching a construction site. Let's see what happens when everything is cleaned up. I think the first emphasis was on getting a structure in place. Just keep looking... Peter AlfkeArticle: 86078
When you generate a core in ISE, the CoreGen tool creates a file
with your module name and extension .veo
(so if your core is called my_dds, you should have a file called
my_dds.veo)
In this file is an instantiation template for the CoreGen module.
It may look like:
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
my_dds YourInstanceName (
.DATA(DATA),
.WE(WE),
.A(A),
.CLK(CLK),
.ACLR(ACLR),
.RFD(RFD),
.RDY(RDY),
.SINE(SINE),
.COSINE(COSINE));
// INST_TAG_END ------ End INSTANTIATION Template ---------
In Verilog you can't tell from the template which ports are ins,
outs, vectors, scalar. You can find this information if you look
into the generated simulation module my_dds.v
Here you may find something like:
module my_dds(
DATA,
WE,
A,
CLK,
ACLR,
RFD,
RDY,
SINE,
COSINE
); // synthesis black_box
input [27 : 0] DATA;
input WE;
input [4 : 0] A;
input CLK;
input ACLR;
output RFD;
output RDY;
output [5 : 0] SINE;
output [5 : 0] COSINE;
If you're using the project navigator, an easy way to see how
to instantiate the module is to go to Project-->NewSource
and make a new Verilog TestFixture associated with my_dds.
This will generate a file with the instantiation template and
registers and wires for the modules inputs and outputs. It may
look like:
module my_dds_test_dds_v_tf();
// DATE: 14:54:07 06/21/2005
// MODULE: my_dds
// DESIGN: my_dds
// FILENAME: test_dds.v
// PROJECT: FastVideo1
// VERSION:
// Inputs
reg [27:0] DATA;
reg WE;
reg [4:0] A;
reg CLK;
reg ACLR;
// Outputs
wire RFD;
wire RDY;
wire [5:0] SINE;
wire [5:0] COSINE;
// Bidirs
// Instantiate the UUT
my_dds uut (
.DATA(DATA),
.WE(WE),
.A(A),
.CLK(CLK),
.ACLR(ACLR),
.RFD(RFD),
.RDY(RDY),
.SINE(SINE),
.COSINE(COSINE)
);
// Initialize Inputs
`ifdef auto_init
initial begin
DATA = 0;
WE = 0;
A = 0;
CLK = 0;
ACLR = 0;
end
`endif
endmodule
Obviously the code at the bottom is for simulation only, but
the uut instantiation and the reg's and wires should work
with synthesizable code.
Hope this helps,
Gabor
angilberto wrote:
> Hi all,
> I'm having a hell of a time trying to use a Xilinx IPCore (DDS).
>
> I can generate the CORE, it seems I can instantiate it (not sure --
> verilog/fpga newbie).
>
> Everything seems to be ok, but I get no output -- like the output pins
> are not connected to module's sin/cos output...
>
> Can anyone provide a sample (small one) code showing how to really
> instantiate a CORE into a Verilog projet ?
>
> Thank you,
>
> Angilberto.
Article: 86079Mirko Roller <unknown@unknown.de> wrote: > Sylvain Munaut wrote: > > Mirko Roller wrote: > >> Hi, > >> > >> Iam designing a little cpu board with an fbga-289-14x14 chip. > >> > >> Where can i get a dru file for eagle, so i can design the board. > >> > >> greetings, Mirko > >> > > > > You must make it yourself, mirroring the specifications of your board > > house. > > > > > > Sylvain > Someone knows a board house in germany, who can build boards with fbga parts > on it ? What ball spacing is fbga-289-14x14? 1.27/1/0.8 mm? With 1.0 mm spacing you need 0.14/0.14 lines/spaces, to my knowledge only available as "pool" offer from multi-pcb (0.125 as a sur-plus to the normal 0.15). E.g. q-pcb offers placement services. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 86080
What do people in this forum see is the future of FPGA 4 to 5 years down the line? FPGA, generic processor, or ASIC? ASICs have won out for consumer applications until recently, but now generic processors are doing tasks that used to be done almost exclusively with ASICs. Take MPEG decoding and/or encoding, like in a DVR for instance. There used to be a dozen or two different chip manufacturers that produced ASICs for this field, and now most of them aren't even bothering to come out with new products. The push seems to be using DSPs to do these things, the TI chips being the obvious leader. Part of this has to do with the ever-changing MPEG-4 "standard" and manufacturers being unwilling to commit tons of resources to design a chip that may be obsolete in a year, but it also makes sense from a technical and risk standpoint to do it in software instead of hardware. DSPs are also very power-efficient, even running full out at 600 MHz or more. Less demanding applications have already gone to generic processors, too. What are the applications it is most widely used right now, and what will be the applications that it will be highly used in a near future? Prototyping ASICs. Relatively low-volume tasks where cost is not necessarily the overwhelming priority, instead it's flexibility or development time (space, military, etc.). High-end applications where performance of DSPs is not enough (heavy-duty FIR filtering, etc.). Future applications will be the same as now. Currently, on average, a consumer (who may own cellphone, camera, camcorder, ipod, etc.) owns zero FPGAs. Do you see this ratio of number of FPGAs/consumer changing? No. Or. Do you see power and clock speed to continue to remain as major bottlenecks for FPGAs compared to ASICs in the next few years? Or will the difference diminish in sub 65nm technologies? Or will it blow up?? DSPs and generic processors will continue to take over for ASICs. FPGAs will remain a niche market. There are two main advantages, as I see, of FPGAs over ASICs or processors - ability to implement designs faster (shorter time to market) and ability to perform easy "firmware updates". Will these two factors ever influence the decisions of designers to switch to FPGAs completely in the future? Designers of what? Consumer products? No, only if cost is reduced to compete with DSPs, generic processors, and ASICs. Most ASICs these days use microcode anyway and are already firmware upgradable. DSP firmware can be upgraded as easily (perhaps easier) than FPGAs. DSPs have little of the clock speed and power consumption disadvantages of FPGAs, and are cheap too. If you are not as optimistic about FPGAs as I am sounding, what major bottlenecks do you think will check FPGA growth? In most applications generic processors will do the job just fine and cost less, burn less power, and might even be cheaper to develop with. Software programmers are cheap nowadays.Article: 86081
I had a similar problem once. If you must have flow control, and there's latency in the feedback, then you need FIFOs. I know of no way of avoiding them. The trick is to have one multichannel FIFO controller that controls the addresses to a single large RAM, with all the virtual FIFOs for the TDM channels using (different parts of) the same RAM, rather than having a bazillion independent FIFOs. Only one virtual FIFO needs to be writen at any time (this being the nature of TDM), which means you can TDM at least the write side logic of the FIFO controller. All state variables in the FIFO controller will be held in small rams (CLB ram is good for this, if you don't have more than 32 channels) rather than flip flops. Regards, Allan P.S. If anyone has missed me recently, it's because my news server has been down. :(Article: 86082
Hi, Iam designing a little cpu board with an fbga-289-14x14 chip. Where can i get a dru file for eagle, so i can design the board. greetings, MirkoArticle: 86083
Sylvain Munaut wrote: > Mirko Roller wrote: >> Hi, >> >> Iam designing a little cpu board with an fbga-289-14x14 chip. >> >> Where can i get a dru file for eagle, so i can design the board. >> >> greetings, Mirko >> > > You must make it yourself, mirroring the specifications of your board > house. > > > Sylvain Someone knows a board house in germany, who can build boards with fbga parts on it ? greetings, MirkoArticle: 86084
square root of 289 = 17, and 17 x 0.8 =14.2, so it is a tight fit with 0.8 mm ball spacing. Any other spacing is out of the question Peter AlfkeArticle: 86085
Jedi wrote: > hello > > > Is there any example of how to add JTAG port support into > own non-SOPC builder design like I can directly access > SPI config port? > > For example I want to read/set own register word from > an own JTAG tool. > Okay..getting some own defined bitstream out of JTAG port when assigning something to "tdouser"... But still unclear now what those JTAG IR exactly do: 0000001100 0000001101 0000001110 Any more documentation about this? Or is this some high-security risk NDA stuff? thx rickArticle: 86086
Mirko Roller wrote: > Hi, > > Iam designing a little cpu board with an fbga-289-14x14 chip. > > Where can i get a dru file for eagle, so i can design the board. > Sorry.. But what has it to do with fpga? (o; rickArticle: 86087
Symon, I sent you a lengthy private response. If you want to share some of it, be my guest... Peter AlfkeArticle: 86088
Chris, Good questions. I hope lots of people respond and give their two cents. Austin Chris wrote: > What do people in this forum see is the future of FPGA 4 to 5 years down the line? > > FPGA, generic processor, or ASIC? ASICs have won out for consumer applications until recently, but now generic processors are doing tasks that used to be done almost exclusively with ASICs. Take MPEG decoding and/or encoding, like in a DVR for instance. There used to be a dozen or two different chip manufacturers that produced ASICs for this field, and now most of them aren't even bothering to come out with new products. The push seems to be using DSPs to do these things, the TI chips being the obvious leader. Part of this has to do with the ever-changing MPEG-4 "standard" and manufacturers being unwilling to commit tons of resources to design a chip that may be obsolete in a year, but it also makes sense from a technical and risk standpoint to do it in software instead of hardware. DSPs are also very power-efficient, even running full out at 600 MHz or more. Less demanding applications have already gone to generic processors, too. > > What are the applications it is most widely used right now, and what will be the applications that it will be highly used in a near future? > > Prototyping ASICs. Relatively low-volume tasks where cost is not necessarily the overwhelming priority, instead it's flexibility or development time (space, military, etc.). High-end applications where performance of DSPs is not enough (heavy-duty FIR filtering, etc.). Future applications will be the same as now. > > Currently, on average, a consumer (who may own cellphone, camera, camcorder, ipod, etc.) owns zero FPGAs. Do you see this ratio of number of FPGAs/consumer changing? > > No. > > Or. Do you see power and clock speed to continue to remain as major bottlenecks for FPGAs compared to ASICs in the next few years? Or will the difference diminish in sub 65nm technologies? Or will it blow up?? > > DSPs and generic processors will continue to take over for ASICs. FPGAs will remain a niche market. > > There are two main advantages, as I see, of FPGAs over ASICs or processors - ability to implement designs faster (shorter time to market) and ability to perform easy "firmware updates". Will these two factors ever influence the decisions of designers to switch to FPGAs completely in the future? > > Designers of what? Consumer products? No, only if cost is reduced to compete with DSPs, generic processors, and ASICs. Most ASICs these days use microcode anyway and are already firmware upgradable. DSP firmware can be upgraded as easily (perhaps easier) than FPGAs. DSPs have little of the clock speed and power consumption disadvantages of FPGAs, and are cheap too. > > If you are not as optimistic about FPGAs as I am sounding, what major bottlenecks do you think will check FPGA growth? > > In most applications generic processors will do the job just fine and cost less, burn less power, and might even be cheaper to develop with. Software programmers are cheap nowadays.Article: 86089
Join Altera's free net seminar, Addressing Base Station Design Challenges for 3GPP Release 6 and Beyond. You will find out about the trends and challenges involved in next generation cellular base station designs and how they can be addressed with Altera FPGAs. This free, one-hour net seminar will cover: . Current challenges faced by wireless carriers and infrastructure OEMs . Enabling technologies such as HSUPA, MIMO and OFDMA . Reconfigurable, scalable and cost-effective base station design using FPGAs Attend the net seminar for a chance to win a Gateway DVD Recorder/Player ($250 USD value) built with Altera devices. To register, click on the link below http://seminar2.techonline.com/s/altera_jun2905Article: 86090
Uwe Bonnes wrote: > Mirko Roller <unknown@unknown.de> wrote: >> Sylvain Munaut wrote: > >> > Mirko Roller wrote: >> >> Hi, >> >> >> >> Iam designing a little cpu board with an fbga-289-14x14 chip. >> >> >> >> Where can i get a dru file for eagle, so i can design the board. >> >> >> >> greetings, Mirko >> >> >> > >> > You must make it yourself, mirroring the specifications of your board >> > house. >> > >> > >> > Sylvain > >> Someone knows a board house in germany, who can build boards with fbga >> parts on it ? > > What ball spacing is fbga-289-14x14? 1.27/1/0.8 mm? With 1.0 mm spacing > you > need 0.14/0.14 lines/spaces, to my knowledge only available as "pool" > offer > from multi-pcb (0.125 as a sur-plus to the normal 0.15). E.g. q-pcb > offers placement services. > > Bye > fbga is 0.8mm ball spacing, and iam also searching for a firm, who can assemble me the fbga chip on the board, couse i dont know how to handle fbga. greetings, MirkoArticle: 86091
Hi Johnson, Apologies to the newsgroup for advertising, but have a look on our website www.tyder.com Our software ONEoverT will design your filter and produce the VHDL, testbenches, test data automaically for you. It will even produce the compile script which you can run through your favourite simulator and see the results of your filter in simulation. The VHDL can then be targetted for any FPGA you like (Xilinx, Altera etc etc..whatever you like). Have a look at the documentation. It shows how easy it is. You can also download ONEoverT which will let you experiment with different types of filters. Alan "Johnson Liuis" <gpsabove@yahoo.com> wrote in message news:d988pn$tvl$1@domitilla.aioe.org... > > Does anybody have filter design experience with FPGA? I would like to know a > general picture with recent FPGA technologies like XtremeDSP and others. I > am also curious about the limitation of FPGA design on filter design, like > the maximum center frequency and bandwidth of the filters that can be > implemented with FPGA. Could anybody let me know if I am able to simulate a > SAW (surface acoustic wave ) filter with 185MHz center frequency and 4MHz > double-side bandwidth, and Max. 20dB insertion loss inside of a FPGA? > > Any information will be highly appreciated. Thanks in advance. > > Johnson > >Article: 86092
Johnson Liuis wrote: >Does anybody have filter design experience with FPGA? I would like to know a >general picture with recent FPGA technologies like XtremeDSP and others. I >am also curious about the limitation of FPGA design on filter design, like >the maximum center frequency and bandwidth of the filters that can be >implemented with FPGA. Could anybody let me know if I am able to simulate a >SAW (surface acoustic wave ) filter with 185MHz center frequency > Well, the Nyquist criteria indicates you will need an ADC operating at above 370 Megasamples/second, with sufficient number of bits at that frequency to give the signal to noise ratio required for your application. This may be the real problem. Depending on the type of filter required, I imagine some of the higher-end FPGAs could handle the arithmetic at this rate, although some multiplexing of resources might be required. Then, a DAC with the same sample rate and sufficent bits for reconstruction of the signal will be needed after the FPGA. JonArticle: 86093
Un bel giorno Chris digiṭ: > What do people in this forum see is the future of FPGA 4 to 5 years down > the line? > > FPGA, generic processor, or ASIC? My preference would be for FPGA with more specialized functions, and a (really) user-friendly software development environment: pseudo visual programming, no need for external toolchains for embedded CPUs development, integrated debugging instead of crappy simulators, and so on. FPGA are cool, there are a lot of special applications where they are already (and always will be) the best choice; but for the real breakthrough, IMHO they have to win the match with generic 16- and 32-bit microcontrollers/DSP for small and medium-volume applications. > Currently, on average, a consumer (who may own cellphone, camera, > camcorder, ipod, etc.) owns zero FPGAs. Do you see this ratio of number > of FPGAs/consumer changing? I really don't know much about ASIC, but as far as I can see, I don't think that FPGA would ever be the right choice for this type of volume applications. If I plan to sell one million of units, I don't care much if I have to spend one million dollars for ASIC setup, if then one chip will cost one dollar (ASIC) instead of ten (FPGA). > There are two main advantages, as I see, of FPGAs over ASICs or > processors - ability to implement designs faster (shorter time to > market) and ability to perform easy "firmware updates". Generic processors are as fast developing and upgradable than FPGA (if not more), and I used to think that the development steps for ASIC and FPGA until the "real" manufacturing were very similar. Am I wrong? And by the way, I don't think that if you order one million FPGA, either Xilinx or Altera will ship them overnight. :) -- asdArticle: 86094
Thanks, Jon, You mentioned "although some multiplexing of resources might be required." Could you please explain it in a little bit more detail? Thanks. Johnson "Jon Elson" <jmelson@artsci.wustl.edu> wrote in message news:42B89AB2.5040006@artsci.wustl.edu... > > > Johnson Liuis wrote: > >>Does anybody have filter design experience with FPGA? I would like to know >>a general picture with recent FPGA technologies like XtremeDSP and others. >>I am also curious about the limitation of FPGA design on filter design, >>like the maximum center frequency and bandwidth of the filters that can be >>implemented with FPGA. Could anybody let me know if I am able to simulate >>a SAW (surface acoustic wave ) filter with 185MHz center frequency >> > Well, the Nyquist criteria indicates you will need an ADC operating at > above 370 Megasamples/second, with sufficient number of bits at that > frequency > to give the signal to noise ratio required for your application. This may > be the > real problem. Depending on the type of filter required, I imagine some of > the > higher-end FPGAs could handle the arithmetic at this rate, although some > multiplexing of resources might be required. Then, a DAC with the same > sample rate and sufficent bits for reconstruction of the signal will be > needed after the FPGA. > > Jon >Article: 86095
lovesinghal wrote: > Hi All, > Thanks for your responses. > Marc and Jim, your responses were very interesting. I learned a lot > going through those searches. > Rene, I did not say that I will base my PhD topic on this discussion. > My advisor is helping me decide a topic in a major way. Through this > side discussion, I want to know the industry opinion and opinions of > people who use FPGAs in their designs. Here's another research node : Besides the STW22000 device, in one of the interviews the Cell Processor designers mentioned having configurable IO (and how that allowed design closure earlier). [IIRC IBM does have a cross license to Xilinx FPGAs - Xilinx got the PowerPC in return]. Does anyone have info on just how configurable the Cell processor IO is ? Which tool flows support it ? -jgArticle: 86096
Yes, but it might be nice if most of these files were put into a subdirectory so they don't clutter up the project directory. Best wishes, --Phil Martel "Frank Chee" <F.r.a.n.c.i.s.C.h.e.e.(Remove the dots)@hotmail.com> wrote in message news:d90gun$d8p$1@mawar.singnet.com.sg... > when u become experienced in xilinx, they ain't useless files. > every file serves a purpose. > > > > "Qi Sun" <qisun@NOSPAM_itee.uq.edu.au> wrote in message > news:d8td87$sr3$1@bunyip2.cc.uq.edu.au... >> Too many useless files. >> > >Article: 86097
lovesinghal wrote: > Currently, on average, a consumer (who may own cellphone, camera, > camcorder, ipod, etc.) owns zero FPGAs. Do you see this ratio of number > of FPGAs/consumer changing? There was a thread here recently where someone saw a Spartan3 part in their new flatscreen TV.Article: 86098
dalai lamah wrote:
> My preference would be for FPGA with more specialized functions
Here come my wishes:
1. Built-in tamper-resistant cryptoprocessor block with write-only
nonvolatile
memory. There should be no way to read this memory, neither externally
(through JTAG, SignalTap etc.) nor internally, because it should contain
a wide (at least 128 bits!) symmetric key. This block should have serial
input and serial output and encrypt its input data using something very
strong, say AES. It doesn't have to be fast, but must be as secure as
possible.
2. Configuration bitstreams MUST be encrypted to prevent cloning and
to open the field of data encryption to FPGAs -- today every moron with
a logic analyzer can easily crack a SRAM FPGA-based scrambler.
The encryption block mentioned above can be reused for bitstream
encryption too. In this case SRAM-based configuration would not be
a problem.
3. There should be a way to "destroy" the chip from its internals, i.e.
to make it useless. This could be a trurly physical destruction, but
if the cryptoprocessor's nonvolatile memory block were erased, it
would be enough.
4. Fuses, more fuses! JTAG disable, readback disable etc.
5. Partial reconfigurability.
Best regards
Piotr Wyderski
Article: 86099Terrifc, Gabor. Thank you very much for the TIPs (Capital tip) -- I'll take a closer look into it. Angilberto
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