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On Mon, 13 Jun 2005 20:51:55 +0000, Joseph H Allen wrote: > In article <3h3o19Ff6phbU1@individual.net>, > Falk Brunner <Falk.Brunner@gmx.de> wrote: >>"Austin Franklin" <austin@dark99room.com> schrieb im Newsbeitrag >>news:911re.4452$Ub4.3176@fe06.lga... > >>> > I used Synplify for many years but I haven't used it recently. I >>> > switched to XST about a year ago when it got to the good enough level. >>> > XST improves with each release, my gut says that it's pretty close to >>> > Synplify's level at this point. > >>Recently, I had a design, not really a big deal. Running at 36 and 72 MHz. >>XST was not able to squeeze it into a XC2S50E, but Synplify was. (~1600 LUTs >>to ~ 1200 LUTs). Speed was not the problem, both implementation where fast >>enough. But Synplify was more area efficient. >>We are using XST only, this was just a test with a real case. > > I'm having the same experience: Synplify_pro 8.1 uses 97% (map with -tx on) > of an XC2V6000 (which "map" with "-tx on -timing" actually can close timing > on), whereas XST 5.2 uses 102% (no -tx on). I think Synplify's CSE (or > "resource sharing") is better. The difference in price between an XC2V8000 > and an XC2V6000 more than covers Synplicity's fee. On the other hand, XST > and Synplicity seem to be on par as far as the resulting design's speed. > > One big annoyance: attributes use a completely different concept between the > two tools: Synplicity, following verilog tradition, associates attributes by > position within a comment before the ; of an instantiation. XST follow VHDL > and associates them by name: the comment can be anywhere in the file. But > now that I have my conversion script, this is no big deal. XST uses > data_bus<1> and Synplicity uses data_bus[1]. XST flattens the hierarchy, > Synplicity doesn't (earlier versions used to). All of this makes the .ucf > file fun. > > We are not using later versions of XST due to answer record #16808 (casex > doesn't always make correct code)- I'd like to try 7.1i, but it wont work on > RedHat 7.3. Synplify 8.1 (their latest) does work in RedHat 7.3. Also code > errors which XST 5.2 allows cause XST 6.1 - 6.3 to core dump- which makes it > difficult to find the error. Note that we have to run XST 5.2i in wine (but > we then run place & route with 6.2isp3). > > Other issues: synplicity runs about 33% faster, but sometimes for larger > designs it is much faster. I think we are hitting some exponential time > algorithm in XST. > > The error reporting from Synplify is much better than XST: > > // XST gives no error > output [5:0] foo; > reg [4:0] foo; > > // XST gives no error: two always blocks writing to the same signal when the > // signal gets optimized out because nobody is readying it. > reg x; > > always @(posedge clk or negedge reset_l) > if (!reset_l) > x <= 0; > > always @(posedge clk or negedge reset_l) > if (!reset_l) > x <= 0; > else > x <= y; There are switches in the XST script for controlling things like hierarchy flattening and bus delimiters. There is an issue with case statements doing something unexpected if you don't have a default, the solution is to always have a default: in every case statement, this is the correct thing to do anyway. I played around with XST's switches until I was happy with the results. XST's switches can make a big difference in the size and speed of the final results. Here are the switches from one of my scripts, run -ifn loopback_m325_sma.xprj -ifmt Verilog -ofn loopback_m325_sma.ngc -top loopback_m325_sma -ofmt NGC -p xc2vp70-6-ff1704 -opt_mode SPEED -opt_level 1 -max_fanout 32 -keep_hierarchy no -register_duplication YES -equivalent_register_removal no -hierarchy_separator / -bus_delimiter <> -mux_extract YES -mux_style MUXF -ram_extract YES -ram_style Auto -rom_extract YES -rom_style Distributed -verilog2001 NO -vlgcase Full-Parallel -decoder_extract YES -priority_extract YES -shreg_extract YES -shift_extract YES -xor_collapse YES -resource_sharing YES -iobuf NO -register_balancing no -slice_packing Yes -glob_opt max_delay -fsm_encoding CompactArticle: 85676
Austin Lesea wrote: > > All parts are in stock here at the factory (I checked). That a > distributor doesn't order them is of course troubling, and another > issue. That Digikey doesn't carry the latest and greatest products > may be because they offer little to no support. We prefer our > distributors to earn their percentages (that they make on the parts). What the hell do I need (or WANT) anyone looking over my shoulder? Let me have the parts without the overhead. After the Xilinx web site, I don't NEED anything else but my simulator. > > Other distributors do not want to be undersold by someone who offers > no services (and we don't see any benefit in that either). > > If all you need are some samples, you should develop a better > relationship with your local X distributor or X representative. What does a (high priced) distributor actually deliver to me? I'm not working for Boeing or other huge corporation. Digi-Key is the right-sized distributor for me. I look up the part, and order it. Very simple. JonArticle: 85677
Hi, kittyawake@gmail.com wrote: > i am trying to collect some data and store in the memory.I want this > data to be continuous.Can i write my own section like > (.text,.sdata,.bss,etc..) in the linker script??and then assign a > pointer which points to this section and store the data using this > pointer???I have never written a linker script before.Please give me > some suggestions if i want to write such a section in linker > script.What does ALIGN(8) or ALIGN(4) mean? ALIGN(n) means move the current address pointer (called '.' in gnu linker terminology) to the next address that is n-byte aligned - so ALIGN(4) means the next word aligned address. More broadly, the two sources I recommend are the Gnu linker documentation: http://www.gnu.org/software/binutils/manual/ld-2.9.1/html_mono/ld.html and the following Xilinx app note: http://www.xilinx.com/bvdocs/appnotes/xapp642.pdf Link scripts are cryptic, but not actually difficult. You need to just take your time, read the documentation carefully and be prepared to experiment. You should also learn how to use the objdump tool (either mb-objdump or ppc-eabi-objdump, depending on which processor you are using). It will give you a lot of info about your object files, including the sections and symbols, and where they are located. Hope this helps, JohnArticle: 85678
Hi George, Do you have any ideas on how to do this? I am also using Altera parts...I am using a Stratix. ThanksArticle: 85679
mk wrote: > Actually the 2.5 Gb/s is with electrical bit rate which results by > encoding using the 8b10 code so it is not available as data rate at > all. The best logical bit rate is 2 Gb/s on top of which you put all > the framing, packetization etc. so actual utilization is still lower > than that. Woops :) Shouldn't have missed that one.. Had it somehow in my head that it was a 3.125Gb/s raw bit rate. JeremyArticle: 85680
One additional note. As mentioned below, the master should ACK each byte
that it reads, except for the last byte. The last byte should be nacked
prior to the stop condition.
dbrown
"Gabor" <gabor@alacron.com> wrote in message
news:1118690295.803563.225360@g43g2000cwa.googlegroups.com...
> praveen.kantharajapura@gmail.com wrote:
>> Hi Gabor ,
>>
>> Thanks for the reply. My EEPROM is write protected i will only be
>> reading the first 128 bytes, is this flow diagram all right.
>>
>>
>> 1-bit 8-bits 1-bit
>>
>> Start from master --->> EEPROM Slave address("10100001") -->> ACK
>> from eeprom --->>
>
> Actually you need to start with write address "10100000" in order
> to write the address register (you don't need to write the EEPROM
> array so write protect doesn't matter).
>
>>
>>
>> 8-bits 1-bit
>> Write register address "00000000" --->> ACk from EEPROM
>
> Right here you need to switch to read mode. There are two
> ways to do this. Either master sends Stop followed by Start
> or master sends repeated start. If you intend to reuse this
> code for other peripherals besides EEPROM, you'll find the
> repeated start is compatible with more chips.
>
> Then you need to provide slave address "10100001" for read
> and get ack from slave then:
>
>> 8-bits 1-bit
>> --->> Data[0]
>> from EEPROM --->> ACK from master
>>
>> 8-bits 1-bit
>>
>> ................. --->>Data[127] from EEPROM --->> STOP from master
>>
>> I will generate the STOP condition after receiving 128 bytes.
>>
>> Any comments on this.
>>
>>
>> Regards,
>> Praveen
>>
>>
> Also you talk about "bits" when you send start and stop. These
> conditions
> do not toggle the SCL line so they are not usually counted as "bits"
> as would be data or Ack cycles.
>
> Regards,
> Gabor
>
Article: 85681Check the delay report and follow your net... It's a little easier to look through the text rather than using the FPGA Editor, but sometimes they complement each other. Jason "MM" <mbmsv@yahoo.com> wrote in message news:3gtpr1Feefu1U1@individual.net... >I am getting the following warning on a Virtex-II design: > > WARNING:Route - CLK Net:clk50_BUFGP may have excessive skew because 1 > NON-CLK pins failed to route using a CLK template. > > My question is how can I find the problematic pin? > > A similar question was asked here in the past, but the discussion slipped > into design practices. My design is pretty big and the biggest part of it > is > third party core, for which I don't have source code. So, I need to figure > out what exactly causes this warning... > > Thanks, > /Mikhail > > >Article: 85682
On Mon, 13 Jun 2005 09:29:26 -0700, "Symon" <symon_brewer@hotmail.com> wrote: >"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message >news:oibka1p30g1hs69add4jamu01mi9pc8de2@4ax.com... >> On Fri, 10 Jun 2005 22:04:01 +0200, "Falk Brunner" >> <Falk.Brunner@gmx.de> wrote: >> >> I do stuff with jitters in the >> low single digits of ps, and use microstrip traces referenced to power >> planes all the time. >> >Single ended? >Cheers, Syms. > Yup. JohnArticle: 85683
David Brown wrote:
> One additional note. As mentioned below, the master should ACK each byte
> that it reads, except for the last byte. The last byte should be nacked
> prior to the stop condition.
>
How will the master know that this byte is the last byte, and what
happens if the master acknowledges the last byte also.
> dbrown
>
> "Gabor" <gabor@alacron.com> wrote in message
> news:1118690295.803563.225360@g43g2000cwa.googlegroups.com...
> > praveen.kantharajapura@gmail.com wrote:
> >> Hi Gabor ,
> >>
> >> Thanks for the reply. My EEPROM is write protected i will only be
> >> reading the first 128 bytes, is this flow diagram all right.
> >>
> >>
> >> 1-bit 8-bits 1-bit
> >>
> >> Start from master --->> EEPROM Slave address("10100001") -->> ACK
> >> from eeprom --->>
> >
> > Actually you need to start with write address "10100000" in order
> > to write the address register (you don't need to write the EEPROM
> > array so write protect doesn't matter).
> >
> >>
> >>
> >> 8-bits 1-bit
> >> Write register address "00000000" --->> ACk from EEPROM
> >
> > Right here you need to switch to read mode. There are two
> > ways to do this. Either master sends Stop followed by Start
> > or master sends repeated start. If you intend to reuse this
> > code for other peripherals besides EEPROM, you'll find the
> > repeated start is compatible with more chips.
> >
> > Then you need to provide slave address "10100001" for read
> > and get ack from slave then:
> >
> >> 8-bits 1-bit
> >> --->> Data[0]
> >> from EEPROM --->> ACK from master
> >>
> >> 8-bits 1-bit
> >>
> >> ................. --->>Data[127] from EEPROM --->> STOP from master
> >>
> >> I will generate the STOP condition after receiving 128 bytes.
> >>
> >> Any comments on this.
> >>
> >>
> >> Regards,
> >> Praveen
> >>
> >>
> > Also you talk about "bits" when you send start and stop. These
> > conditions
> > do not toggle the SCL line so they are not usually counted as "bits"
> > as would be data or Ack cycles.
> >
> > Regards,
> > Gabor
> >
Article: 85684Altera's DSP Builder Ray Andraka wrote: > Davy wrote: > > >Hi all, > > > >Is there any tools to convert Matlab M-language to HDL? Thanks! > > > >Best regards, > >Davy > > > > > > > Accelchip sells a tool that does it, but you'll need to tweak the code > some to get something that is reasonable in hardware. You'll get better > results by simply using Matlab as a simulation model and designing a > matching circuit in your favorite HDL. > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759Article: 85685
Last week I finally found why my software wasn't booting from Flash. >From disassembling the generated flash_ext.flash file, the data contained is not actual machine code but rather an "S-Record" Flash file. Once this Flash file was converted to raw binary and cropped off at my designated flash offset, the Nios executed the software code just fine.Article: 85686
Hi,
I think so ..You can specify that in Software Platform Settings in
EDK ..I am not sure ...
--
Parag
Article: 85687Michael, I don't know if this board is available in Germany, but the Avnet FX12 board might be ideal for you. Here are the features.. Virtex-4 FX12 (contains Power PC) 32MB DDR SDRAM 4MB FLASH 8Mb Config FLASH RS232 port 10/100 Mbps Ethernet port 128x64 display 8 LEDs 8 position DIP switch 2 push button switches 50-pin GPIO connection Power Supply Best part is the cost .... $249. Here is the link (sorry it's so long) http://www.em.avnet.com/evk/home/0,1719,RID%253D0%2526CID%253D21013%2526CCD%253DUSA%2526SID%253D4742%2526DID%253DDF2%2526SRT%253D1%2526LID%253D18806%2526PVW%253D%2526BID%253DDF2%2526CTP%253DEVK,00.html On Mon, 13 Jun 2005 01:52:42 GMT, michaeldre@gmx.de (Michael Dreschmann) wrote: >Hello, > >I came in contact with FPGAs at the university and have done some >designs. Now I decided to start with FPGAs in private because I'm >really fascinated by their capabilities. >I think designing a PCB for an FPGA is not simple so I decided to buy >a board for my first (home) steps, but I've some requirement to that >board, because flashing LEDs isn't really interesting... :) > >It should be a Spartan3 1000 or above with a bootflash for a stand >alone powerup and maaaany free pins to connect a lot of things. >Things like clock oscillator and power supply are included on any >board I think. >The next point is external RAM. I'd like testing microblaze with uC >linux but I never worked with linux, especially not with the uC >version so I don't know how much external RAM is neccessary. >Any suggestions? >I've searched the web and only found a single board that has most of >my requirements and can be paid by a student: >http://shop.trenz-electronic.de/catalog/product_info.php?cPath=1_27&products_id=63 >Sorry, can't find the page in english. It has a Spartan3 1000 with >Xilinx Plattform-Flash XCF04 and USB 2.0 transceiver. The only point >I'm missing is the external RAM. >So my question is, do you have any alterntive boards in mind that fits >my requirements and can be paid? What do you think by the board above? >Is it ok? > >Thanks, > MichaelArticle: 85688
Hi all, I am using ModelSim PE 6.0d. I have done functional simulation for my design (i could view all internal signals there) and that works fine. When i run Post P&R simulation i get some misfunctionality. To correct the same i need to view internal signals in the post P&R simulation. But the same does not come if we check the signals listed under UUT. I know this has been posted some time back also but i could not understand correctly. If somebody knows the correct procedure then please help. Thanx in advance.Article: 85689
John, Altera requires anyone doing a HardCopy design to first prototype it in an FPGA, so there isn't really a direct route to HardCopy. It's not a technical issue, it's simply that our whole value proposition (over other firms of ASIC) is that we match the functionality and timing constraints of the FPGA, so that you know when you replace the FPGA with the HardCopy it will work the same. Technically, we could certainly remove this restriction but then if the HardCopy device didn't work in the system, we wouldn't be able to see where the problem lay. Regarding Synplicity support, I'll have to check 7.1 vs 7.7 but if you simply target the appropriate Stratix FPGA in Synplicity, this will do all the required synthesis to LEs and you can then use Quartus II to do the mapping to the HardCopy Stratix device. Hope this clears up your questions. Paul Hollingworth Altera Marketing John M wrote: > I seem to remember Synplicity and Quartus allowing the user to select > an Altera Stratix Hardcopy device as the target directly, as opposed to > targeting an FPGA that is used for prototyping. Quartus 3.0 seems to > support this, and I swear Synplicity did as well. However, I've gone > back from Synplify 7.7 to 7.1, and I can't find any versions that > support Stratix Hardcopy as a target. Am I crazy, or does anyone else > remember this? Also, why did Altera remove support for this? Now, you > have to use an FPGA prototype, and there doesn't seem to be a path to > go directly to a structured ASIC. Thanks. > > JohnArticle: 85690
Hi, I'm still working on creating a DDR interface for an OCM bus. The problem I now face is the following: I need "shifted" clk signals. I'm using a driver originally used for the PLB bus, which has those shifted clks. Since I do not have enough knowledge or time to create shifted clk's myself (The deadline is reaaaly close). So I "borrowed" the clock signals from the PLB bus (Runs on the same speed as the OCM bus, I thought I could give it a try :p. But when I do this, the timing constrains aren't met. So I guess I need to create my own shifted signals from the OCM clk (Which I'm not even using right now) Here is the timing constraint table: ---------------------------------------------------------------------- Constraint | Requested| Actual |LLvls ---------------------------------------------------------------------- NET "bufgp_10/IBUFG" PERIOD = 10 nS HI | N/A | N/A | N/A GH 50.000000 % | | | ---------------------------------------------------------------------- PERIOD analysis for net "dcm_0/dcm_0/CLK0 | 10.000ns | 5.476ns| 17 _BUF" derived from NET "bufgp_10/IBUFG" | | | PERIOD = 10 nS HIGH 50.000000 % | | | ---------------------------------------------------------------------- * TSCLK2CLK90_ocm_ddr_1 = MAXDELAY FROM TIM | 2.250ns | 3.931ns| 5 EGRP "PLB_Clk_ocm_ddr_1" TO TIMEGRP "Clk | | | 90_in_ocm_ddr_1" 2.250 nS | | | ---------------------------------------------------------------------- PATH "FROM CPUS THRU RST_GRP TO FFS" TIG | N/A | 1.810ns| 0 ---------------------------------------------------------------------- PATH "FROM FFS THRU RST_GRP TO FFS" TIG | N/A | 1.445ns| 1 ---------------------------------------------------------------------- PATH "FROM FFS THRU RST_GRP TO CPUS" TIG | N/A | 0.656ns| 0 The one with the * is the one giving the problem. How can I easily make such a clock myself? Btw, I'm using EDK 6.3 and working on the ML310 board. (Virtex 2pro) Thanks in advance, Jim TuilmanArticle: 85691
zoinks@mytrashmail.com wrote: > How can I easily make such a clock myself? > Btw, I'm using EDK 6.3 and working on the ML310 board. (Virtex 2pro) Use a DCM: http://toolbox.xilinx.com/docsan/xilinx5/data/docs/lib/lib0127_111.html#wp1000992 cu, SeanArticle: 85692
I use a Spartan 3 and the ISE software. Now that I'm bringing all the different parts of my project together, I have this problem with the gated clock. I donīt have a clue how to solve it out. It appears in the "Generate Programming File" part: WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net a1_1 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. I tried introducing the clock in a flip-flop whith a CE pin and controllin it, but it was no use. So I donīt use it anymore. It's really weird, cause I add a memory, it's mapped properly, and this dammed warning pops out. With this warning the core doesnīt work propperly in the FPGA. My design clock is 5MHz, so I guess I canīt use the DCM (in case it helped). What can I do? Would it help if I changed the synthesizer and use, say, Simplicity's Simplify software? I would be extremely thankful if anyone could help me. I MEAN IT. ThanksArticle: 85693
As someone who is still working with Spartan II, I was amused to see that my
mothers new television has a Spartan 3 inside ...
Dave
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Article: 85694
> I use a Spartan 3 and the ISE software. Now that I'm bringing all the
different parts of my
> project together, I have this problem with the gated clock. I donīt have a
clue how to solve it
> WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net a1_1 is sourced
by a combinatorial pin.
> It's really weird, cause I add a memory, it's mapped properly, and this
dammed warning pops out
Hmm. It looks like you've (literally) got some wires crossed. I suggest:
* Find all references to this net called a1_1 in your design.
* Identify what exactly generates it.
* Identify where it's used.
* Identify what clock pins it's connected to.
* ...
* profit!
Judging by the name, a1_1 is probably part of a bus of some sort. Most
likely you've just made a typo when connecting up some ports. If so, it
should be easily fixable. If not, and there really is some logic in one of
your clock paths, well you'll need to spend some time analysing what the
circuit's supposed to do, and figure out how to do that *without* gating the
clock.
Good luck,
-Ben-
Article: 85695what kind of tv is that?Article: 85696
"osedax" <osedax_latin@yahoo.com> wrote in message
news:1118747692.631639.100890@g49g2000cwa.googlegroups.com...
> what kind of tv is that?
It is a Loewe Xelos A26 - basically a high end flat panel unit. Being
German, it comes with a circuit diagram.
Dave
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Article: 85697Hi all, I have some basic doubts on PCI arbiter. 1)how is the framen controlled -- i guess it is a shared resource on the PCI bus wher all the devices sitting on the PCI bus have access to it. 2)If a request is received from a device on PCI bus ,should the grant be issued immediately or should the PCI arbiter wait until the framen is dropped (asserted). 3)If a request is received from a device on PCI bus , but the framen is not dropped at all.how should the PCI arbiter react to this condition. Regards, PraveenArticle: 85698
Jedi wrote: > dirk wrote: > >> For my latest Nios II DevKit I have received 2 additional Nios II 1.1 >> Upgrades although the kit already came with this version. I haven't >> received >> any copy of the 5.0 version so far. The most annyoing thing is that they >> guarantee the updates for 1 year but never send any. I had another devkit >> with the old Nios and never got the Nios II software or at least an >> evaluation version of it. If they want us to download the new versions >> then >> they should simply say so on their web site. From the information on >> the web >> site I always get the impression that it's just an evaluation version and >> not the real thing although with previous versions there was no >> difference >> in the end. >> >> >> "Jedi" <me@aol.com> wrote in message >> news:lFDne.179$YR2.156@read3.inet.fi... >> >>> So for how long is NIOS2 5.0 out? >>> >>> Just received today my NIOS2 1.1 upgrade... >>> Unbelievable fast they are (o; >>> > > Well...seems I getting an upgrade maybe...not sure if it also > contains the NISO toolchain sources from the Linux CD as the > Windows sources can be only compiled on Windows... > > But since I also develop FPGA hardware for local distributors > here and do software porting for softcore platforms I am > switching to Lattice and Actel since as a developer I get > their full design software for free (o; > Finally received the NIOS2 5.0 upgrade today (o; Thanx to Jesse from Altera (o; rickArticle: 85699
You may want to bring your gated clock to an IO pin and back into a GCLK pin. dbrown "neu" <markuer@hotmail.com> wrote in message news:ee8edfa.7@webx.sUN8CHnE... >I use a Spartan 3 and the ISE software. Now that I'm bringing all the >different parts of my project together, I have this problem with the gated >clock. I donīt have a clue how to solve it out. It appears in the "Generate >Programming File" part: WARNING:DesignRules:372 - Netcheck: Gated clock. >Clock net a1_1 is sourced by a combinatorial pin. This is not good design >practice. Use the CE pin to control the loading of data into the flip-flop. >I tried introducing the clock in a flip-flop whith a CE pin and controllin >it, but it was no use. So I donīt use it anymore. It's really weird, cause >I add a memory, it's mapped properly, and this dammed warning pops out. >With this warning the core doesnīt work propperly in the FPGA. My design >clock is 5MHz, so I guess I canīt use the DCM (in case it helped). What can >I do? Would it help if I changed the synthesizer and use, say, Simplicity's >Simplify software? I would be extremely thankful if anyone could help me. I >MEAN IT. Thanks
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