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On 10 Jun 2005 11:11:57 -0700, Eric Smith <eric@brouhaha.com> wrote: >Ray Andraka <ray@andraka.com> writes: >> I'd like something that doesn't sound like a vacuum >> cleaner and heat the room like a space heater this time around too, >> perhaps I need to consider liquid cooling? > >I've been thinking about using a Zalman Reserator fanless watar >cooling kit when I upgrade my machine to an Athlon 64 X2 4400+ >(dual core 2.2 GHz), but I haven't tried it yet so I can't personally >confirm the claims. > > http://www.zalman.co.kr/eng/product/view.asp?idx=63&code=021 > >I've been happy with Zalman's other products, though. I'm using their >CNPS7000B-Cu heatsink/fan on a Athlon 64 3500+, and it does a great >job of keeping the temperature down without much noise. > > http://www.zalman.co.kr/eng/product/view.asp?idx=141&code=005 > >But the X2 uses a lot more power (up to 105W, IIRC), and I suspect that >the Reserator will be able to keep it cooler than the CNPS7000B-Cu >would. > >Zalman recommends distilled water for the Reserator. I wonder whether >it's a good idea to add something to inhibit growth of microorganisms, >like a tiny amount of bleach? If the thing is working properly, the >water won't get hot enough to kill all the critters. > Car anti-freeze? JohnArticle: 85551
"Krist Neot" <Krist_Neot@hotmail.com> writes: > For such LCDs, is the display RAM usually implemented in the LCD panel > or the camera manufacturer implements that in his camera's circuit board? Look at the panel's FPC (Flexible Plastic Connector). There should be a chip bonded to it -- that's the LCDC (Liquid Crystal Display Controller). Anyway, the LCDC generates panel voltages from incoming data. Most panels need something like the following: - Parallel data (6 or 8 bit) - Clock (anything from 500 kHz to 25 MHz) - Supply voltages. These are often suprisingly high, and if you connect them to the wrong pins you've got a dead panel. I work with small LCD panels (actually, I'm busy writing HDL for a LCDC at the moment) and I'll warn you: if you don't have a spec for the device you're quite likely to fry it or break it in other ways (for instance, most LC requires row-by-row voltage inversion to stop it from sticking). When we hook up competitors panels for testing we use a tool for hooking into the FPC to probe the signals being sent to it. It's pretty ridiculously expensive though. HTH, Peter -- E-mail: peter@peter-b.co.uk Website: http://www.peter-b.co.uk v2sw6YShw7ln5pr6ck3ma8u7Lw3+2m0l7CFi6e4+8t4Eb8Aen4g6Pa2Xs5MSr5p4 hackerkey.comArticle: 85552
On Thu, 09 Jun 2005 11:17:34 -0500, calaf_calaf_calaf@yahoo-dot-es.no-spam.invalid (calaf) wrote: >Hi all, I am new in this forum, and I have not found a question as the >stated below. Sorry if it has already done. I have been designing >with Spartan-3 and as a consequence of the number of different power >suply and the pinout distribution on the board it is impossible to me >to have a very reduced number of pcb layers. Allowing for simetries >between powers and gnd layers on the stack I almost can't decrease >from ten. Is there any idea I am missing? maybe as 2.5 V is only >used in configuration I can create islands on the 3.3V layer and >share the ground layer return between both power supply? >I think there must be something else that allow me to work effitienly >wilt fewer layers. >Thanks in advance I did an S2E in the FG456 package in 8 layers, 6 mil design rules in places. The same arrangement would probably work for an S3 with three supplies if you split one of the power planes. The trick of course is to not go nuts with bypass caps. I could post some layer pics to alt.binaries.schematics.electronic if there's demand. JohnArticle: 85553
On Fri, 10 Jun 2005 18:46:51 +0200, "Falk Brunner" <Falk.Brunner@gmx.de> wrote: > >"calaf" <calaf_calaf_calaf@yahoo-dot-es.no-spam.invalid> schrieb im >Newsbeitrag news:jYGdnT7auunXIDTfRVn_vg@giganews.com... > >> problem. Shouldn't a power plane be below or above all the pins of >> the FPGA as it happens with ground planes? > >This is the better solution (if you have the layer available) but split >power planes are OK too. Just be carefull, dont use these as reference >planes for high speed lines, this can bite you. > Why? They're all at AC ground. JohnArticle: 85554
"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> schrieb im Newsbeitrag news:6asja1deqev84jtunnakfmqunqls0k3e57@4ax.com... > >This is the better solution (if you have the layer available) but split > >power planes are OK too. Just be carefull, dont use these as reference > >planes for high speed lines, this can bite you. > > > > Why? They're all at AC ground. Yes, but connected through vias + decoupling caps to "real" ground. It works, but less good than a real ground plane. Regards FalkArticle: 85555
billh40@aol.com wrote: > Ray Andraka wrote: > > Time has come for a computer upgrade (I'm currently using a dual Athlon > > 1.8GHz with 4GB memory and 15000RPM scsi raid array running Win2K, > > matrox dual head video with a pair of 19" monitors), but I haven't kept > > up at all with the computer market. I'm wondering what people are using > > these days for high end designs (for simulation and PAR especially). > > I'd like something that doesn't sound like a vacuum cleaner and heat the > > room like a space heater this time around too, perhaps I need to > > consider liquid cooling? ANy comments would be appreciated. Yes, I > > admit I am being lazy. > > > > I am using a 2.6 GHZ P4 , XP PRO, DELL GX270, 2GB RAM, 7200 RPM IDE. > > It takes 7 hours to PAR for a V6000 at 83% utilization (28,400 slices). > > Bill Howdy Ray and Bill, Config: 3.2 GHz P4, XP Pro, Dell PWS360, 2 GB RAM. Files stored out on a network drive. Results: It takes 3 hours for timing driving MAP + PAR to spit out an LX25 (10.8k slices) design at 91% LUT utilization, using 6.3.3i. 7.1i takes noticably longer if global optimization is turned on. According to http://www.polybus.com/linux_hardware/index.htm and other things I've read, you want as much cache as you can afford. The general agreement also seems to be that Athlon 64's tend to be the fastest things out right now, to make a very sweeping generalization. Have fun, MarcArticle: 85556
Michael, I had a warning like this on the clock signal which is originally routed through the clock pin, but not directly to BUFG, i.e. there was some muxes on the way. I think the explanation is that BUFGP is IBUFG + BUFG, and if there is logic in between, then the placer fails using a template (i.e. BUFGP). May be your design / core has some gated clocks or any other logic associated with clock muxing. Hope this helps. Vladislav. "MM" <mbmsv@yahoo.com> wrote in message news:3gtpr1Feefu1U1@individual.net... >I am getting the following warning on a Virtex-II design: > > WARNING:Route - CLK Net:clk50_BUFGP may have excessive skew because 1 > NON-CLK pins failed to route using a CLK template. > > My question is how can I find the problematic pin? > > A similar question was asked here in the past, but the discussion slipped > into design practices. My design is pretty big and the biggest part of it > is > third party core, for which I don't have source code. So, I need to figure > out what exactly causes this warning... > > Thanks, > /Mikhail > >Article: 85557
"Ray Andraka" <ray@andraka.com> wrote in message news:HFiqe.559$FP2.71@lakeread03... > Time has come for a computer upgrade (I'm currently using a dual Athlon > 1.8GHz with 4GB memory and 15000RPM scsi raid array running Win2K, matrox > dual head video with a pair of 19" monitors), but I haven't kept up at all > with the computer market. I'm wondering what people are using these days > for high end designs (for simulation and PAR especially). I'd like > something that doesn't sound like a vacuum cleaner and heat the room like > a space heater this time around too, perhaps I need to consider liquid > cooling? ANy comments would be appreciated. Yes, I admit I am being > lazy. > The new Opterons actually have relatively low power dissipation requirements. You may want to consider 2 of the Opteron 252s (single core 90nm devices) as they have fastest clock speed and lowest power consumption requirements. Here are some benchmarks of the new Opterons: http://www.gamepc.com/labs/view_content.asp?id=opteron275&page=1 Daniel LangArticle: 85558
Falk Brunner wrote: >>IIRC the "official" escape pattern for FT256 is 6/6 and uses top & >>botton layer only. > > > I doubt it. For a BGA fanout, you need n/2-1 signal layers, where n is the > number of rows/columns (assuming you have a complete ball grid without space > in the center. So for a 16x16 (FG256) you need 7 signal layers. To our > advantage, the inner balls are just VCC/GND, so you get away with 4 signal > layers. Take a look at http://www.xilinx.com/bvdocs/appnotes/xapp157.pdf For the FG256 they only show two signal layers. SylvainArticle: 85559
Falk Brunner wrote: > "dlharmon" <harmon.darrell@gmail.com> schrieb im Newsbeitrag > news:1118373181.586925.297720@f14g2000cwb.googlegroups.com... > > > I have laid out my first board using the FT256. I have not had it > > fabricated yet. It is 4 layers 6/6mil track/space. The real killer was > > the size of the vias. I used 1 solid groundplane and planelets for > > ??? How is it possible to fanout the balls on just 2 signal layers (1 layer > is "lost" for Ground, the other for VCC)? Or do you mean a 6 layer board > (which leaves 4 layers for signals)? > > Regards > Falk It isn't. I just used about 120 of the 171 IO. I used a solid ground plane and another plane for power. The first 2 rows were brought out on top and a few IO were brought out on the bottom. Darrell HarmonArticle: 85560
calaf wrote: > > As far I can gather I find some issues: There are some disposition of > vias on the 2.5V planelet that reduce significatively the path's > width for currents (and therefore it raises the impedance. I have > found quite interesting the method used to take the 3.3V to the VCCO > pins but I wonder whether a trace (instead of a plane is not a > problem. Shouldn't a power plane be below or above all the pins of > the FPGA as it happens with ground planes? Thanks for the tip. I took out a few vias and enlarged the 2.5V planelet. It is fairly solid now. Unfortunately the clearance around the via is the minimum allowed by the PCB maker (PCBTrain). The 3.3V IO does not really have a plane, but has an 0402 cap between the ground plane at each via. All of the IO are 3.3V LVCMOS. I am going to go ahead and build it. It has to be better than the alternative (PQ208). Darrell HarmonArticle: 85561
"Symon" <symon_brewer@hotmail.com> wrote in message news:42a9de59_3@x-privat.org... > "calaf" <calaf_calaf_calaf@yahoo-dot-es.no-spam.invalid> wrote in message > news:jYGdnT7auunXIDTfRVn_vg@giganews.com... > > > As far I can gather I find some issues: There are some disposition of > > vias on the 2.5V planelet that reduce significatively the path's > > width for currents (and therefore it raises the impedance. > > > The vias are plated through. With metal. Like Khan, you're thinking too two > dimensionally. Think like Mr. Spock. > Doh, I was looking at the wrong bit. Shouldn't've gone drinking on a school night yesterday! Syms.Article: 85562
Hi Ray, > Time has come for a computer upgrade (I'm currently using a dual Athlon > 1.8GHz with 4GB memory and 15000RPM scsi raid array running Win2K, > matrox dual head video with a pair of 19" monitors), but I haven't kept > up at all with the computer market. I'm wondering what people are using > these days for high end designs (for simulation and PAR especially). > I'd like something that doesn't sound like a vacuum cleaner and heat the > room like a space heater this time around too, perhaps I need to > consider liquid cooling? ANy comments would be appreciated. I personally use an Athlon XP 3200 with 2GB and plain old parallel IDE disks - I don't think that RAID performance helps me with P&R that much. Mind you, so far I've worked on designs up to the 20K1500E and the 2S60 - I guess I'd need a bit more when designing for something bigger. Take a look at http:// www.alienware.com and look up the Aurora ALX. Dress it up as you go, but do use the Athlon 64 X2 4800+ CPU, 2G of memory, and even though it's liquid-cooled, it may be a good idea to add the noise dampener stuff as well. Alienware PCs are fast and reliable, and even though they're designed for gamers, they should do a good job running Modelsim and PAR as well. Also, I must say that they have sublime taste in casing - which after all does matter since you'll be seeing that thing under your desk for the next few years. As to the OS - it's completely up to you. I'm a Linux fan, and the whole Altera kit runs at the same speed under Linux as under W2K, with Modelsim running around 10% faster than under Windows. SOPC Builder is faster by a (subjective) factor 2 under Linux. I haven't tried webpack under Linux yet - so much to do, so little time... Just my $.02 Best regards, BenArticle: 85563
"Gabor" <gabor@alacron.com> wrote in message news:1118417613.834535.32380@g43g2000cwa.googlegroups.com... >> A master has to support clock stretching to be I2C compliant. Yes. >> Clock stretching is used by slaves that need time to process data. >> If a slave doesn't need the extra time, it doesn't need to stretch the >> clock and can maintain I2C compliance without clock stretching. True. The key point is that clock stretching allows any master to work with any slave. Omitting it inserts an Achilles heel in the design. It is really irritating when people publish interfaces with such flaws. Even more so when the authors acknowledge the flaw and then waffle their excuses for not doing it the way it ought to work. > A lot of IC's with I2C slaves show the SCL pin as > an input-only. The Xilinx app assumes you're getting data from > inside the FPGA which should never require stretching even at > the fastest bit rates. If the slave runs fast enough it never needs to stretch the clock. But the master always have to cope with clock stretching. > A clock stretcher usually only asserts SCL during the ACK cycle of > the access requiring more time. This is not a requirement, but it > keeps a slave from stretching SCL cycles that are not intended for > that slave, as might happen if the address is still being sent. IIRC any slave should be able to stretch the clock at any bit. For example, and extremely slow slave might need to slow do the address bit rate in order to read all the bits. It doesn't matter if the address is for it or not, it still needs its own time to read it. > Also make sure that the decision to stretch or not stretch does not > come more than Tlow (min) after the falling edge of SCL or you may > have a race condition allowing the SCL to "double pulse". It's > probably best to synchronize the start of the stretch pulse to the > falling edge of SCL. I thought a good way to clock stretch is to have a gated 3s buffer with the in and out both wired to SCL. Like a 74LS125 (IIRC). With the enable negated, it acts as if it were not there. With the enable asserted, it is 'armed': when the SCL line goes low, the gate locks it low (for the slave to take its own sweet time to note it). The slave then negates the enable to allow SCL to float.Article: 85564
http://www.menie.org/georges/embedded/#xmodem Petter Gustad wrote: > > I want do download some date into my FPGA over a serial line. It would > be great to do so using xmodem or kermit. However, the source code > I've found (Omen and Columbia U) seem to be based upon a file system > or assume a POSIX OS. > > Are there any simple public domain xmodem or kermit implementations > which will simply store the received data in a buffer out there? > > Petter > -- > A: Because it messes up the order in which people normally read text. > Q: Why is top-posting such a bad thing? > A: Top-posting. > Q: What is the most annoying thing on usenet and in e-mail?Article: 85565
Hi Ray, I use the following heatsinks: http://www.sidewindercomputers.com/swmcforinxe.html I use this on a 3.x GHz P4 dual system, and they work great. I got a super quiet $5 fan with it, and no problems. I use this case: http://www.antec.com/us/productDetails.php?ProdID=15001 and it comes with two very very quiet fans. The biggest feature of it is the way the disk drives mount and are easily removeable. It comes with a four carrier drive bay that allows access out the side. You may not like the neon blue lights, or the clear sides, but ignore them...it's a really nice case. Has front USB ports as well. I also use this power supply: http://www.antec.com/us/productDetails.php?ProdID=20551 which is sufficiently quiet. As far as motherboard and memory goes, well, they really don't make much noise, so I believe any of your liking that fit this case will do, and I'd also recommend one that has at least a PCI-Express 16x video slot, if not also a 4x and a few PCI slots. Regards, Austin "Ray Andraka" <ray@andraka.com> wrote in message news:HFiqe.559$FP2.71@lakeread03... > Time has come for a computer upgrade (I'm currently using a dual Athlon > 1.8GHz with 4GB memory and 15000RPM scsi raid array running Win2K, > matrox dual head video with a pair of 19" monitors), but I haven't kept > up at all with the computer market. I'm wondering what people are using > these days for high end designs (for simulation and PAR especially). > I'd like something that doesn't sound like a vacuum cleaner and heat the > room like a space heater this time around too, perhaps I need to > consider liquid cooling? ANy comments would be appreciated. Yes, I > admit I am being lazy. > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 85566
Hi, Here you are for 'carry adder' key word in all patents title field: PAT. NO. Title 1 5,045,681 Optoelectric ripple carry adder 2 4,931,981 Multi-place ripple-carry adder 3 4,899,305 Manchester carry adder circuit 4 4,839,849 Ripple-carry adder 5 4,704,701 Conditional carry adder for a multibit digital computer 6 4,675,838 Conditional-carry adder for multibit digital computer 7 4,660,165 Pyramid carry adder circuitArticle: 85567
Some years ago, a XILINX project was "Designed by Jens Hildebrandt, University of Rostock/Germany, 2002", as it says. The purpose of this piece of work was to enable one, by means of a CPLD, to program a FLASH memory via an ASYNC serial link, and, after changing the state of RTS, to use that FLASH memory to provide the bitstream and controls to program a XILINX FPGA. Unfortunately, the portion of this that I received did not specify anything about the external interface. Has anyone had experience with this project, to the extent that it's been implemented? If so, can you advise me as to how this scheme can be implemented in hardware? thanks in advanceArticle: 85568
I am well impressed with the Athlons we run. I am looking at the new X2s when they really become available in a couple of weeks. For a single thread type application like most of the current tools the Athlon FX55 would probably do slightly better but having something in reserve on a dual is great to have. The Intel equivalents in the main run hotter and need louder, or more sophisticated, cooling. In a couple of years I expect software to make better use of dual processors given the number of single chip dual cores coming into the mainstream market. I would suspect your disk drives are a good part of your noise. Our RAID arrays make a reasonable racket. If you move to IDE arrays your will probably suffer some performance drop but you should be able to find some less noisy disk drives to take your noise down. If your monitors are CRT then go LCD. CRTs would probably contribute a several hundred watts to your room heating our CRT pairs certainly do. We are also run LCD pairs and these are very impressive and all new monitors we buy will be LCD. If you run XP and are really desperate consider running a remote desktop. Put the noise powerful machine in a suitably remote place and use a second low power, low noise, machine as your display machine. You can do similar things with Linux etc too but I am no expect on their implementations and limitations of running remote shells. Other practical things we do is to use full tower cases and put them under desks or behind noise baffles. Does not get rid of the heat but the perceived noise goes down. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "Ray Andraka" <ray@andraka.com> wrote in message news:HFiqe.559$FP2.71@lakeread03... > Time has come for a computer upgrade (I'm currently using a dual Athlon > 1.8GHz with 4GB memory and 15000RPM scsi raid array running Win2K, matrox > dual head video with a pair of 19" monitors), but I haven't kept up at all > with the computer market. I'm wondering what people are using these days > for high end designs (for simulation and PAR especially). I'd like > something that doesn't sound like a vacuum cleaner and heat the room like > a space heater this time around too, perhaps I need to consider liquid > cooling? ANy comments would be appreciated. Yes, I admit I am being > lazy. > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com http://www.andraka.com > "They that give up essential liberty to obtain a little temporary safety > deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 85569
On Fri, 10 Jun 2005 22:04:01 +0200, "Falk Brunner" <Falk.Brunner@gmx.de> wrote: > >"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> schrieb im >Newsbeitrag news:6asja1deqev84jtunnakfmqunqls0k3e57@4ax.com... > >> >This is the better solution (if you have the layer available) but split >> >power planes are OK too. Just be carefull, dont use these as reference >> >planes for high speed lines, this can bite you. >> > >> >> Why? They're all at AC ground. > >Yes, but connected through vias + decoupling caps to "real" ground. It >works, but less good than a real ground plane. > They're also connected by the parallel plane capacitance, which is typically pretty hefty when the dielectrics are properly thin. If you don't trust power planes for the "return current" you'll need a lot more ground planes, hence more layers. I do stuff with jitters in the low single digits of ps, and use microstrip traces referenced to power planes all the time. I blame Johnson for all this obsession with "return currents." JohnArticle: 85570
Bob Perlman wrote:
>I've just upgraded to a 3GHz Prescott Pentium 4 system. Prior to this
>I'd used dual-processor systems, but the hyperthreading feature seems
>to let me run small stuff painlessly while a simulation or route is
>running. And speed is good, too.
>
>Sad to say, it doesn't meet your "no space heater" criterion. The
>Prescott CPUs run very, very hot.
>
>Bob Perlman
>Cambrian Design Works
>
>
>
Hmm, water cooling might let me put a radiator in another room.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 85571Stephane, Can you give a digital example on the median value algorithm or any references to its original paper. Thank you. WengArticle: 85572
John Adair wrote: > > If you run XP and are really desperate consider running a remote desktop. I'll second that. In fact, I neglected to mention in my other post that the system that I described is nowhere near me. It's in the server room and I control it via XP's Remote Desktop. In fact, I have three Remote Desktop sessions open to different Windows XP boxes doing FPGA builds this very moment. Screen refresh is as if you were sitting in front of the machine - good enough to use Model Sim. Standard VNC doesn't even come close, especially when connecting from home via VPN. > Put the noise powerful machine in a suitably remote place and use a second > low power, low noise, machine as your display machine. You can do similar > things with Linux etc too but I am no expect on their implementations and > limitations of running remote shells. Other practical things we do is to use > full tower cases and put them under desks or behind noise baffles. Does not > get rid of the heat but the perceived noise goes down. Has anyone done any ISE runtime comparisons between Linux and Windows on similar or identical machines? MarcArticle: 85573
In article <HFiqe.559$FP2.71@lakeread03>, Ray Andraka <ray@andraka.com> wrote: >Time has come for a computer upgrade (I'm currently using a dual Athlon >1.8GHz with 4GB memory and 15000RPM scsi raid array running Win2K, >matrox dual head video with a pair of 19" monitors), but I haven't kept >up at all with the computer market. I'm wondering what people are using >these days for high end designs (for simulation and PAR especially). >I'd like something that doesn't sound like a vacuum cleaner and heat the >room like a space heater this time around too, perhaps I need to >consider liquid cooling? ANy comments would be appreciated. Yes, I >admit I am being lazy. Performance and not sounding like a vaccume cleaner are going to be exclusive, you can't do both. However, a suggestion: Make sure the computer has DVI output, run a 12' DVI cable, and a long USB cable, and put the space heater in a closet on the OTHER side of your office, or down in the basement, etc. The other option, as mentioned, is remote desktop. But (big but), putting graphics through the net frankly, uhh, blows. In terms of architecture, a dual processor Athlon 64 would probably be better than the dual processor P4: The AMDs have lower memory latency, and the dual processor system will have 2x the memory bandwidth of a 1 processor system (thanks to the NUMA-ish architecture). One other option would be a small form factor Shuttle system. It won't be as good on P&R as its only single processor, but it will be quite WHEN you aren't doing P&R. -- Nicholas C. Weaver. to reply email to "nweaver" at the domain icsi.berkeley.eduArticle: 85574
In article <ngrja1ll0gd4e0f2cmlgcenhvgjrdb4jn8@4ax.com>, John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote: >Car anti-freeze? Nah. Use water-wetter. It's an anticorrosion agent without the ethylene glycol: http://www.redlineoil.com/products_coolant.asp -- Nicholas C. Weaver. to reply email to "nweaver" at the domain icsi.berkeley.edu
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