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Has anyone tried the Actel ProASIC3 Starter Kit? What is the cost of this unit? From the documentation, the chip claims to be able to run from an external 350MHz clock (and it appears the internal PLLs can generate a 350MHz clock from an external source) but the system says it can only do about 150MHz internal? Is this correct? Are there other companies making flash-based FPGAs? Is there a better Starter Kit value available somewhere that anyone knows about? Thanks. DaveArticle: 85401
You have two independent access mechanism, but only one 18Kb storage area. If you want two separate single-portRAMs, you must assure that the two ports never overlap into the storage area. The simplest way is to tie one address bit in one port High, and the SAME addresss bit on the other port low. That gives you two independent 9Kb RAMs, but you might also divide less symmetriclly. Once you realize: two completely independent access mechanism, but one common storage area, the rest is obvious. Peter Alfke, Xilinx ApplicationsArticle: 85402
Laurent, do what Steve Knapp suggests in the other thread with the obnoxious title: Order them from your distributor, but append 0974 right after the temperature letter C. That allows the disti to sell you the new parts, made in a 300 mm fab. Steve, with 20 years of Applications experience, and responsible for Spartan Applications, knows what he is talking about. He and I were (almost) as frustrated as you guys about this non-problem that was allowed to mushroom into a real problem. And we rocked the boat. Let's hope for the good solution. Xilinx has no problems whatsoever making these chips by the bucketfull. The problem was in the selling. Weird, isn't it? Peter AlfkeArticle: 85403
Erik Walthinsen wrote: > For the record I have nothing against > Altera, but without Quartus running "easily" in Linux, they're mostly > out of the running otherwise. I plan on actually using Makefiles and > CVS to manage heavily co-dependent C and Verilog, and that gets almost > prohibitively annoying and hard with Windoze. This has little to do with xilinx vs. altera, but if all of your tools for any technology are command-line capable under windows, you can use cygwin to get yourself what is essentially a unix environment with a real shell for scripting and make, gcc, etc. The only real problems I had were that if something crashed I sometimes had to kill it from the windows task manager rather than the shell, and occasionally if I tried to build someone's generic unix package to run locally under cygwin there were some header file problems with different handling of signals or something (cygwin is a unique *nix flavor, it's not precisely the same programming model as linux).Article: 85404
I know we had some problems with Impact (I wasn't directly involved) that were resolved by updating to 6.3. I think we were using a DELL with Windows 2000. Jason "Rehan" <rehanhafiz@gmail-dot-com.no-spam.invalid> wrote in message news:ZvmdnSODrtLBQgDfRVn_vg@giganews.com... > Hi , i am using Xilinx iMPACT (6.1.03i) to detect the JTAG-Parallel > Port Cable on my DELL PC (Windows XP). > But everytime it says "Cable connection failed".I have attached the > error report below. If someone had a smilar problem , > PLZ help me in this issue, Regards > > ================================================ > Connecting to cable (Parallel Port - LPT1). > Checking cable driver. > Installing WinDriver... > File C:\WINDOWS\system32\drivers\windrvr.sys not > found. > File C:/Xilinx/bin/nt/windrvr.sys not found. > Failed. > Service using windrvr.sys : > SYSTEM\CurrentControlSet\Services\WinDriver. > ImagePath = \SystemRoot\System32\drivers\windrvr.sys. > DisplayName = WinDriver. > Start = 2. > ErrorControl = 1. > Type=1. > Cable connection failed. > > ======================== > & even if i copy windrvr.sys to the folder in which it looks for > it , it still > fails. Apparently there is some problem with the Windrvr . I was also > wondering why these files are missing on my computer ???? > > Anyone please help . thanks[/b] > >Article: 85405
"starfire" <starfire151@cableone.net> schrieb im Newsbeitrag news:11afakg1pbsp9a6@corp.supernews.com... > Has anyone tried the Actel ProASIC3 Starter Kit? What is the cost of this > unit? > > From the documentation, the chip claims to be able to run from an external > 350MHz clock (and it appears the internal PLLs can generate a 350MHz clock > from an external source) but the system says it can only do about 150MHz > internal? Is this correct? > > Are there other companies making flash-based FPGAs? Is there a better > Starter Kit value available somewhere that anyone knows about? > > Thanks. > > Dave > are you sure PA3 kit is already available !!?? to my knowledge all PA3 shipments are delayed unitl august september? I do have the PA+ kit but havent done much with it. check out Lattice XP series, they have many advantages over PA3 XP10 starterkits are available silicon also AnttiArticle: 85406
Hi I hope someone has more experience and can give advice - what I need (for urgent customer design) is simple? design with FPGA having high speed video memory (must be implemented with standard cheap devices like DDR) - the constraints are both PCB size and power consumption. The system must support sustained 12bit DDR datastream at 165MHz pixelclock to the DVI encoder. so current consideration is FPGA: V4 + Memory: 2 fully separate DDR chips BGA144, 32 bit physical eg 64 bit per clock edge Q: as the DDR chips are mounted VERY close, all wires less than 0.5 inch? and there is never more than one load on the DDR chips, I am wondering is it safe to not have DDR termination resistors by using DCI in the FPGA and switching the DDR into SSTL1 mode by the extended mode register write? Q: or perhaps there is some other memory solution known, that doesnt require more PCB space and is not much more expensive. ZBTRAMs are in BGA also and there are special video rams, but those are usually way more expensive and/or more exotic. I guess main issues are correct PCB design and decoupling as the DDR chips power consumption is per datasheet 0.8A and the FPGA is running at relativly high frequencies as well. any help/hints appreciated AnttiArticle: 85407
Hi there I would like to design Motion Controller (Single axis) with Xilinx FPGA or CPLD. Please send me if you have design examples or application note. Best regards IH Lee leeih@chollian.netArticle: 85408
Hi Antti, yes you are of course correct : PCB design and decoupling is the main issue. If possible, simulate your layout. If not possible : follow standard design practice (correct layer-stackup to start with, impedance matched lines,etc...) and you should be safe. I have a design with V4 and 6 DDR2 memories running at 200 MHz, the longest traces are about 2 inches. DDR2 has the possibility of internal termination, V4 has DCI. I disabled DCI on the DQ bus (so only DCI on the strobes are enabled) because of power consumption and the memory-interface still works => DQ bus shows some moderate under/overshoot, but still nothing worrying. Oh and by the way : I also use it as video-memory. hope this helps... Bart De ZwaefArticle: 85409
"Leeinhyuk" <engtech1@kornet.net> schrieb im Newsbeitrag news:d88ndk$eqp$1@news2.kornet.net... > Hi there > I would like to design Motion Controller (Single axis) with Xilinx FPGA or > CPLD. > Please send me if you have design examples or application note. > Best regards > IH Lee > leeih@chollian.net > > http://www.mesanet.com/ grab in the zip archives there is motion controller with specially designed small dsp core all hdl sources also :) anttiArticle: 85410
"zeeman_be" <zeemanbe@gmail.com> schrieb im Newsbeitrag news:1118301206.943537.97030@g43g2000cwa.googlegroups.com... > Hi Antti, > > yes you are of course correct : PCB design and decoupling is the main > issue. If possible, simulate your layout. If not possible : follow > standard design practice (correct layer-stackup to start with, > impedance matched lines,etc...) and you should be safe. I have a design > with V4 and 6 DDR2 memories running at 200 MHz, the longest traces are > about 2 inches. DDR2 has the possibility of internal termination, V4 > has DCI. I disabled DCI on the DQ bus (so only DCI on the strobes are > enabled) because of power consumption and the memory-interface still > works => DQ bus shows some moderate under/overshoot, but still nothing > worrying. Oh and by the way : I also use it as video-memory. > > hope this helps... > > Bart De Zwaef > thanks! DDR2 looks better, just need to find a chipd with 32 bit wide bus, micron has only x16 chips available :( anttiArticle: 85411
Hi Dave, As mentioned before on this newsgroup, the only way to find out what kind of performance you can achieve is to do a synth and place&route run. In addition to that you need to look at the architecture and if required adjust your design accordingly. I have a simple AES core on my website which I synthesised for an A3PE600 to just get an fmax value, however, I didn't appreciate that the ProASIC3 doesn't support any internal ROMs (i.e. preloaded memory cells) and thus ended up was a long chain of C-cells (see http://www.ht-lab.com/freecores/AES/aes.html). After changing the design to use synchronous embedded SRAMs the fmax increased to a respectable value :-) One thing I really like about Actel is that they give excellent support (at least here in the UK). If I were you I would invite one of the FAE to visit you to discuss your requirements, Hans. "starfire" <starfire151@cableone.net> wrote in message news:11afakg1pbsp9a6@corp.supernews.com... > Has anyone tried the Actel ProASIC3 Starter Kit? What is the cost of this > unit? > > From the documentation, the chip claims to be able to run from an external > 350MHz clock (and it appears the internal PLLs can generate a 350MHz clock > from an external source) but the system says it can only do about 150MHz > internal? Is this correct? > > Are there other companies making flash-based FPGAs? Is there a better > Starter Kit value available somewhere that anyone knows about? > > Thanks. > > Dave > >Article: 85412
On Wed, 08 Jun 2005 14:48:43 -0700, Austin Lesea <austin@xilinx.com> wrote: >Erik, > >What is vcolo.com doing with FPGAs? Looks like you re-sell computer >resources virtually? > >See below, > >Austin > >Erik Walthinsen wrote: > >> Austin Lesea wrote: >> >>>> The parts are not discontinued. Digikey carries them, and we still >>>> sell them. And, we still make them, too. We use our website to >>>> showcase the new products, not the old ones. >> >> Then why, when I try to search for various part numbers found on Digikey >> on Xilinx's site do I get no useful results? (specifically anything >> under ~$50 as appropriate for my projects) For the sole reason that ISE >> runs on Linux I would prefer to use Xilinx parts. But when Digikey is >> the only way to get any parts in small quantity, and I can't even >> determine if the parts they actually do sell have a hope of handling my >> project, I start looking at putting up with Windoze and Quartus (better >> interface than ISE anyway, from my limited experience) and going with >> Altera parts. >> >> Not to mention that all the parts on Digikey are afaict ludirously >> expensive for their capbilities, because they are built with such old >> processes. >> >> Can some give an explanation as to why Digikey does not even offer the >> newer parts in the first place? I gather there are apparently problems >> producing the chips in sufficient quantity, but that's never stopped >> Digikey from at least listing a part as non-stock before. > >All parts are in stock here at the factory (I checked). That a >distributor doesn't order them is of course troubling, and another >issue. That Digikey doesn't carry the latest and greatest products may >be because they offer little to no support. We prefer our distributors >to earn their percentages (that they make on the parts). > >Other distributors do not want to be undersold by someone who offers no >services (and we don't see any benefit in that either). > >If all you need are some samples, you should develop a better >relationship with your local X distributor or X representative. Much of the discussion recently on availability seems to be from people who will only ever want small quantities - distributors tend not to be interested in such customers.... As Xilinx already has a web-shop set up, it seems that this would be the ideal way to make small quantities available.Article: 85413
> Hi Patrick, > > > I've got a big problem with a Altera Stratix Kit EP1S25. > > Is that the DSP kit or the NIOS kit? I've heard about problems with some of > the newer DSP kits where the manufacturer stuck on different Flash chips > than the old one. > Best regards, > Ben It's the DSP Kit Stratix... Effectively, we had the problem that there is now new Flash memory and we have needed to reprogram the MAX Altera, because with the news Flash Memory it was impossible to program it..Article: 85414
Hi Mr.Alfke, Could 2 single-port RAM be accessed at the same time? Best regards, DavyArticle: 85415
"Philip Freidin" <philip@fliptronics.com> wrote in message news:qofea1t6uhm5v2qor2ca5s5kr7kk357ton@4ax.com... > On Wed, 8 Jun 2005 16:13:01 +0200, "Marco" <marcotoschi_no_spam@email.it> > wrote: >>Hallo, >>I would buy a ip core. What does it means: "Available under the terms of >>the SignOnce IP License" ??? >> >>Thanks >>Marco > > Google is your friend, why didn't you ask google? > > Here is a link that explains "SignOnce IP License": > > http://www.xilinx.com/ipcenter/signonce.htm > > > > > Philip > Philip Freidin > Fliptronics Before opening the thread I read the link you told, but because of my little english acquaintance, I didn't apperar too much clear. I understood in what way to join the consortium, but I didn't understand the condition to buy ip cores. Thanks MarcoArticle: 85416
Hi Davy, > Could 2 single-port RAM be accessed at the same time? short answer: yes - as Peter already explained: >> two completely independent access mechanism, [...] JochenArticle: 85417
Davy, Just to complemenmt what Peter and Jochen said, as you go simulating your memory, remember that write and read to the same address entry will give you unknown values. you will have to bypass this. Vladislav "Davy" <zhushenli@gmail.com> wrote in message news:1118280314.768895.81260@z14g2000cwz.googlegroups.com... > Hi all, > > I use Xilinx Vertex2 FPGA. Can I use a 18k ram as 2 single-port ram? > > Best regards, > Davy >Article: 85418
Tried weeks ago contacting Lattice without any response so far... Besides the DQS/data bit groups per bank...are all other signals free to choose where to connect to? How about differential clock signals? thanx in advance rickArticle: 85419
Hi Davy, just to let you know that i did exactly the same thing recently. I split the Dual Port Rams into 2 with independent access control. The simulation was perfect. Try it ...its quite simple when you think about it. Good Luck, Adarsh "Davy" <zhushenli@gmail.com> wrote in message news:1118311830.368908.11780@g14g2000cwa.googlegroups.com... > Hi Mr.Alfke, > > Could 2 single-port RAM be accessed at the same time? > > Best regards, > Davy >Article: 85420
Hi all, I have been having problems with the EKD 7.1 and the ML40x reference design for quite some time now. ISE/EDK 7.1 cannot meet the timing constraints on that design. I would really appreciate if anyone would post a solution to this problem? Thanks, PeterArticle: 85421
Hi all, Is there any tools to convert Matlab M-language to HDL? Thanks! Best regards, DavyArticle: 85422
I've submitted a request to our local sales rep asking for pricing and availability but have not heard back yet. I will check into the Lattice parts. Thnaks for the heads-up. I have used the Actel Axcelerator parts in previous designs and like the way the PLLs work. The parts are fairly fast, also. The idea of a flash-based part is very nice, though. It sure beats throwing those expensive anti-fuse units away after every change. Dave "Antti Lukats" <antti@openchip.org> wrote in message news:d88io9$59m$03$1@news.t-online.com... > "starfire" <starfire151@cableone.net> schrieb im Newsbeitrag > news:11afakg1pbsp9a6@corp.supernews.com... >> Has anyone tried the Actel ProASIC3 Starter Kit? What is the cost of >> this >> unit? >> >> From the documentation, the chip claims to be able to run from an >> external >> 350MHz clock (and it appears the internal PLLs can generate a 350MHz >> clock >> from an external source) but the system says it can only do about 150MHz >> internal? Is this correct? >> >> Are there other companies making flash-based FPGAs? Is there a better >> Starter Kit value available somewhere that anyone knows about? >> >> Thanks. >> >> Dave >> > > are you sure PA3 kit is already available !!?? > to my knowledge all PA3 shipments are delayed unitl august september? > I do have the PA+ kit but havent done much with it. > > check out Lattice XP series, they have many advantages over PA3 > XP10 starterkits are available silicon also > > Antti > >Article: 85423
Vladislav, what you wrote is correct, but totally irrelevant to this thread. Once you divide the memory into two, you can do anything you want in the two memories. The problem you mention only occurs when you do NOT separate the memory between the two ports. Peter AlfkeArticle: 85424
Hi Falk, What temperature/voltage did you get these results at? At 85 C and 1.14 volts I'm getting just over 4 ns in an XC3S50-4 Paul Falk Brunner wrote: > "Paul Smith" <ptsmith@nospam.indiana.edu> schrieb im Newsbeitrag > news:d84q4e$uga$1@rainier.uits.indiana.edu... > > >>I need to add a pair of 8 bit (unsigned) integers to get a 9 bit >>(unsigned) result at 250 MHz, preferably in an XC3S50-4. >> >>Using the Coregen adder/subtractor V7 with maximum pipelining (9) and >>RPM on, the best cycle time I can get is 4.55 ns. At each pipeline >>level the critical path is a LUT, a MUXCY, and another LUT. > > > Hmm, strange. a 8 bit adder should fit into one level of logic. make sure > both inputs are registered and placed correctly (close to the carry chain). > The output should be registerd too, of course ;-) > > OK, I did a quick test using Webpack 7.1. > > A plain description reaches 3.995 ns, uhhh tight timing ;-) > Looking at the floorplanner (after P&R) I see the mess.The registers for my > inputs are placed inside the IOBs. Not bad in general, but bad here, where > we need every fraction of a ns. So I disable the option for placing the > registers into the IOBs and run again. > BINGO! 3.5ns. > > But the automatic P&R tools are lazy bastards. A look at the floorplanner > reveals, that the input registers are spread over the chip. OK, handmade is > handmade. We add some LOCs into the UCF. New run. > 3.49 ns. Hmm, not too much improvement, but since the placement is fixed > this should be reliable. > See the files below. > > Njoy. > Falk
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