Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
> Well, with a lot of screwing around, I managed to get what I needed.
> Veteran developers, please observe the barf bag located in the seat-back
> in front of you:
>
> always @(posedge clk) begin
> if (prev_lrclk != lrclk)
> int_strobe = 1'b1;
> else
> int_strobe = 1'b0;
> prev_lrclk = lrclk;
> end
A small tip, use non-blocking assignments:
always @(posedge clk) begin
if (prev_lrclk != lrclk)
int_strobe <= 1'b1;
else
int_strobe <= 1'b0;
prev_lrclk <= lrclk;
end
A google search should tell you why.
Cheers,
Jon
Article: 76301Uzytkownik "Guenter Dannoritzer" <dan_nospam_noritzer@web.de> napisal w wiadomosci news:coggir$g8a$00$1@news.t-online.com... > Hi, > > I have a design where a Spartan XL was replaced by a Spartan 3. The FPGA > is configured by an ATmega MCU which loads the configuration file into the > FPGA. This procedure works fine with the old board and the Spartan XL, but > with the Spartan 3 I have the trouble that I never get the DONE signal, > after the configuration is done. > > I see data going over the DIN line into the Spartan 3 and an active clock > signal. As I did not change anything on the ATmega software this should be > fine. > > I generated the binary for the Spartan 3 and enabled the setting for > "Drive DONE Pin High", to have the DONE signal being driven. > > As the ATmega uses 3.3V the Spartan is used in the 3.3V compatibility mode > for configuration. I am just not sure about the VCCO_4 signal, as the data > sheet is for my understanding a bit confusing. In the design that I am > using it is tied to 3.3V. Is that correct or does it need to be connected > to 2.5V during configuration? > > Is there anything else I need to consider with the serial slave mode when > switching from Spartan XL to Spartan 3? see if CCLK is present when the last byte was sent to fpga. krzysiekArticle: 76302
Hello! From the Virtex 4 documentation (Configuration Guide, Users Guide) I learned that this family can be configured during runtime in the granularity of single frames. The frames which have a fixed size for all members of this family. Additionally the documents state that there is a tiled placement of those frames. For Virtex II the frames started at the topmost CLB and ended at the bottom of the FPGA. This does not seem to be the case with Virtex 4 devices. This brings me to the question if it is now possible to configure a part of the FPGA which looks like e.g. a rectangle consisting of whole frames. Having neighbour frames at all four sides of that rectangle which are operating during that reconfiguration process. I'm having a picture of a matrix-style arrangement of all the frames in mind where I can select a set of them which are to be reconfigured. Unfortunately I didn't find any figure in the docs which gives me a hint on that. Could anyone comment on this? Greetings, AndreasArticle: 76303
Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> wrote in message news:<2tonq01dcsg3dogiuckpn60pnhba2h00b2@4ax.com>... > On 29 Nov 2004 12:56:51 -0800, gabor@alacron.com (Gabor Szakacs) > wrote: > > >RobertP <r_p_u_d_l_i_k@poczta.onet.pl> wrote in message news:<coesj1$c50$1@news.onet.pl>... > >> For Virtex II: > >> > >> Vbatt - in some places in the datasheet and user manual it is advised to > >> leave it open if not used, in other it is advised to connect it to Vaux > >> or to ground. Maybe someone knows what is the right way to go? > >> (in previous project I left it open, no problems noticed). > > > >I've left these unconnected in multiple designs - no problems. > > Earlier versions of the datasheet indicated that Vbatt could be left > open. The most recent version indicates that Vbatt should be > connected to gnd or vccaux. Presumably this change was made to fix > some problem. > The version currently on the web (ds031 v3.3) has this note on page 39: Notes: 1. If battery is not used, do not connect VBATT. What "most recent" version of the datasheet do you have? > Regards, > AllanArticle: 76304
Hello, I think that you first must clarify whether you need FPGA or CPLD, which differe in the concept, capacity, routing resources, and price. CPLD gives your design more security (does not need external EEPROM) and guaranteed timing (important for high-speed designs), whereas FPGA provides more capacity but less security and non-guaranteed timing. For CPLD, I always go with Lattice M4000 series, providing excellent fitting/re-fitting resources and capacity. I would not claim on the CPLDs from other manufacturers since I missed the comparison tracking since '98, however I would definately recommend to consider Lattice (BTW, they have free design tools). For FPGA, I go with Xilinx due to a historical issue, however I believe that there is actually a smoall difference with Altera FPGA. -- Regards, Pavel "Johnson" <gpsabove@yahoo.com> wrote in message news:b1ac2406.0411291426.2b7e0d4a@posting.google.com... > Hi there, > > Could anybody please let me know what is the approximate price of the > lowest-cost FPGA or CPLD with about 20K Lggic Cells, or even less? The > quantum will be around 10K per year. We will start a very simple > application, and I hope I can find some FPGA less than $5. > > Thanks in advance. > > JohnsonArticle: 76305
Krzysztof Szczepanski wrote: [snip] > > > see if CCLK is present when the last byte was sent to fpga. > > krzysiek > > Do I have to add some CCLK cycles after I have sent the last data? I recognized there are a bunch of new settings in the ISE6.3 in comparison to the 4.1 which I used for the Spartan XL. The ATmega code applies the data, creates a rising edge for the CCLK and in the next loop toggles the CCLK. I have to check whether there is a falling edge after the last data bit is applied, at least it has a rising edge. The same code worked fine with the Spartan XL. Is there a differenc with the Spartan 3? GuenterArticle: 76306
Jan, Yes, I blew it. "About a 3S1000 to get close to 20K logic cells (has 17,280)" is one response I already got last night from a friend. Sorry to have mixed the gates thing. Something that I, too, don't like about how we count. I much prefer just counting look up tables and flip flops (at least that way I am less confused that normal). Austin Jan Gray wrote: > "Austin Lesea" <austin@xilinx.com> wrote > >>XC3S50 == 50K logic cells. > > > You presumably misspoke, here 50K = 50,000 system gates (a.k.a. marketing > gates, dog gates, what have you). > > An XC3S50 contains 768 slices, or 1536 4-LUTs and FFs, or 1728 logic cells > by that curious derating understood and beloved (and believed) only by > Xilinx marketing. The rest of us just giggle. See also > http://www.fpgacpu.org/#021129 and its links. > > The smallest 3S device with ~20K LCs is an XC3S1500 (26,624 LUTs+FFs, 29952 > "LC"s). The 3S1000 is close (15360 LUTs+FFs, 17280 "LC"s). > > To my knowledge, nothing has been announced that provides 20 KLUTs for $5 in > any quantity. (Not to mention the configuration memory.) I think the > closest announced EasyPath device is something like ~$13(?) for an XCE3S1500 > in quantity with ~$75K(?) NRE. > > But Moore's Law will take us there ere long. Make it your ASIC, indeed! > > Jan Gray > >Article: 76307
All, The question is: what to do with Vbatt if not used? If it is not used, then it really is a 'don't care'. You could float it, connect it to ground, or connect it to a Vcco. But if you let it float, it is a very low leakage pin (obviously, as you do not want to let the battery die from leakage). A very low leakage pin is also a very sensitive pin to ESD damage. So when we tested it for ESD, we decided to change the documentation to say to ground it if not used. If it gets zapped by an ESD discharge, it will have bad leakage. It is most unlikely to cause any other problems, but why take the risk? So, you are correct, in that we are correcting a problem. It is a very small, and very unlikely problem (customer removes part where Vbatt was left floating, Vbatt was zapped with an ESD discharge, and then uses it in an application where Vbatt is used, and the battery ends up running down in less than 25 years). Austin Gabor Szakacs wrote: > Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> wrote in message news:<2tonq01dcsg3dogiuckpn60pnhba2h00b2@4ax.com>... > >>On 29 Nov 2004 12:56:51 -0800, gabor@alacron.com (Gabor Szakacs) >>wrote: >> >> >>>RobertP <r_p_u_d_l_i_k@poczta.onet.pl> wrote in message news:<coesj1$c50$1@news.onet.pl>... >>> >>>>For Virtex II: >>>> >>>>Vbatt - in some places in the datasheet and user manual it is advised to >>>>leave it open if not used, in other it is advised to connect it to Vaux >>>>or to ground. Maybe someone knows what is the right way to go? >>>>(in previous project I left it open, no problems noticed). >>> >>>I've left these unconnected in multiple designs - no problems. >> >>Earlier versions of the datasheet indicated that Vbatt could be left >>open. The most recent version indicates that Vbatt should be >>connected to gnd or vccaux. Presumably this change was made to fix >>some problem. >> > > The version currently on the web (ds031 v3.3) has this note on page 39: > Notes: > 1. If battery is not used, do not connect VBATT. > > What "most recent" version of the datasheet do you have? > > >>Regards, >>AllanArticle: 76308
!!!!!!!????? Yet another clandestine altera.com posting? Who can we trust? In all fairness, what the poster did is against Altera company policy, and he (or she) if caught, will be in 'big trouble' (this from a private communication to me from an Altera VP). I would prefer real customer questions and concerns in this forum, as I know would all of you. Austin ----snip---- >>Message-ID: <ce9c6dd6.0411291119.6cff39c0@posting.google.com> >>References: <cnl7em$9q3$1@hood.uits.indiana.edu> >>NNTP-Posting-Host: 66.35.226.228 <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< >>Content-Type: text/plain; charset=ISO-8859-1 >>Content-Transfer-Encoding: 8bit >>X-Trace: posting.google.com 1101755942 24698 127.0.0.1 (29 Nov 2004 19:19:02 GMT) >>X-Complaints-To: groups-abuse@google.com >>NNTP-Posting-Date: Mon, 29 Nov 2004 19:19:02 +0000 (UTC) >>Xref: newsmst01a.news.prodigy.com comp.arch.fpga:78930 > > > > nslookup 66.35.226.228 > Name: ip66-35-226-228.altera.com > Address: 66.35.226.228 -----endsnip----Article: 76309
Jon Beniston wrote:
> A small tip, use non-blocking assignments:
>
> always @(posedge clk) begin
> if (prev_lrclk != lrclk)
> int_strobe <= 1'b1;
> else
> int_strobe <= 1'b0;
> prev_lrclk <= lrclk;
> end
>
> A google search should tell you why.
Read below what Ian Lang has written on this subject.
-- Mike Treseler
______________________________________________
When must non-blocking assignments be used in RTL code?
Answer: to assign the outputs of any clocked process that is used
synchronously within another clocked process. That's it. Any other usage
is in fact redundant (and to my mind superfluous). In VHDL, it is in
fact impossible not to do this because all communications between
processes have to be by means of signals. This document contends that
that is the only time that non-blocking (or VHDL signal) assignments
should be used. Most designers make much more liberal use of the
non-blocking assignment than strictly necessary. I would argue that this
obfuscates the code in that the real usage is lost amongst the
non-essential uses. The example UART design (RTL.vhd) shows how it is
done. The output readData, for example, is generated thus.
The corollary of this rule is that, synchronous outputs aside, all other
assignments should be non-blocking (Verilog) or use variables (VHDL).
Again, the UART example shows this. It can be seen that the VHDL and
Verilog versions of this design are exactly analogous. In fact, this
style lends itself to being auto-translated between the two languages.
In general, I would advocate only using non-blocking assignments (VHDL
signal assignments) when their special behaviour is actually required.
This is at odds with conventional wisdom but in keeping with a
minimalist approach whereby code that does nothing and behaviour that
isn't required are avoided.
http://www.designabstraction.co.uk/Articles/Advanced%20Synthesis%20Techniques.htm
Article: 76310Andreas, Yes, the configuration is in frames now that cover (I am pretty sure) 16 CLB's in height (if I'm wrong about the height, I am sure someone will throw something at me -- I've switched from being on the DCM team to the config team!). The new FARME_ECC primitive has a 12 bit ECC word as part of the thousand some odd bit long frame, which is written at the time of configuration with the ECC syndrome. If later, an upset occurs, the syndrome will not match, and the offending bit is pointed to by the syndrome (so it can be corrected). Each CLB has 22 frames to configure it. All frames are equivalent as fas as interconnect, but the remaining frames are individualized for the tile they are in. So yes, you may reconfigure any, or part, of the part while it is operating, and the frame boundries form a better "fence." The whole issue of reconfiguring while operating (which we have allowed in all the Virtex parts) is more one of finding the boundaries, than a functional issue (how to not disturb something while changing something else by ripping up and redoing the interconnect). A config bit that was a 1, and is programmed to be a 1 (or the other way around) will not cause a glitch on the resulting resource. For more information, contact your local FAE. Austin Andreas Schallenberg wrote: > Hello! > > From the Virtex 4 documentation (Configuration Guide, > Users Guide) I learned that this family can be > configured during runtime in the granularity of single > frames. The frames which have a fixed size for all > members of this family. > Additionally the documents state that there is a tiled > placement of those frames. > > For Virtex II the frames started at the topmost CLB > and ended at the bottom of the FPGA. This does not > seem to be the case with Virtex 4 devices. > > This brings me to the question if it is now possible > to configure a part of the FPGA which looks like > e.g. a rectangle consisting of whole frames. > Having neighbour frames at all four sides of > that rectangle which are operating during that > reconfiguration process. > > I'm having a picture of a matrix-style arrangement > of all the frames in mind where I can select a set > of them which are to be reconfigured. > Unfortunately I didn't find any figure in the docs > which gives me a hint on that. > > Could anyone comment on this? > > Greetings, > Andreas >Article: 76311
Paolo, As far as I understand, the board comes with the Spartan loaded with the "pass-thru" bit file. This allows the board to be tested/used without plugging it into a PCI slot. So, till you are able to load the bridge program onto the spartan, the board will not be seen by the PC. I have placed an order for a JTAG4 cable, but haven't received it yet. Plan to try it again after i am able to program the spartan. -Sirish "Mindroad" <mindroad@hotmail.com> wrote in message news:41ab6362$0$13480$ba620e4c@news.skynet.be... > System : Win XP (Fresh install) > > Read the user's guide multiple times to ensure correct jumper settings. > The board is configured for SelectMAP programming mode JP8 shunted > The board is configed in master-serial mode for PROM programming of SPARTAN > bridge : JP9 open > Other jumpers have default values, triple checked > > The S1 and S2 dipswitches : > S1 : all on off ... CF card loads position 0 normally > S2 : all on off as described in user guide > > inserted the card into 32bit PCI slot > for normal PCI use at present time > > booted PC > followed driver installation instructions, windriver6.inf installed by => > wdreg -inf "location of inf file" install > then copied avpci...inf file to WINDOWS/INF directory then rebooted. > > Accessed PCI Utility : no board connected > > Tried to manually install the avpci driver, still nothing detected ... > Checked PCI slots, and no extra entries in ID list of device wether or not > the device is connected to the bus > > Has somebody experienced this problem ? > Could it be the PROM not longer contains the config file for the bridge or > should i look for answers in another direction > > Thx in advance, > > Paolo > >Article: 76312
I've got a state machine that periodically enters an "unknown state". It meets all the timing requirements I have set. My debug port indicates an output state inconsistent with any of the states in the state machine and also inconsistent with the assignment for "others". The code below indicates what is going on. with CC2400State select debug_state <= "0001" when RadioReset, "0010" when RadioResetCheck, "0011" when RadioCommand, "0100" when RadioCommandWaitNotDone, "0101" when RadioCommandWait, "0110" when RadioConfig, "0111" when RadioWaitOscStable, "1000" when RadioWaitFSStable, "1001" when RadioReadStatusWait, "1010" when RadioEnablePacketRX, "1011" when RadioReadNumBytes, "1100" when RadioClearFIFO, "1101" when RadioError, "1110" when DelayState, "1111" when others; In the unknown state my debug_state output is "0000". Any ideas? DecoArticle: 76313
After installation of ISE 6.3 there is a new executable in edk/bin/nt: _xps.exe This might work. Or try to invoke XPS_GUI.exe directly. Holger "massoud shakeri" <shakeri@no_spam_please.telus.net> wrote in message news:iTyqd.200226$df2.155920@edtnps89... > Hi All: > I have installed ISE6.3i and EDK 6.2i. When I run "platform studio" it show > the following message: > "$XILINX does not point to an ISE 6.2 installation" > and does not work. > I am wondering if there is any way to have EDK ruuning with ISE 6.3? > Thank you in advance. > Massoud > >Article: 76314
Hello All FPGA Gurus, I want to do some estimation of resources for my design for V2Pros as we will be going into production and we need to decide if we can stick to our current V2P7(which our board designer and my boss would love !!!) or if we should move to V2P20(which i badly want !!!) I know there were some threads related to this earlier but was not able to find them...easily. Could someone give me pointers to them or give general suggestions on the issue ? Thanks to all ! AdarshArticle: 76315
deco wrote: > I've got a state machine that periodically enters an "unknown state". > It meets all the timing requirements I have set. My debug port > indicates an output state inconsistent with any of the states in the > state machine and also inconsistent with the assignment for "others". > The code below indicates what is going on. > > with CC2400State select > debug_state <= > "0001" when RadioReset, > "0010" when RadioResetCheck, > "0011" when RadioCommand, > "0100" when RadioCommandWaitNotDone, > "0101" when RadioCommandWait, > "0110" when RadioConfig, > "0111" when RadioWaitOscStable, > "1000" when RadioWaitFSStable, > "1001" when RadioReadStatusWait, > "1010" when RadioEnablePacketRX, > "1011" when RadioReadNumBytes, > "1100" when RadioClearFIFO, > "1101" when RadioError, > "1110" when DelayState, > "1111" when others; > > In the unknown state my debug_state output is "0000". > > Any ideas? You might want to check whether all inputs to your state machine are synchronized. vax, 9000 > > DecoArticle: 76316
Should we ever get to that ? I know typically A and X bother recommend 80-85% resource usage and so do a lot of others But besides having no provision for expansion of design and probably extremely long p&r times, what are the other dangers of such a high resource utilisation, if our clock is only 40 MHz. Also what if we are using all 8 Rocket IOs in a device ?Article: 76317
"Adarsh Kumar Jain" <adarsh.jain@cern.ch> wrote in message news:coi7rq$nce$1@sunnews.cern.ch... > Should we ever get to that ? > I know typically A and X bother recommend 80-85% resource usage and so do a > lot of others > But besides having no provision for expansion of design and probably > extremely long p&r times, what are the other dangers of such a high resource > utilisation, if our clock is only 40 MHz. > Also what if we are using all 8 Rocket IOs in a device ? You're worried because you have 99% slice utilization? Don't! Check your LUT and register usage and you'll find you're probably *well* under the 99% mark. The P&R software tends to spread things around in the fabric, one element per slice until the slices are each occupied with something, then begin to backfill the extra slice resources to get the design in the part. It seems inefficient, but it's what we have to deal with. I look forward to the day when the slice components are be freely rearranged by the P&R software; why have two registers locked together at the map phase when P&R needs to make the tough decisions?Article: 76318
"Kevin Neilson" <kevin_neilson@removethiscomcast.net> wrote in message news:cog6kb$ohv2@xco-news.xilinx.com... > I'm trying to figure out the best way to floorplan registered adder > trees, such as those used in FIR filters. The (Xilinx) placer seems to > have very little idea what to do with these. Even when I use an area > constraint around the whole tree, the individual adders are not > optimally placed, so the result is that my critical path is always > between adders, and not the adder carry chain itself. I always have to > manually place each adder in the tree to get good results. My questions > are: > 1. Is there a way to get adder trees to work without manual placement? > 2. Is the best placement for an adder tree a tree structure (wide at > one end and narrow at the other) or some more rectangular arrangement? > -Kevin I've tried to work this issue some in the past. Since you're using Xilinx, the adders are vertical structures that occupy half a CLB allowing 2 adders per CLB column. The final adder has two inputs that come from smaller adder trees to the right and left for minimum propagation. I ended up going into the FPGA Editor to try different configurations to come up with the "optimum" delay. Most architectures like inputs that are one or two columns away with a feedback within a column sometimes producing better, sometimes worse delays compared to the adjacent column. Proper timing constraints would *ideally* give you the nice, right/left distributed adders.where bits at the same level are in the same CLB row across the adders. The P&R tool tends to be a little less precise but might be coerced into giving proper results with better constraints than I've developed. For the extremely tight designs I tend to RLOC the adders. It's a pain in Verilog but I haven't had to RLOC more than one or two moderately sized adder trees.Article: 76319
Johnson wrote: > > Hi there, > > Could anybody please let me know what is the approximate price of the > lowest-cost FPGA or CPLD with about 20K Lggic Cells, or even less? The > quantum will be around 10K per year. We will start a very simple > application, and I hope I can find some FPGA less than $5. I wish you luck in finding an FPGA at that price in any size at that quantity. My experience is that unless you are using a large enough quantity to get a vendor to pay for a new fab, you will be paying about $10 minimum. I think this has to do with the costs associated with testing. It seems that FPGAs will never truly be jellybean parts and I expect the FPGA vendors want to keep it that way since there is very little margin in such low prices no matter how efficiently they build them. By entering a low margin business model they could even become like the SDRAM vendors and loose a little on each unit they sell, trying to make it up in the volume! One other point, using gate counts to estimate chip size is pretty pointless, even for a rough estimate. The variation in actual gate count achieved varies so widely and how you measure gate count varies so widely that the metric is pointless. I guess it could get you to within an order of magnitude... $5 vs. $50 :) -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 76320
Hi Erik, I think others have described a solution to your problem. For a very good book on Verilog (and VHDL), check out "HDL Chip Design" by Douglas J. Smith. It has equivalent Verilog and VHDL for examples, and often equivalent schematics for both. There's more example code in this book than any other I've come across. For example, there's 74 pages solely on FSMs with 13 example state machines. As the title suggests the book details good design practice in general. I did about 3 years of VHDL before learning Verilog about 1.5 months ago so YMMV on how much Verilog resources you need. This book plus a few Google'd websites taught me as much Verilog as I need. Don't forget to check out http://www.sutherland-hdl.com/papers/2000-HDLCon-paper_Verilog-2000.pdf - a great summary of the cool Verilog 2001 additions. -- Pete Erik Walthinsen <omega@temple-baptist.com> wrote in message news:<cog9gj01ncl@enews2.newsguy.com>... > I'm a total Verilog newbie, having just started yesterday but already > finding it far less intimidating than the VHDL I thought I was going to > have to deal with. I'm a systems software programmer with enough > hardware knowledge to be dangerous, and a few projects under my belt > (microcontroller based servo-style stuff). FWIW I'm not taking any > classes on this stuff (yet?), just screwing around on my own. > > I'm playing with the design of a multi-channel analog capture system, > where I need an FPGA to take a number (4-16) of SPI inputs from stereo > audio ADCs, and multiplex them all into a 16-bit bus with a single write > strobe, to be connected to a Cypress EZ-USB FX2. > > I'm pretty sure I've got almost all the logic in place, *except* for a > clocking issue. The PCM audio SPI port includes an LRCLK (left-right > clock) that goes high at the end of the left channel sample, then goes > low at the end of the right channel sample. > > The problem is that even with a lot of googling, I haven't been able to > find (or recognize?) a way to create a pulse I can use to start the > parallel output sequence, on *both* edges of the LRCLK: > > SCLK .. _-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_- .. > DATA .. xxxxxxRRRRRRRRRRRRxxxxLLLLLLLLLLLLxxxxRRRRRRRRRRRRxx .. > LRCLK .. __----------------________________----------------__ .. > goal .. __-_______________-_______________-_______________-_ .. > > Once I have the LRCLK edge pulse, I can start up the FSM that will drive > each group of 16 bits to the output bus one at a time, based either on > SCLK or another clock (safer with SCLK, as it stays a basic synchronous > design AFAICT). > > Any hints would be greatly appreciated, especially code fragments <g> > Also if anyone can suggest a good example-heavy, relatively theory-light > book on Verilog FPGA design (e.g. "Verilog FPGA Design by Example for > Dummies") that I might get... > > TIA, > Omega > aka Erik Walthinsen > omega@temple-baptist.comArticle: 76321
Hello folks, I often see the following equation to define the dynamic power consumption of a node in a CMOS circuit: P = aCV^2F where: P = dynamic power a = ** average number of times in a clock cycle a node with capacitance C will make a power consuming transition ** V= supply voltage F = clock rate My question is related to the definition of 'a'. In a CMOS related paper I have seen 'a' defined as the average number of "0 to 1" transitions in a clock cycle since that is when power is drawn from the supply (half being stored in the cap and half being dissipated in the node). The 1 to 0 transition does not draw power from the supply, only the power previously stored in the cap on the 0 to 1 transition is dissipated. However, in some FPGA related papers, I see 'a' being defined as the probability of a 0 to 1 or a 1 to 0 transition during a clock cycle. Hence my confusion... Can anyone shed any light on why this might be (or are the FPGA papers I've seen just wrong)? Many thanks for your time, KenArticle: 76322
Hal Murray wrote: > > >Yes, I agree for a FIFO the simpler read port, write port block ram is > >preferred and is all that is needed for a FIFO. But the OP was asking > >for a way to infer a dual port block ram with write on both ports. He > >was not asking about FIFOs. I think the FIFO was mentioned as a way to > >interface a separately clocked interface to a single clock, dual port > >block ram. > > > >I dug through all this a few weeks ago and both Xilinx and Altera say > >that there are no means to infer true dual port, dual clock block rams > >at this time. > > Seems a bit strange. Why is a 2 port RAM that can read and write on > both ports that much more complicated to recognize than a 2 port > RAM that can only read on one port and write on the other? Damn good question. I suggest you ask your synthesis vendor... Oh, BTW, if you really want to deal with spammers, you might check up on a Maryland company that is going after them big time. http://www.baltimoresun.com/business/bal-bz.spam28nov28,1,5554454.story?coll=bal-business-headlines You will have to register to read the article. I am in Maryland and I would love to be able to cash in on this. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 76323
Varun Jindal wrote: > > Falk, > > You can do one thing, take a post-map verilog simulation file and > pattern search for LUT instances with only one input ... these will the > ones which are configured as route-thru > > Now, in the FPGA editor, you can search the component names for those > LUTs. > > I had done somehting similar few months back, i found most instances > when the LUT is used as route-thru to feed the dedicated XOR gate. the > otehr input of XOR gate coming from BY/BX signal. What could be the > reason for hte same !? ... my guess is some timing improvemnets. > > Though i have not yet seen myself the LUT route-thru mode used to feed > the flip - flop but i think it is possible to do so, while using both > Set and Reset signal in the Flip-flop. eg.FDSR instance of xilinx > primitives. > > the issue with this is, how the tool at mapping stage estimate whether > the preceeding logic to the flip flop be accomodated in the LUT or the > LUT be configured in route-thru mode. > > probably some data like number of route-thru LUTs post-map and post-pnr > can shed more light to it? Hmmm... it is odd that they would bother to do this, but if you are correct, it doesn't "cost" any extra LUTs then. Certainly they would not be using the LUT as a route-thru if it were being fed by any other LUTs. If the BX/BY input were being fed by a LUT, I still expect timing on most paths could be improved by moving some of the other signals to the route-thru LUT. If both inputs are being fed from registers, then no savings would be seen by using the LUT instead of making it a route-thru. But is it really very likely that there are 300 of these in a 1000 LUT design? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 76324
Andreas Schallenberg wrote: > > Hello! > > From the Virtex 4 documentation (Configuration Guide, > Users Guide) I learned that this family can be > configured during runtime in the granularity of single > frames. The frames which have a fixed size for all > members of this family. > Additionally the documents state that there is a tiled > placement of those frames. > > For Virtex II the frames started at the topmost CLB > and ended at the bottom of the FPGA. This does not > seem to be the case with Virtex 4 devices. > > This brings me to the question if it is now possible > to configure a part of the FPGA which looks like > e.g. a rectangle consisting of whole frames. > Having neighbour frames at all four sides of > that rectangle which are operating during that > reconfiguration process. > > I'm having a picture of a matrix-style arrangement > of all the frames in mind where I can select a set > of them which are to be reconfigured. > Unfortunately I didn't find any figure in the docs > which gives me a hint on that. > > Could anyone comment on this? I expect you are opening a serious can of worms. The concept is great, but the hard part is not the hardware, but the design software. Xilinx has supported modular design for partial reconfiguration (MDPR) for quite a while. But they have never represented that it works well and in fact caution users to tread carefully and to not get too ambitious. With the frame oriented MDPR being new, I would not expect it to be a simple thing to use for quite a while. I am still waiting for MDPR support for the Spartan 3, even without the rest of the chip running (which the Spartan 3 won't do). I just want to make my designs truely modular at configuration time to match the hardware configuration rather than to have to produce thousands of different configurations. I am now being told they will get right on that *after* they have done the Virtex 4 MDPR. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z