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CMOS wrote: > im looking for some advice/information on how to interface spartan3 > FPGA with TTL and CMOS chips. > does anybody know any ways to solder CLCC (CMOS image sensor ) at home? > > > Thank you As far as interfacing chips goes, just make sure the bank voltage matches the IO standard you want to use. Take a look at the datasheet for what the FPGA supports. You will most likely be using LVCMOS33 for most of your IO. The spartan 3 does not have 5V tolerant IO, so if you have any 5V logic, you will need translators. To solder the CLCC, you probably can just use your iron and a lot of flux. I like this method better than using a toaster oven since you can add parts one at a time and test. See http://dlharmon.com/solder/smd.html I only use a toaster oven for BGA. Darrell HarmonArticle: 88701
Ray Andraka wrote: (snip) > What Peter described is going to be more clock cycle efficient because > you use the BRAM in place of a wallace tree. His description isn't > really a wallace tree because it doesn't have the same structure (no > tree of carry-save adders, and the final outputs are complete sums of > the bits for those BRAMs, not a carry vector and a sum vector like a > wallace tree). You could use wallace trees to combine the results, from > the BRAMs, but it isn't efficient in an FPGA. Well, I might describe Peter's as using 12 bit wide (or is it deep) carry save adders. I forget by now if he actually made a tree out of it, though. -- glenArticle: 88702
Hello all, I am writing a problem that I have designing Standard Cell based designs. I know that this is an FPGA forum, but I am hoping someone here can help me. I am doing this design flow from Verilog->Netlist->Place&Route. I am doing this for the first time, so as u can imagine I have problems. According to the documentations I read, I need to generate an edif file, which is a schematic of the design, which is needed for the Floorplanner and then the Place and Route tools. I am using Synopsys Design Vision, and I am using the right target and symbol libraries, and the file gets compiled alright and I can see the schematic of my design. Now obviously, I should be able to capture this schematic in some sort of a text file (which is edif). But when I try to save as edif, it says that there is no schematic for the current design. There is no documentation at all for this, so I cannot figure out what to do. If anyone knows about this please let me know. If there is any other way that I can proceed to the Physical design tools also, please do let me know. Sincerely, AnupArticle: 88703
Symon, Virtex 4 is the target family for support. Although it is backward compatible to V2, if and when they do it. The DSp group here at Xilinx is doing this, and they have press releases, articles, etc. planned to go out, so I won't steal their thunder. Contact your FAE for details. I believe they are preparing to beta trials with early access customers (maybe you will be late!). Austin Symon wrote: > "austin" <austin@xilinx.com> wrote in message > news:dekl0k$b5m3@cliff.xsj.xilinx.com... > >>I also know that internal partial reconfiguration is seldom used, as there >>is very little tool support to enable designers to take advantage of it. >>The software defined radio (SDR) application appears to be the market >>driver here, with new tools being built right now to allow designers to >>use one small FPGA in a SDR that is able to modulate and demodulate dozens >>of over the air channel standards (SSB AM, NB FM, QAM, GMSK, etc etc >>etc...) merely by recognizing the senders format (using microblaze or the >>405PPC), followed by a partial reconfiguration of mod and demod functions, >>all in time to listen to who called you, and answer back. >> >>Exciting. >> > > Hi Austin, > Exciting indeed. At last a proper application that the rest of us can > leverage for our lower volume designs. Can you tell us which device(s) these > tools will be targetted at? (If the SDR app really takes off, I bet Xilinx > will soon add ICAP to Spartan devices!) And how far along the development > is? I guess I'll need to talk to my FAE under NDA. > Cheers, Syms. > >Article: 88704
I figured I should still be in the default PIO mode and signals don't get changed unless dmack is asserted in response dmarq and I'm sending a PIO only command so Dmarq isn't asserted. This is what threw me off. Register timings are pretty much work 100% and they work with the drive because I can tell it to go to idle and standby without problem but when I load the registers and send a command to write data it won't accept.Article: 88705
Ok I made the DMA write the value '0xE5C7CDDE872BF27C' to a SW register and it wrote '0xE5C7CDDE0xE5C7CDDE' ( the upper word was written twice ) so the problem is that it writes the upper word twice even when I am telling it to write 8 bytes froma buffer of 8 bytes. NoelArticle: 88706
Thank you all. I would like to know I there are any good books about building complex systems with signals between them. The usual beginner VHDL books do not go to deep on these things. :-/ "Simon Peacock" <simon$actrix.co.nz> skrev i meddelandet news:430d8f5b@news2.actrix.gen.nz... > One way to think about it.. is to try and imagine the design.. if you can't > imagine it all then it shouldn't be one module. > if you think logically about what modules work with what.. you can usually > imagine a simple interface between two parts and the timings can be simple > for this. That's where you break modules. The interface can then be fairly > logical and simple. > > Simon > > "Bubba" <blabla@bredband.net> wrote in message > news:430cc4ab$0$18647$14726298@news.sunsite.dk... > > I'm wondering what sort of approach I should have in coding a > > bigger-than-one-entity-system. > > > > > > > > The system is going to use an FPGA to get sample data from two different > > kinds of AD-converters (6 + 3 A/D-converters in total). Two different > > LP-filters to filter the signals. An SPI-interface to all send all the > data > > from the FPGA to the next system. > > > > > > > > Should I have a single state machine controlling all the different > entities? > > Or should I have some form of signal between the different blocks that > > determines the dataflow? > > > > > >Article: 88707
Hello,
For some reason the DMA drivers generated by the EDK 7.1 for my core
write the same word twice when the buffer is of two words. For example
I discovered that the DMA would write for rthe source buffer value of:
0xE5C7CDDE872BF27C
it will write to the destination: 0xE5C7CDDEE5C7CDDE (note that it
write the values from index =3D 0 to index =3D 3 twice) Can someone give me
some insight into what is happenning?
Thanks Here is the code:
Xuint8 SrcBuffer[MULTI_DES_SELFTEST_B=ADUFSIZE]
Xuint8 DstBuffer[MULTI_DES_SELFTEST_B=ADUFSIZE]
// SrcBuffer is initialize via a loop to contain '0xE5C7CDDE872BF27C'
for( Index =3D 0; Index < MULTI_DES_SELFTEST_BUFSIZE; Index + 8)
{
SrcBuffer[ Index ] =3D 0xE5;
SrcBuffer[ Index + 1 ] =3D 0xC7;
SrcBuffer[ Index + 2 ] =3D 0xCD;
SrcBuffer[ Index + 3 ] =3D 0xDE;
SrcBuffer[ Index + 4 ] =3D 0x87;
SrcBuffer[ Index + 5 ] =3D 0x2B;
SrcBuffer[ Index + 6 ] =3D 0xF2;
SrcBuffer[ Index + 7 ] =3D 0x7C;
}
// THe DstBuffer is initialize to zeroes
.=2E.
// The DMA is reset
MULTI_DES_mResetDMA0(baseaddr)=AD;
// The DMA setup
MULTI_DES_mSetDMA0Control(base=ADaddr, DMA_SINC_MASK | DMA_LOCAL_MASK );
// DMA transfer
MULTI_DES_DMA0Transfer( baseaddr, baseaddr +
MULTI_DES_WRFIFO_DATA_OFFSET,
MULTI_DES_SELTEST_BUFSIZE);
Article: 88708
Bubba wrote:
> I would like to know I there are any good books about building complex
> systems with signals between them. The usual beginner VHDL books do not go
> to deep on these things. :-/
Consider learning your vhdl simulator inside and out first.
Running a top level simulation can quickly answer
questions that are difficult to even put into words.
-- Mike Treseler
Article: 88709jms019@gmail.com wrote: > I have inherited a nearly-working FPGA SDRAM controller but my testing > shows I have got the structure wrong, partly due to lack of data on > Kingston's site. > > The module in question is the Kingston KVR133X64C3/1G. > > The verilog I have inherited caters for 11 column bits, 13 row bits, 4 > banks and two select lines. The module has sixteen chips on it which I > thought might be eight bit each so there would have to be two chip > select lines. > > But my testing shows something wrong with the way I assign > row/column/bank/cs. Maybe it is in fact 16 off 4 bit chips and just the > one chip select but a test assuming that shows I'm still losing a bit > somewhere. > > So what is the structure of this module and does the column go out on > A0-A9(,A11,A12) ? Googling throws up surprisingly little data given > that I'm not out to buy them. You could use the serial presence detect feature of the module in order to read out the device configuration. It's just I2C. The SPD ROM has this information. http://www.jedec.org/download/search/4_05_04R9.PDF http://download.micron.com/pdf/technotes/TN_04_42.pdf JeremyArticle: 88710
dlharmon wrote: > CMOS wrote: > >>im looking for some advice/information on how to interface spartan3 >>FPGA with TTL and CMOS chips. >>does anybody know any ways to solder CLCC (CMOS image sensor ) at home? >> >> >>Thank you > > > As far as interfacing chips goes, just make sure the bank voltage > matches the IO standard you want to use. Take a look at the datasheet > for what the FPGA supports. You will most likely be using LVCMOS33 for > most of your IO. The spartan 3 does not have 5V tolerant IO, so if you > have any 5V logic, you will need translators. > > To solder the CLCC, you probably can just use your iron and a lot of > flux. I like this method better than using a toaster oven since you can > add parts one at a time and test. See > http://dlharmon.com/solder/smd.html I only use a toaster oven for BGA. Not really on topic but why are the caps number in the 300 range on your DSP card ? like 339 ... SylvainArticle: 88711
"glen herrmannsfeldt" <gah@ugcs.caltech.edu> wrote > Marc Battyani wrote: > > > Does anybody already made a comparison of the high performance FPGA (Stratix > > II, V4, ?) relative to double precision floating point performance (add, > > mult, div, etc.) ? > > As far as I know, the biggest problem with floating point > in FPGAs is the barrel shifter needed to pre and post normalize > addition (and subtraction). > > Floating point multiply and divide are a little harder than fixed > point, but the post normalization only needs to shift one bit. > (I think that is right, but maybe two.) > > I would assume you can set the rounding mode at compile time, and > any other applicable IEEE mode bits. In fact I'm not sure that full IEEE floating point accuracy is needed. For sure single precision is not enough but probably double precision is not really needed. The problem is that people who write the algorithms do it in C(++) using double precision floats and they use double precision libraries, etc. So it's not obvious to see what precision is really needed. After all in an FPGA we can use the exact number of bit needed. (In fact it is even possible that a fixed point format could work) MarcArticle: 88712
Hi Jean, > -- II has less drive than MV (TMS,TCK,TDI,TDO are not buffered on my > card) BB2 has a completely different driver circuit, so that might definitely be the problem. However, you may want to put a 22-ohm resistor on TDI and TCK on the cable side - it sometimes helps. Best regards, BenArticle: 88713
<Terradestroyer@gmail.com> wrote in message news:1124999660.402695.301780@g47g2000cwa.googlegroups.com... > I figured I should still be in the default PIO mode What default PIO mode? The one in Set Transfer Mode or the one it comes up in? > and signals don't get changed unless dmack is asserted in response > dmarq and I'm sending a PIO only command so Dmarq isn't asserted. > This is what threw me off. > Register timings are pretty much work 100% and they work with the > drive because I can tell it to go to idle and standby without problem > but when I load the registers and send a command to write data it won't > accept. Any clues in the error bits? >Article: 88714
Here's a pipeline in Verilog - the theory should translate easily to
VHDL. I'm a beginner at Verilog, so forgive me if there's something
obviously wrong here.
module pop64(
input clk,
input [63:0] vec,
output reg [6:0] sum);
reg [63:0] s1, s2, s3, s4, s5;
always @(posedge clk)
begin
s1 <= (vec & 64'h5555555555555555) + ({ 1'b0, vec[63:1]
} & 64'h5555555555555555);
s2 <= (s1 & 64'h3333333333333333) + ({ 2'b0, s1[63:2]
} & 64'h3333333333333333);
s3 <= (s2 & 64'h0707070707070707) + ({ 4'h0, s2[63:4]
} & 64'h0707070707070707);
s4 <= (s3 & 64'h000f000f000f000f) + ({ 8'h0, s3[63:8]
} & 64'h000f000f000f000f);
s5 <= (s4 & 64'h0000001f0000001f) + ({ 16'h0,
s4[63:16] } & 64'h0000001f0000001f);
sum <= s5[37:32] + s5[5:0];
end
endmodule
This adds pairs of bits, then adds the sums.. then those sums, etc:
// vec bbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbb
// =>
// s1 aabbaabbaabbaabbaabbaabbaabbaabbaabbaabbaabbaabbaabbaabbaabbaabb
// =>
// s2 .aaa.bbb.aaa.bbb.aaa.bbb.aaa.bbb.aaa.bbb.aaa.bbb.aaa.bbb.aaa.bbb
// =>
// s3 ....aaaa....bbbb....aaaa....bbbb....aaaa....bbbb....aaaa....bbbb
// =>
// s4 ...........aaaaa...........bbbbb...........aaaaa...........bbbbb
// =>
// s5 ..........................aaaaaa..........................bbbbbb
// =>
// sum aaaaaaa
Comments welcome.
Paul.
Article: 88715Dimitri Turbiner wrote: [...] > Since books are really expensive and since I just want to get a "feel" > of the topics I'm looking at, I picked the habit of getting myself a > lot of ebooks. > > Now the thing is that I've accumulated some collection already. But > unfortunately I almost never really use them. (For the ones I liked I > used I buy the real books...). > > I just wanted to share with everyone interested the collection. [...] > As I don't really know the legal issues about publicly distributing > ebooks, I don't want to just post the adress of my ftp where I put > them (my old high school). I would be very appreciative if someone > would post a reply with some notice saying if it is legal or not. > If it is fully legal, then I can put them on my MIT account where I > have about 20 gigs of free space, and we could kind of start a > library of ebooks on fpga's, electronics, programming, and whatever > other topic. [...] > Hope these ebooks will help save money to some folks! Sorry, it's a bad idea that will get you into trouble, unless you know *for sure* that the ebook is redistributable. If you read at the first few pages of each book, you will almost certainly see a message stating whether copying and redistribution is allowed, and I'll bet that for most of those books you listed, it isn't. Even for stuff like Java documentation that is readable from Sun's web site, and downloadable after a license agreement, you aren't allowed to just redistribute the docs yourself. If you don't find a copyright notice within the ebook, you should assume that it is not for redistribution until you find some information to the contrary. You can always ask the author/publisher if you're not sure. The last sentence in your quote is telling: if the publisher is selling the ebook for money, don't you think they would prosecute copyright violations on that ebook? > Just a last consideration, I think a good legal solution would be > this: > I keep the ftp password protected, and then give the password to > anyone that wants to drop me an email. This way, it would'nt be > acccessible through google to all the spammers, etc, and I think that > this way there would be no problem for me to run it in the MIT > servers. This might be a way to avoid detection, but it doesn't change the legality of the actions. If you're not meant to redistribute the ebook, you can't give the password to anyone. If you are allowed, then the password is not needed! -Jason [not wanting to be rude, just trying to save you from hassle later on]Article: 88716
yusufilker@gmail.com wrote: > For analog video input ADV7402A is the best choice with it's RGB > digital output ports.. > If this board has either an ADV7400 or an ADV7402 on it, as well as a large S3, it has my name on it. I pity the poor fools who try to buy one first [grin]. SimonArticle: 88717
austin wrote:
> All,
>
> 'Reconfigurable' has now been extended to imply that while the device is
> operating, a section of it may be re-configured (changed to perform a
> new or different function) and then seemlessly used.
>
> The meaning is broader that the original.
>
> The ICAP (internal configuration access port) means you can perform this
> re-configuration from internal control sources, while performing other
> functions. I believe both of these capabilties are unique to Xilinx,
> starting with Virtex II.
>
> Spartan does not provide this ICAP feature. To them, re-configure,
> really means to configure the entire device, again. This is he original
> pre-Virtex II definition. Although, any new design may be loaded at the
> user's direction given there is more than one design to load, and a
> means to control which one gets loaded.
>
> I also know that internal partial reconfiguration is seldom used, as
> there is very little tool support to enable designers to take advantage
> of it. The software defined radio (SDR) application appears to be the
> market driver here, with new tools being built right now to allow
> designers to use one small FPGA in a SDR that is able to modulate and
> demodulate dozens of over the air channel standards (SSB AM, NB FM, QAM,
> GMSK, etc etc etc...) merely by recognizing the senders format (using
> microblaze or the 405PPC), followed by a partial reconfiguration of mod
> and demod functions, all in time to listen to who called you, and answer
> back.
>
> Exciting.
"Meeting Software Defined Radio cost and power targets: Making SDR feasible"
By Manuel Uhm, Xilinx and Jean Belzile, ISR
The vision of software reconfigurable radios is finally a reality, but
implementations are not as efficient as they could be. Although the radio
itself can be programmed to realize multiple waveforms for joint service
interoperability, current implementations require redundant hardware for
multiple channels.
A better approach is to use higher performing programmable logic that can be
partially reconfigured in-system. This shared resources method allows not only
the radio to implement multiple waveforms, but eliminates redundant per-
channel hardware. Partially reconfigurable FPGAs will save space, weight,
power, and cost.
-- end excerpt --
http://www.mil-embedded.com/articles/id/?379
-or-
http://www.mil-embedded.com/PDFs/Xilinx.May05.pdf
--
rk, Just an OldEngineer
"These are highly complicated pieces of equipment almost as complicated as
living organisms. In some cases, they've been designed by other computers. We
don't know exactly how they work."
-- Scientist in Michael Crichton's 1973 movie, Westworld
Article: 88718I am assuming it is starting up in any PIO mode from 0 - 2. I've been going through the ata-6 specs and it doesn't say anything about the mode the drive should start up in Right know my program is very "basic" to say the least. It really just tries to transfer data no matter what right know. So I actually have to add in checking the error register, but thats a good idea, it might be throwing me back something that could be a very good clue. Thanks KeithArticle: 88719
John Adair wrote: > Generally there are 100 variations of the place and route algorithm > otherwise known as cost tables. I have noticed over the past year or two with the current xilinx tools that when I run multi pass P&R, lots and lots of the passes will have different seed numbers, but it looks like they are the same route! By that I mean that all dozen or so of my timing constraints come out the same to 5 figures precision. If all the timespecs are identical, it must be the same route, right? In the past, with designs close to passing constraints I could run 30 MPPR passes and count on getting one that passes all constraints. But now when running 30 passes I only get 4 or 5 unique routes. Has anyone else noticed this phenomenon? I couldn't find mention of this in the answers database. -JeffArticle: 88720
speaking of ICAP, i don't know how to write the code to control the readback operation of configuration frame to BRAM. can you give me some suggestion? now, i am planning to implemente partial reconfiguration by SystemACE CF, i can obtain the partial bitstream through modular-based design flow introduced in XAPP290, then produce system .ACE file, and load the partial bitstream from CF in run-time. do you think this way is viable?Article: 88721
Hello All, I am a graduate student in Computer Engineering an am developing some small VHDL modules targeted to Xilinx Virtex devices. While I was trying to synthesize some of those designs using synpliciy I got the following error." Invalid LUT instantiation. Have you included the virtex.v(hd) file, and an INIT value @E:Internal Error". I tried adding virtex.vhd from synplicity installation library and tried to re synthesize it and now I see an error " Undefined identifier" and it does not even point to the module which causes this. I have read in some other postings in this group that one should not include unisim libraries while synthesizing using Synplify pro 7.7. I have in fact tried both ways (including and excluding unisim libraries) but the above error persists. I would appreciate if anyone can suggest where I am doing wrong. Thanks HarishArticle: 88722
I plan to implement partial reconfiguration by SystemACE CF: 1) produce partial bitstream through the module-based design flow introduced in XAPP290; 2) transform the partial bitstream to .ace files by iMPACT, load to CF; 3) load the needed partial bitstream in run-time from CF. DO you think this method is viable? what must I pay attention to?Article: 88723
It's a good module but their data is under NDA .. silly but I guess its a competitive market. We use the 7 port device with 4 built in PHY's (going to a quad RJ45 with built in XFMR's) and one Ethernet connected to a PPC and one to the FPGA. With QOS, VLAN and bridging you get a lot of features for little cost. The reversed PHY connections also make it better for an FPGA as the FPGA generates the rxc and txc clocks, but as its a switch, with buffering, the clocks don't need to vary as a normal PHY will do. I should have a working prototype MAC running in next week but its a very specific one for my company allowing full speed 100 MBS full duplex ... I convinced my Boss to get a Memic S31500 demo board with a broadcom PHY... no where near as good or easy to use as the Marvell and they put the chip under the LCD so you can't even look at the pins... but beggars can't be choosers. Simon "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk> wrote in message news:1124976892.2298.0@spandrell.news.uk.clara.net... > We will have a look at this as a module. We already have and ethernet module > planned so maybe a multichannel might be better. > > John Adair > Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development > Board. > http://www.enterpoint.co.uk > > "Simon Peacock" <simon$actrix.co.nz> wrote in message > news:430d9100@news2.actrix.gen.nz... > > How about a Marvell 4 port Ethernet switch (linkstreet) so that you can > > build a real internet host... they aren't that expensive and can be an > > option if your desperate. > > http://www.marvell.com/products/switching/linkstreet/index.jsp > > > > It is strictly an MII interface so it can be treated as a PHY except it > > can > > receive TX_CLK and RX_CLK which makes it nice for an FPGA. > > I know this as I am just starting to connect one to a S31000. > > Simon > > > > > > "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk> wrote > > in > > message news:1124900629.17438.0@ersa.uk.clara.net... > >> Well you might be pleasantly surprised by the new board. > >> > >> EAR, to use the acronym, affects some leading edge-ish semiconductors if > > you > >> onward ship the devices or products made from them. Items that can be > > "dual > >> use" especially can be affected, "Dual Use" refers to an item finding its > >> way into military kit when it's origional function was purely commercial. > > It > >> is conceivable that FPGA development boards could be used for something > >> outside their intended use because they are user programmable. More of a > >> problem that say a PCI card with a fixed function. > >> > >> The US also have embargoed countries that technically can't be shipped > >> to. > >> > >> Failure to observe these regulations can bring fines and I believe > >> imprisonment. Someone from the US may say that my understanding is > > incorrect > >> and I don't claim to be any expert in these matters. > >> > >> John Adair > >> Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development > >> Board. > >> http://www.enterpoint.co.uk > >> > >> > >> "c d saunter" <christopher.saunter@durham.ac.uk> wrote in message > >> news:dehvgq$p56$1@heffalump.dur.ac.uk... > >> > John, > >> > I had a look at the Broaddown2 module, and one item I couldn't see > >> > was > >> > a user Flash device - although the platform flash can be used for user > >> > data it's sometimes convenient to have a physically seperate flash, and > >> > these days you can get some large storage, physically tiny SPI devices. > >> > > >> > Also as an asside, I was interested to see your note on the US & UK > > export > >> > regulations - can you expand any details on that? Top Secret pinout on > > the > >> > edge connectors :-) or regulations on the FPGA? > >> > > >> > Regards, > >> > Chris > >> > > >> > John Adair (removethisthenleavejea@replacewithcompanyname.co.uk) wrote: > >> > : Representing a manufacturer of development boards I am going offer > >> > you > >> > all > >> > : the chance to have your say on what is goes into our new product > >> > : Raggedstone1 and it's supporting modules. > >> > > >> > : What I can tell is that the board is very cheap and takes what we > > think > >> > are > >> > : some of the best attributes of the our existing Broaddown2 and > > MINI-CAN > >> > : products. Like them it is also a Spartan-3 board (why another! - well > >> > you > >> > : just have to wait and see when we start revealing features in about 4 > >> > weeks > >> > : time). We have also included ideas based on existing customer > >> > feedback > >> > on > >> > : the Broaddown2 and MINI-CAN products. > >> > > >> > : We are now in the last week of layout and have found some small areas > > of > >> > : board space that we might stick something on. So do your worst and > >> > suggest > >> > : (politely please) what we might give you in features. Even if your > > idea > >> > is > >> > : too big, or expensive, for Raggedstone1 itself then it may make our > >> > add-on > >> > : module list or even the next higher end Broaddown3/4 product > >> > launches. > >> > > >> > : John Adair > >> > : Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 > > Development > >> > : Board. > >> > : http://www.enterpoint.co.uk > >> > : > >> > > >> > > >> > >> > > > > > >Article: 88724
Hallo, I have compiled "simple bootloader" generated with tool "Program Flash memory" of EDK Platform studio. At Local date and time: Fri Aug 26 10:15:15 2005 Command xbash -q -c "cd /cygdrive/d/Projects/sistema_boot/; /usr/bin/make -f system.make program; exit;" Started... mb-gcc -Os bootloader/bootloader.c bootloader/srec.c -o bootloader/executable.elf \ -mno-xl-soft-mul -I./microblaze_0/include/ -Ibootloader/ -L./microblaze_0/lib/ \ -xl-mode-executable \ mb-size bootloader/executable.elf text data bss dec hex filename 2576 20 1192 3788 ecc bootloader/executable.elf Done. After I have opened the tool: "Generate Linker script" to configure memory sections. .text 0x000008C8 .rodata 0x00000120 .sdata2 0x00000028 .data 0x00000014 .sbss 0x00000000 .bss 0x000004A8 Heap 0xA28 Stack 0XE28 I generate Linker Script using a dedicated bram of 8Kbytes connected to system through opb_bram_controller. When I recompile bootloader I receive the following error message: Linker Script generated successfully. At Local date and time: Fri Aug 26 10:21:16 2005 Command xbash -q -c "cd /cygdrive/d/Projects/sistema_boot/; /usr/bin/make -f system.make program; exit;" Started... mb-gcc -Os bootloader/bootloader.c bootloader/srec.c -o bootloader/executable.elf \ -mno-xl-soft-mul -Wl,-T -Wl,bootloader/bootloader_linker_script -I./microblaze_0/include/ -Ibootloader/ -L./microblaze_0/lib/ \ -xl-mode-executable \ /cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/3.4.1/../../../../microblaze/bin/ld.real: region opb_bram_if_cntlr_0 is full (bootloader/executable.elf section bss_stack) /cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/3.4.1/../../../../microblaze/bin/ld.real: region opb_bram_if_cntlr_0 is full (bootloader/executable.elf section bss_stack) collect2: ld returned 1 exit status make: *** [bootloader/executable.elf] Error 1 Done. What could I do to solve this trouble? Many Thanks Marco
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