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many thanks for all the ppl. yes, they dont provide much infomation/documentation on USB 2 module. The more info button brings up a .pdf, which is wrong ( which is a doc file for a USB1.1 device). Digilent confirmed me that it points to a wrong place. but the problem im having is why cant they fix it and give some useful infomation about that board. anyway, since im in the real need for USB2, i bought that board together with the starter board ( 400K, im dissappointed i could not order a 1000K one bcuz it is out of stock for 2-4 weeks). the Cypress controller it has supports high speed data rate. But im not sure what kind of interface from host side and form hardware side is provided with this board. If i have to write a device driver to use it properly OR if i have to read the full documentation of cypress USB controller to use it, it is almost useless for me. i think they should atleast provide VHDL code to controll the cypress controller and some dll to run in windows, which has a simple enough interface for programmers. Thank you. CMOSArticle: 88676
im looking for some advice/information on how to interface spartan3 FPGA with TTL and CMOS chips. does anybody know any ways to solder CLCC (CMOS image sensor ) at home? Thank youArticle: 88677
Google "toaster oven" solder. HTH, Syms. "CMOS" <manusha@millenniumit.com> wrote in message news:1124950202.603492.10380@g14g2000cwa.googlegroups.com... > im looking for some advice/information on how to interface spartan3 > FPGA with TTL and CMOS chips. > does anybody know any ways to solder CLCC (CMOS image sensor ) at home? > > > Thank you >Article: 88678
Hi everybody, As I received some emails about the systemC books I had I decided to post this: I'm a student so my interests still change rather fastly :D Since books are really expensive and since I just want to get a "feel" of the topics I'm looking at, I picked the habit of getting myself a lot of ebooks. Now the thing is that I've accumulated some collection already. But unfortunately I almost never really use them. (For the ones I liked I used I buy the real books...). I just wanted to share with everyone interested the collection. I'm still uploading some books, but here's what I got at the moment: - about 25 books on AI with, mostly about Neural Networks and Computer Vision. There's my very loved book: Artificial Intelligence, A modern Approach!!!! - about 15 books about FPGA's, mostly on SystemC, VHDL, DSP on FPGA, and introductory guides and books (I have The Designer Warrior guide to FPGA's for example) - 4 books on LaTex, graphics and just writing LaTex - 3 books on programming that didn't fit in AI: My two very loved Structure and Interpretation of Computer Programs (Abelson and Sussman) and Introduction to Algorithms (Cormen et al), and a genetic algorithms book - 2 books on Scheme (a LISP dialog) The list is growing rather fastly... As I don't really know the legal issues about publicly distributing ebooks, I don't want to just post the adress of my ftp where I put them (my old high school). I would be very appreciative if someone would post a reply with some notice saying if it is legal or not. If it is fully legal, then I can put them on my MIT account where I have about 20 gigs of free space, and we could kind of start a library of ebooks on fpga's, electronics, programming, and whatever other topic. Anyways, just drop me an email at dima_turbiner[at]yahoo.com and I'll gladly send you the link. (Just please don't post it until I'm sure its legal) Hope these ebooks will help save money to some folks! BTW, what would all of you think about putting up a library of these ebooks. Everyone ecould use them and everyone could contribute to it (I would be very glad :D) If this whole thing is solid enough, I'll put up a full list and keep updating it twice a month or so as I (or anyone willing to contribute) put in more books. Just a last consideration, I think a good legal solution would be this: I keep the ftp password protected, and then give the password to anyone that wants to drop me an email. This way, it would'nt be acccessible through google to all the spammers, etc, and I think that this way there would be no problem for me to run it in the MIT servers. I hope people will reply to this post so that this library gets a start! Greetings to all, Dimitri drop me an email at dima_turbiner[at]yahoo.com to get the link or just questionsArticle: 88679
Hallo, I have made a small microcontroller based on microblaze, I have added the microblaze debug module core. I have connected also a lcd display. This peripheral is fully working. I have created a software to write a word into display. If I download software into ram, through XMD, and run it, it is fully functional, it writes the word. I have created a bootloader through "Program Flash Memory" window. I have checked "Mark to initialize bram" into bootloader options. I have updated the fpga bitstream. I have cerated also a prom, following xapp482 that contains the bitstream and my software. Now, when I power on the board, the fpga configures itself, but does not write anything into the lcd display. I have tried opening xmd and use the command run, but I receive the following error message: XMD% run Processor started. Type "stop" to stop processor RUNNING> Xilinx Bootloa Xilinx Bootloader: ERRROR: SREC line is corrupt edRUNNING> If I still type, "run", the software works and prints the word into display. What could I do to solve this trouble? Many Thanks MarcoArticle: 88680
I would agree... I do this quite often in VHDL using the same idea.. statements are executed is sequence within a process... processes are executed in parallel. this is a good way to generate strobes which have one on condition and multiple off conditions. I just have a section of "defaults" after the clock. Quite nice in state machines to keep states uncluttered... and it means states only care about the tasks each state knows about (or cares about). Simon "Jonathan Bromley" <jonathan@oxfordbromley.u-net.com> wrote in message news:430ca95b.2463367@news.freeserve.com... > On Mon, 15 Aug 2005 03:21:49 +0200, Tullio Grassi > <tgrassi@mail.cern.ch> wrote: > > >my understanding of verilog is that the code below is umbigous, > > >> always @(posedge clk) begin > >> out_reg <= 2'd0; // Default value > >> if (condition_1) > >> out_reg <= 2'd1; > >> if (condition_2) > >> out_reg <= 2'd2; > >> end > > >so it is a bad practice anyway, with or without delays. > >The reason of the ambiguity is that assignements are > >analyzed in parallel, so if condition 2 is true, you > >don't know if the synthezaizer implemented > > out_reg <= 2'd0; > >or > > out_reg <= 2'd2; > > This is completely untrue. > > Signal updates scheduled by nonblocking assignments > *for a given moment of time* are performed in the > same order in which the assignments were executed. > > I stand by my statement that this is "a useful > synthesis idiom" provided you don't make the mistake > of adding delays to the assignments. > > -- > Jonathan BromleyArticle: 88681
One way to think about it.. is to try and imagine the design.. if you can't imagine it all then it shouldn't be one module. if you think logically about what modules work with what.. you can usually imagine a simple interface between two parts and the timings can be simple for this. That's where you break modules. The interface can then be fairly logical and simple. Simon "Bubba" <blabla@bredband.net> wrote in message news:430cc4ab$0$18647$14726298@news.sunsite.dk... > I'm wondering what sort of approach I should have in coding a > bigger-than-one-entity-system. > > > > The system is going to use an FPGA to get sample data from two different > kinds of AD-converters (6 + 3 A/D-converters in total). Two different > LP-filters to filter the signals. An SPI-interface to all send all the data > from the FPGA to the next system. > > > > Should I have a single state machine controlling all the different entities? > Or should I have some form of signal between the different blocks that > determines the dataflow? > >Article: 88682
How about a Marvell 4 port Ethernet switch (linkstreet) so that you can build a real internet host... they aren't that expensive and can be an option if your desperate. http://www.marvell.com/products/switching/linkstreet/index.jsp It is strictly an MII interface so it can be treated as a PHY except it can receive TX_CLK and RX_CLK which makes it nice for an FPGA. I know this as I am just starting to connect one to a S31000. Simon "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk> wrote in message news:1124900629.17438.0@ersa.uk.clara.net... > Well you might be pleasantly surprised by the new board. > > EAR, to use the acronym, affects some leading edge-ish semiconductors if you > onward ship the devices or products made from them. Items that can be "dual > use" especially can be affected, "Dual Use" refers to an item finding its > way into military kit when it's origional function was purely commercial. It > is conceivable that FPGA development boards could be used for something > outside their intended use because they are user programmable. More of a > problem that say a PCI card with a fixed function. > > The US also have embargoed countries that technically can't be shipped to. > > Failure to observe these regulations can bring fines and I believe > imprisonment. Someone from the US may say that my understanding is incorrect > and I don't claim to be any expert in these matters. > > John Adair > Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development > Board. > http://www.enterpoint.co.uk > > > "c d saunter" <christopher.saunter@durham.ac.uk> wrote in message > news:dehvgq$p56$1@heffalump.dur.ac.uk... > > John, > > I had a look at the Broaddown2 module, and one item I couldn't see was > > a user Flash device - although the platform flash can be used for user > > data it's sometimes convenient to have a physically seperate flash, and > > these days you can get some large storage, physically tiny SPI devices. > > > > Also as an asside, I was interested to see your note on the US & UK export > > regulations - can you expand any details on that? Top Secret pinout on the > > edge connectors :-) or regulations on the FPGA? > > > > Regards, > > Chris > > > > John Adair (removethisthenleavejea@replacewithcompanyname.co.uk) wrote: > > : Representing a manufacturer of development boards I am going offer you > > all > > : the chance to have your say on what is goes into our new product > > : Raggedstone1 and it's supporting modules. > > > > : What I can tell is that the board is very cheap and takes what we think > > are > > : some of the best attributes of the our existing Broaddown2 and MINI-CAN > > : products. Like them it is also a Spartan-3 board (why another! - well > > you > > : just have to wait and see when we start revealing features in about 4 > > weeks > > : time). We have also included ideas based on existing customer feedback > > on > > : the Broaddown2 and MINI-CAN products. > > > > : We are now in the last week of layout and have found some small areas of > > : board space that we might stick something on. So do your worst and > > suggest > > : (politely please) what we might give you in features. Even if your idea > > is > > : too big, or expensive, for Raggedstone1 itself then it may make our > > add-on > > : module list or even the next higher end Broaddown3/4 product launches. > > > > : John Adair > > : Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development > > : Board. > > : http://www.enterpoint.co.uk > > : > > > > > >Article: 88683
What's the error message you get from Impact? And have you tried to narrow the scope down a little? There could be 100s of different things wrong, from software drivers, to cable setup, to your pcb... Ben "Pierre" <pierre.lefaix@siemens.com> wrote in message news:ee8fb6b.-1@webx.sUN8CHnE... > Hello, > > I am working with a spartan 2 and a PROM XCF01S. Impact software does not > recognized the chain of this two components, whereas I have the same > schematic than in the datasheet. > > Could somebody help me ?Article: 88684
Hi group, I have been using one ByteBlasterMV for a long time now, to program a chain of 4 components in JTAG: EPM1270144 LXT971 LXT971 EPM1270144 LXT971's are Intel (Level-One) PHY's, with an Instruction Register of length 4 bits. I run Quartus II 4.2 SP1, free Web version, on an XP PC. I have never had the slightest problem with the MV pod. Recently, I purchased for our manufacturing/test department one ByteBlaster II for programming the same chain of components on the same PCB, using the same setup. Of course, I tried it first at my desk. Does not work. De-installation/re-installation of driver has been done as per Altera Web Site instructions. MV keeps on working fine. ByteBlaster II keeps on refusing to provide reliable behaviours. For instance: -- accepts to erase both Altera CPLD's -- says they are blank -- running examine returns a message like "Bad silicon ID on device 4" -- same thing with program/verify. Tried with a second ByteBlaster II. Same thing. Tried with another card holding the chain of components. Same thing. I can think of: -- II has less drive than MV (TMS,TCK,TDI,TDO are not buffered on my card) -- II runs faster ? Any idea ? Thanks beforehand.Article: 88685
go fly a kite.Article: 88686
We will have a look at this as a module. We already have and ethernet module planned so maybe a multichannel might be better. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "Simon Peacock" <simon$actrix.co.nz> wrote in message news:430d9100@news2.actrix.gen.nz... > How about a Marvell 4 port Ethernet switch (linkstreet) so that you can > build a real internet host... they aren't that expensive and can be an > option if your desperate. > http://www.marvell.com/products/switching/linkstreet/index.jsp > > It is strictly an MII interface so it can be treated as a PHY except it > can > receive TX_CLK and RX_CLK which makes it nice for an FPGA. > I know this as I am just starting to connect one to a S31000. > Simon > > > "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk> wrote > in > message news:1124900629.17438.0@ersa.uk.clara.net... >> Well you might be pleasantly surprised by the new board. >> >> EAR, to use the acronym, affects some leading edge-ish semiconductors if > you >> onward ship the devices or products made from them. Items that can be > "dual >> use" especially can be affected, "Dual Use" refers to an item finding its >> way into military kit when it's origional function was purely commercial. > It >> is conceivable that FPGA development boards could be used for something >> outside their intended use because they are user programmable. More of a >> problem that say a PCI card with a fixed function. >> >> The US also have embargoed countries that technically can't be shipped >> to. >> >> Failure to observe these regulations can bring fines and I believe >> imprisonment. Someone from the US may say that my understanding is > incorrect >> and I don't claim to be any expert in these matters. >> >> John Adair >> Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development >> Board. >> http://www.enterpoint.co.uk >> >> >> "c d saunter" <christopher.saunter@durham.ac.uk> wrote in message >> news:dehvgq$p56$1@heffalump.dur.ac.uk... >> > John, >> > I had a look at the Broaddown2 module, and one item I couldn't see >> > was >> > a user Flash device - although the platform flash can be used for user >> > data it's sometimes convenient to have a physically seperate flash, and >> > these days you can get some large storage, physically tiny SPI devices. >> > >> > Also as an asside, I was interested to see your note on the US & UK > export >> > regulations - can you expand any details on that? Top Secret pinout on > the >> > edge connectors :-) or regulations on the FPGA? >> > >> > Regards, >> > Chris >> > >> > John Adair (removethisthenleavejea@replacewithcompanyname.co.uk) wrote: >> > : Representing a manufacturer of development boards I am going offer >> > you >> > all >> > : the chance to have your say on what is goes into our new product >> > : Raggedstone1 and it's supporting modules. >> > >> > : What I can tell is that the board is very cheap and takes what we > think >> > are >> > : some of the best attributes of the our existing Broaddown2 and > MINI-CAN >> > : products. Like them it is also a Spartan-3 board (why another! - well >> > you >> > : just have to wait and see when we start revealing features in about 4 >> > weeks >> > : time). We have also included ideas based on existing customer >> > feedback >> > on >> > : the Broaddown2 and MINI-CAN products. >> > >> > : We are now in the last week of layout and have found some small areas > of >> > : board space that we might stick something on. So do your worst and >> > suggest >> > : (politely please) what we might give you in features. Even if your > idea >> > is >> > : too big, or expensive, for Raggedstone1 itself then it may make our >> > add-on >> > : module list or even the next higher end Broaddown3/4 product >> > launches. >> > >> > : John Adair >> > : Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 > Development >> > : Board. >> > : http://www.enterpoint.co.uk >> > : >> > >> > >> >> > >Article: 88687
Yes in using the BFM model and it worked great on simulation.Article: 88688
Hi guys, I must admit it's been a while since i have used Spartan2E; please help me with relatively simple issue, as i cannot find the answer to my question anywhere. I am given a board, where I have XC2S400E device (FT256 package), and I have to make a design with what I have. I would like to use DLL. That is, I have an onboard oscillator of 25 MHz, which I would like to multiply by 2, and get 50 MHz (so fat, per datasheet DLL can accept a frequnecy starting from 25 MHz). FPGA device does not receive any external reset (do not ask why, I did not design the board). Now, the question. I see that CLK2x output generates 25 MHz, not 50 MHz. Do I have to reset DLL??? It's just that before I ask to solder some wire for reset, I would like to be sure of that. I saw in Virtex-II devices many times that there is no need for resetting DCMs, and the frequency they produce is just fine. Thanks a lot in advance. VladislavArticle: 88689
All, 'Reconfigurable' has now been extended to imply that while the device is operating, a section of it may be re-configured (changed to perform a new or different function) and then seemlessly used. The meaning is broader that the original. The ICAP (internal configuration access port) means you can perform this re-configuration from internal control sources, while performing other functions. I believe both of these capabilties are unique to Xilinx, starting with Virtex II. Spartan does not provide this ICAP feature. To them, re-configure, really means to configure the entire device, again. This is he original pre-Virtex II definition. Although, any new design may be loaded at the user's direction given there is more than one design to load, and a means to control which one gets loaded. I also know that internal partial reconfiguration is seldom used, as there is very little tool support to enable designers to take advantage of it. The software defined radio (SDR) application appears to be the market driver here, with new tools being built right now to allow designers to use one small FPGA in a SDR that is able to modulate and demodulate dozens of over the air channel standards (SSB AM, NB FM, QAM, GMSK, etc etc etc...) merely by recognizing the senders format (using microblaze or the 405PPC), followed by a partial reconfiguration of mod and demod functions, all in time to listen to who called you, and answer back. Exciting. Austin Symon wrote: > "echoisme" <ghy@eyou.com> wrote in message > news:1124940523.012775.76130@g44g2000cwa.googlegroups.com... > >>thanks, everybody >>then what is difference between "reconfigurable" and "programmable"? >>i am really confused with them for a long time! >> > > In the context we're discussing, "reconfigurable" implies the device can be > programmed more than once. "Programmable" implies it can be configured at > least once. > Cheers, Syms. > > p.s. So, "configurable" means the same as "programmable". Adding "re" at the > beginning of either word means you can do it more than once! > >Article: 88690
> Before you spend too much time screwing around with Hyperterm or other > serial programs, have you looked at the signals from your fpga board to > the serial input of your computer? Start with no serial cable, and > check that the TX pin (when no characters being sent) is -5V > to -15V. The RX line should be floating close to 0V. Check the two pins > that TX and RX connect to on the computer (pins 2 and 3 of serial port > connector). The one that your FPGA TX is going to connect to should be > an RX pin, and it should be close to 0V. The pin that the FPGA board's > RX is going to connect to (computer TX) should be -5V to -15V. With no serial cable fpga TX is -5V and RX is 0V. With no serial cable pc RX is -15V and RX is 0V. Is it fault? MarcoArticle: 88691
Brandon, I'm not 100% clear on what your filter structure looks like, but for a high throughput, large FIR like this, you should be using a transposed direct form I structure. If you have fanout problems with this, and can tolerate additional latency, you can use a systolic structure. Xilinx has a nice depiction of both in (pp. 84-85): http://www.xilinx.com/bvdocs/userguides/ug073.pdf For either structure, you can simply string a shift register together to load your tap coefficients. I hope this helps. cheers, aaronArticle: 88692
Vladislav - Why not create a reset signal in the chip that holds the DCM reset after configuration? The SRL16 shift register starts up after device configuration in a known state. Have it shift out areset signalfor a16 cycles at the 25MHz as the reset to the DCM. You can also use this (with a bit more logic) to reset the rest of your design. John ProvidenzaArticle: 88693
Solved the trouble... sometimes, I'm so stupid... I don't have used a straight cable. Now it works perfectly! Many Thanks to Everyone!!!! MarcoArticle: 88694
"austin" <austin@xilinx.com> wrote in message news:dekl0k$b5m3@cliff.xsj.xilinx.com... > > I also know that internal partial reconfiguration is seldom used, as there > is very little tool support to enable designers to take advantage of it. > The software defined radio (SDR) application appears to be the market > driver here, with new tools being built right now to allow designers to > use one small FPGA in a SDR that is able to modulate and demodulate dozens > of over the air channel standards (SSB AM, NB FM, QAM, GMSK, etc etc > etc...) merely by recognizing the senders format (using microblaze or the > 405PPC), followed by a partial reconfiguration of mod and demod functions, > all in time to listen to who called you, and answer back. > > Exciting. > Hi Austin, Exciting indeed. At last a proper application that the rest of us can leverage for our lower volume designs. Can you tell us which device(s) these tools will be targetted at? (If the SDR app really takes off, I bet Xilinx will soon add ICAP to Spartan devices!) And how far along the development is? I guess I'll need to talk to my FAE under NDA. Cheers, Syms.Article: 88695
Jack Falk wrote: > I've heard this rumor many times from different sources: that Virtex4 > TBUFs don't actually have tri-state buffers in them, and that they're > actually implemented as a set of wires and muxes which is logically > (though not electrically) equivalent to everything you could do if > they were. As I understand it, the problem is buffering. While a long line may look like a wire to you, it has internal buffers in it in hardware. Those buffers have to point the right direction. It is related to the scaling laws. As wires scale they get smaller in two dimensions, increasing the resistance by the square of the scale (decrease) factor, but the capacitance depends only on the width. RC then increases as devices get smaller when it needs to decrease to keep up with the faster logic. The solution is internal buffers. -- glenArticle: 88696
Next step is full system simulation which will then allow you to verify the software is interacting with the hardware correctly. There might be an issue there. If that works, then it is time to insert Chipscope at various places in the hardware and compare the results to the working simulation. A few iterations of this process should reveal the issue. Good Luck! Paul el_boricua wrote: > > Yes in using the BFM model and it worked great on simulation.Article: 88697
Marc Battyani wrote: > Does anybody already made a comparison of the high performance FPGA (Stratix > II, V4, ?) relative to double precision floating point performance (add, > mult, div, etc.) ? As far as I know, the biggest problem with floating point in FPGAs is the barrel shifter needed to pre and post normalize addition (and subtraction). Floating point multiply and divide are a little harder than fixed point, but the post normalization only needs to shift one bit. (I think that is right, but maybe two.) I would assume you can set the rounding mode at compile time, and any other applicable IEEE mode bits. -- glenArticle: 88698
Ray Andraka wrote: (snip regarding BRAMs and shift registers) > Peter, with SPartan3, he can do it with one port of the BRAM if he uses > a modulo-N count instead of a straight 14 bit binary count. I showed > this in the code I posted earlier. The modulo N count is easy if you do > it as a loadable down-count that reloads itself when it goes negative. So you read the previous data while writing the new data into the same address. -- glenArticle: 88699
Ray Andraka wrote: (snip) > Why is it difficult to understand or modify? > It is just a counter that gets loaded with (delay-2) and then counts > down until it becomes -1, and then reloaded. The load value can be > changed at any time, and takes effect the next time the counter reaches > the terminal count of -1 (this downcounter has the advantage of not > requiring any decoding, and of having an easily adjusted modulus). The > counter output becomes the address to the memory. I think it is pretty > straightforward to comprehend, do you find it otherwise? The only > difference is just being a little clever in the counting and taking > advantage of the read before write capability of the memory. > As far as modifying it, I'm not sure I see the difficulty there > either: The modulus is easy to change, and in particular can be easily > changed dynamically. You can easily change the width of the counter for > different aspect ratios on the memory, say for instance if you wanted to > delay a 9 bit signal by a delay not to exceed 2048 clocks. Beyond that, > I'm not sure what modifications you'd want to make, or for that matter > what modifications that wouldn't be as difficult in the two port scheme > you offered. It would seem to perform better if you change the length while it is running. Though at some point changing the length of a running shift register is not so well defined, but the results in Peter's case are a little strange. -- glen
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