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Messages from 88725

Article: 88725
Subject: Re: what is the difference between "configuring" and "programming"?
From: "Symon" <symon_brewer@hotmail.com>
Date: Fri, 26 Aug 2005 02:00:08 -0700
Links: << >>  << T >>  << A >>
"austin" <austin@xilinx.com> wrote in message 
news:del1gh$b5s1@cliff.xsj.xilinx.com...
> Symon,
>
> Virtex 4 is the target family for support.  Although it is backward 
> compatible to V2, if and when they do it.
>
> Contact your FAE for details.
Will do Austin, thanks for the heads up.
Syms. 



Article: 88726
Subject: Re: FPGA Development Board Wish List
From: "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk>
Date: Fri, 26 Aug 2005 10:29:26 +0100
Links: << >>  << T >>  << A >>
I had a 2 min pass at the part and if I understood it correctly (I didn't 
find a datasheet I could access) we need about 40 I/O on the Spartan-3 side. 
It would good as a module if it where less than 38. Otherwise it does look a 
good chip for us to support or even the adv7403 that looks to be 
superceeding it.

John Adair
Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development 
Board.
http://www.enterpoint.co.uk

"Simon" <news@gornall.net> wrote in message 
news:eoudnY3mo96rw5PeRVn-hA@comcast.com...
> yusufilker@gmail.com wrote:
>> For analog video input ADV7402A  is the best choice with it's RGB
>> digital output ports..
>>
>
> If this board has either an ADV7400 or an ADV7402 on it, as well as a 
> large S3, it has my name on it. I pity the poor fools who try to buy one 
> first [grin].
>
> Simon 



Article: 88727
Subject: Re: Stdin / stdout through RS232
From: Philip Freidin <philip@fliptronics.com>
Date: Fri, 26 Aug 2005 10:39:33 GMT
Links: << >>  << T >>  << A >>
On Thu, 25 Aug 2005 16:44:19 +0200, "Marco" <marcotoschi@nospam.it> wrote:
>> Before you spend too much time screwing around with Hyperterm or other
>> serial programs, have you looked at the signals from your fpga board to
>> the serial input of your computer? Start with no serial cable, and
>> check that the TX pin (when no characters being sent) is -5V
>> to -15V. The RX line should be floating close to 0V. Check the two pins
>> that TX and RX connect to on the computer (pins 2 and 3 of serial port
>> connector). The one that your FPGA TX is going to connect to should be
>> an RX pin, and it should be close to 0V. The pin that the FPGA board's
>> RX is going to connect to (computer TX) should be -5V to -15V.
>
>With no serial cable fpga TX is -5V and RX is 0V.
>
>With no serial cable pc RX is -15V and RX is 0V.
>
>Is it fault?

I can't tell. You listed RX twice, and no TX for the PC :-)
The levels you have for the FPGA board is exactly what I wrote
you should expect.

If the first one for the PC is really "RX" and the second is "TX", then
this is wrong. You have the wrong labels (which is what I guessed was
your problem). The PC signal with -15 is a TX pin, not an RX pin.

>Marco

Getting closer.
Philip
Philip Freidin
Fliptronics

Article: 88728
Subject: Re: FPGA Development Board Wish List
From: Sylvain Munaut <com.246tNt@tnt>
Date: Fri, 26 Aug 2005 12:53:54 +0200
Links: << >>  << T >>  << A >>
John_H wrote:
> I think it's the Texas Instruments TFP501 and TFP510 (Rx and Tx) that are
> popular TMDS choices.  These came up with similar parts using a keyword
> search on DVI on the TI website.

Would you happen to know where to find theses for experimenting ? I
don't have any particular project in mind I just want to hook up one of
theses to experiment with. But I don't see them at digikey/mouser/farnel ...

(And being outside US I can't have samples from TI directly)


	Sylvain

Article: 88729
Subject: Writing to Spartan 3 SRAM
From: amir.intisar@gmail.com
Date: 26 Aug 2005 04:32:08 -0700
Links: << >>  << T >>  << A >>
Hello all, i am very new to FPGA design and struggling to understand
how to write data to Spartan 3 SRAM. I am using verilog and my code
looks like something bleow,
-------------------------------------------------------------------
cs = 1'b0;
ub = 1'b0;
lb = 1'b0;

we = 1'b0;
oe = 1'b1;

mem = i    // i is a counter and mem is an 18 bit memory address

end

assign data = (oe)? input_data : 16'bz // data is the memory data
-------------------------------------------------------------------
To my understanding this code will put the Input_data into memory
addrees i, but do i need to loop this code a few times because the SRAM
operates at 100 MHz, twice as fast as the 50Mhz FPGA.

What is the correct wat to write data to SRAM? ....Thanks !!!


Article: 88730
Subject: Re: Writing to Spartan 3 SRAM
From: Aurelian Lazarut <aurash@xilinx.com>
Date: Fri, 26 Aug 2005 14:41:33 +0100
Links: << >>  << T >>  << A >>
Amir,
welcome in the wonderful world of hardware!
you have to forget about C coding and start to learn  (any) HDL 
language, I wish it was that simple.
 
Aurash

amir.intisar@gmail.com wrote:

>Hello all, i am very new to FPGA design and struggling to understand
>how to write data to Spartan 3 SRAM. I am using verilog and my code
>looks like something bleow,
>-------------------------------------------------------------------
>cs = 1'b0;
>ub = 1'b0;
>lb = 1'b0;
>
>we = 1'b0;
>oe = 1'b1;
>
>mem = i    // i is a counter and mem is an 18 bit memory address
>
>end
>
>assign data = (oe)? input_data : 16'bz // data is the memory data
>-------------------------------------------------------------------
>To my understanding this code will put the Input_data into memory
>addrees i, but do i need to loop this code a few times because the SRAM
>operates at 100 MHz, twice as fast as the 50Mhz FPGA.
>
>What is the correct wat to write data to SRAM? ....Thanks !!!
>
>  
>


-- 
 __
/ /\/\ Aurelian Lazarut
\ \  / System Verification Engineer
/ /  \ Xilinx Ireland
\_\/\/
 
phone:	353 01 4032639
fax:	353 01 4640324
    
     

Article: 88731
Subject: Re: Writing to Spartan 3 SRAM
From: "Eric" <ericjohnholland@hotmail.com>
Date: 26 Aug 2005 07:44:10 -0700
Links: << >>  << T >>  << A >>
Xilinx has a good appnote

http://direct.xilinx.com/bvdocs/appnotes/xapp463.pdf

You can also download sample code off of their website
http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?sGlobalNavPick=&sSecondaryNavPick=&category=-1209899&iLanguageID=1


Eric


Article: 88732
Subject: Re: Best FPGA for floating point performance
From: "robin.bruce@gmail.com" <robin.bruce@gmail.com>
Date: 26 Aug 2005 07:53:49 -0700
Links: << >>  << T >>  << A >>
Regarding  x86 vs FPGA for double-precision floating-point arithmetic:

Good points about the relative performances, but you need to look at
more than the peak FLOPs/s to do a comparison between the
architectures. Non-trivial double precision algorithms running on
microprocessors can use anything between 5 and 90 % of their peak
FLOPs/s. Floating-point algorithms are typically memory bound for
microprocessors. FPGAs on the other hand are typically bound by peak
FLOPs/s. FPGAs are able to significantly outperform modern
microprocessors on memory bandwidth sensitive double precision
operations. Microprocessors still beat FPGAs for non-memory bound
operations because they have higher peak FLOPs/s, but this situation
won't last. Peak FLOPs/s for FPGAs are set to exceed those of uP's in
the not too distant future. To chase the increases in peak FLOPs/s on
microprocessors you need ever more complex memory hierarchies, while in
FPGAs it looks like it will be some time before such techniques will be
needed to get the most out of the floating-point units.


Article: 88733
Subject: Re: Best FPGA for floating point performance
From: "gantlord" <robin.bruce@gmail.com>
Date: 26 Aug 2005 08:16:08 -0700
Links: << >>  << T >>  << A >>
Oops, forgot to say where I'm getting this from:

Keith Underwood from Sandia Labs has been looking at this sort of
stuff. I'm just parroting it out here for you guys (I wouldn't anyone
thinking I'd been guilty of an original thought).

R


Article: 88734
Subject: Re: Issues with Synplify Pro 7.7 synthesis
From: "John_H" <johnhandwork@mail.com>
Date: Fri, 26 Aug 2005 16:15:30 GMT
Links: << >>  << T >>  << A >>
Did you instantiate a LUT2, LUT3, or LUT4 primitive?
Did you provide an INIT value on that primitive?
How did you apply the INIT?

It may be a simple mistake in the complete instantiation.

"Harish Vutukuru" <harish.vutukuru@gmail.com> wrote in message
news:1125023514.907773.224250@z14g2000cwz.googlegroups.com...
> Hello All,
>
> I am a graduate student in Computer Engineering an am developing some
> small VHDL modules targeted to Xilinx Virtex devices. While I was
> trying to synthesize some of those designs using synpliciy I got the
> following error." Invalid LUT instantiation. Have you included the
> virtex.v(hd) file, and an INIT value @E:Internal Error". I tried adding
> virtex.vhd from synplicity installation library and tried to re
> synthesize it and now I see an error " Undefined identifier" and it
> does not even point to the module which causes this. I have read in
> some other postings in this group that one should not include unisim
> libraries while synthesizing using Synplify pro 7.7. I have in fact
> tried both ways (including and excluding unisim libraries) but the
> above error persists. I would appreciate if anyone can suggest where I
> am doing wrong.
>
> Thanks
> Harish
>



Article: 88735
Subject: Phase Offset in Xilinx DDS Core
From: "AdamS" <sutongqi@gmail.com>
Date: 26 Aug 2005 09:25:16 -0700
Links: << >>  << T >>  << A >>
I'm now using Xilinx DDS Core(v5.0 in ISE7.1i).

I wanna generate 2 channels of sine wave, same frequency, different
phase offset.

But in the practice, the frequency of Sine wave turns out right, the
phase offset wrong. Even if I give both two channels 0 offset, they two
are not in a same phase.

at first I thought that may coused by my pulling down WE signal after I
write a data into the DDS core. But I found that's not the key after I
tried giving all the data in and then pulling down WE signal.

I can not find the reaseon now.
Does anyone could help?
Any suggestions would be appreciated.


Article: 88736
Subject: Re: i need some help ASAP !!! (DLL - Spartan-IIE)
From: "AdamS" <sutongqi@gmail.com>
Date: 26 Aug 2005 10:01:13 -0700
Links: << >>  << T >>  << A >>
you could refer to the XAPP174 on Xilinx website. It gives some codes
and those codes could be used in you design immediately.


Article: 88737
Subject: Re: Phase Offset in Xilinx DDS Core
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Fri, 26 Aug 2005 19:05:43 +0200
Links: << >>  << T >>  << A >>

"AdamS" <sutongqi@gmail.com> schrieb im Newsbeitrag
news:1125073516.015613.195090@g14g2000cwa.googlegroups.com...

> I can not find the reaseon now.
> Does anyone could help?
> Any suggestions would be appreciated.

Is there a reset for the phase accumulator in the core?

Regards
Falk




Article: 88738
Subject: Re: Kingston module structure
From: Duane Clark <dclark@junkmail.com>
Date: Fri, 26 Aug 2005 17:42:17 GMT
Links: << >>  << T >>  << A >>
jms019@gmail.com wrote:
> I have inherited a nearly-working FPGA SDRAM controller but my testing
> shows I have got the structure wrong, partly due to lack of data on
> Kingston's site.
> 
> The module in question is the Kingston KVR133X64C3/1G.
> 
> The verilog I have inherited caters for 11 column bits, 13 row bits, 4
> banks and two select lines. The module has sixteen chips on it which I
> thought might be eight bit each so there would have to be two chip
> select lines.
> 
> But my testing shows something wrong with the way I assign
> row/column/bank/cs. Maybe it is in fact 16 off 4 bit chips and just the
> one chip select but a test assuming that shows I'm still losing a bit
> somewhere.
> 
> So what is the structure of this module and does the column go out on
> A0-A9(,A11,A12) ? Googling throws up surprisingly little data given
> that I'm not out to buy them.
> 

The two addressing schemes I am aware of for 1GB DIMMs are:
row A0-A12  column A0-A9,A11
row A0-A13  column A0-A9

In my experience, the first is more common, and is the one I normally 
expect on a 16 chip DIMM.

I really don't understand what you mean by "Maybe it is in fact 16 off 4 
bit chips", so I can't address that. Micron supplies very good data 
sheets, so go get all the ones there for 1GB DIMMs. Even if your DIMM is 
not made by Micron, one of them probably matches what you have.

Article: 88739
Subject: Altera NIOS in a Cyclone
From: "GMM50" <george.martin@att.net>
Date: 26 Aug 2005 11:26:08 -0700
Links: << >>  << T >>  << A >>
Hi:

I'm trying to get a NIOS running in an Altera Cyclone FPGA.  I'm
configuring using a epcs (serial eeprom) then booting from FLASH.  THe
boot process copies a code image from FPASH to SDRAM then jumps to the
start in SDRAM.

Running under JTAG is not a problem.

Initially I had RESET* going high before ConfigDone* wnet high.  This
system would boot OK only if we left power off for 20 seconds or more.

I then linked RESET* to the end of ConfigDone* and this never boots.
I also added a delay between RESET* to the NIOS and the NIOS in the
fpga.
I used the DelayedReset block found in the Cyclone evaluation board
design.  But that didn't generate any delay.  I modified it to work but
no different.  Never booting.

I've put a logic analyzer on the fpga and see RESET* delayedReset and
data being read out of the FLASH.

Has anyone ever got something like this running???

George


Article: 88740
Subject: Re: Writing to Spartan 3 SRAM
From: "Vladislav Muravin" <muravinv@advantech.ca>
Date: Fri, 26 Aug 2005 14:38:48 -0400
Links: << >>  << T >>  << A >>
Amir...

Well, your question indicates that you come from the SW background.

The things are a little different in the sense that the way the code is 
supposed to be written is approximately the following
One alternative would be muiltiplying FPGA clock to get 100 MHz clock and 
use the following structure, which executed each time
there is a rising edge of the clock.

always @(posedge sys_clk or negedge sys_reset_n) // clock is
    begin
        if (!sys_reset_n)
            begin
            // reset here all the stuff
            end
        else
            begin

            end
        end

I hoope this information is sufficient from Verilog / HDL point of view.
The hardware point of view is up to you...

Vladislav


<amir.intisar@gmail.com> wrote in message 
news:1125055928.734971.272510@g49g2000cwa.googlegroups.com...
> Hello all, i am very new to FPGA design and struggling to understand
> how to write data to Spartan 3 SRAM. I am using verilog and my code
> looks like something bleow,
> -------------------------------------------------------------------
> cs = 1'b0;
> ub = 1'b0;
> lb = 1'b0;
>
> we = 1'b0;
> oe = 1'b1;
>
> mem = i    // i is a counter and mem is an 18 bit memory address
>
> end
>
> assign data = (oe)? input_data : 16'bz // data is the memory data
> -------------------------------------------------------------------
> To my understanding this code will put the Input_data into memory
> addrees i, but do i need to loop this code a few times because the SRAM
> operates at 100 MHz, twice as fast as the 50Mhz FPGA.
>
> What is the correct wat to write data to SRAM? ....Thanks !!!
> 



Article: 88741
Subject: Re: i need some help ASAP !!! (DLL - Spartan-IIE)
From: "Vladislav Muravin" <muravinv@advantech.ca>
Date: Fri, 26 Aug 2005 14:40:28 -0400
Links: << >>  << T >>  << A >>
Guys,

Sorry to bother all, i have had a stupid problem && mismatch to this xapp 
174.
I did it in the way i am used to do with V2.

thanks a lot

Vladislav

"AdamS" <sutongqi@gmail.com> wrote in message 
news:1125072899.766306.70410@g47g2000cwa.googlegroups.com...
> you could refer to the XAPP174 on Xilinx website. It gives some codes
> and those codes could be used in you design immediately.
> 



Article: 88742
Subject: ISE 7.1 and DCM clkfx
From: "Matthew Plante" <maplante@iol.unh.edu>
Date: Fri, 26 Aug 2005 15:10:58 -0400
Links: << >>  << T >>  << A >>
  I just upgraded to ISE 7.1.03i.  My old 6.3i design used some DCMs in a 
"not so legal" fashion, where I had CLKFX_DIVIDE = 33, and CLKFX_MULTIPLY = 
32.  My old version of ISE (6.3i) would actually accept the divide value and 
produce a working bit stream.  7.1 on the other hand actually complains 
during the mapping phase.  Is there a way to disable the checking of this 
and force it to accept those values?

Thanks,

-- 
-- Matt

+--
|Matthew Plante
| University of New Hampshire
| InterOperability Lab
| Research & Development
| SMTP: maplante@iol.unh.edu
| Phone: +1-603-862-0203
+-



Article: 88743
Subject: Re: Library of eBooks on FPGA's and other programming stuff
From: Ziggy <Ziggy@faked-address.com>
Date: Sat, 27 Aug 2005 01:28:19 GMT
Links: << >>  << T >>  << A >>
Dimitri Turbiner wrote:

> Hi everybody,
> 
> As I received some emails about the systemC books I had I decided to
> post this:
> 
> I'm a student so my interests still change rather fastly :D
> 
> Since books are really expensive and since I just want to get a "feel"
> of the topics I'm looking at, I picked the habit of getting myself a
> lot of ebooks.
> 
> Now the thing is that I've accumulated some collection already. But
> unfortunately I almost never really use them. (For the ones I liked I
> used I buy the real books...).
> 

Sorry, but at least 99.9% of those would be illegal to redistribute..

Not that people arent doing it every day, just be sure you undersand what
you are doing..

Article: 88744
Subject: SERDES
From: "Rob" <robnstef@frontiernet.net>
Date: Sat, 27 Aug 2005 04:40:04 GMT
Links: << >>  << T >>  << A >>
I'm trying to implement a SERDES interface within a Cyclone device.  I've 
set it up using a PLL, DDIO, a couple of shift registers, and some output 
DFF's.  I'm seeing some timing issues.  How do you compensate for shift 
(between the data clock and the serial data) that is caused due to the time 
the PLL takes to lock to the incoming clock?

My PLL is generating 2 clocks: the fast clock to deserialize the data 
(drives the DDIO and shift registers) and the slower data clock (which drive 
the output DFF's).  In my case I have a 66MHz data  clock and a 264MHz 
deserializer clock.

Thank you. 



Article: 88745
Subject: infering a BRAM block for a dual ported ROM
From: abgoyal@gmail.com
Date: 27 Aug 2005 01:46:03 -0700
Links: << >>  << T >>  << A >>
Hi,

I have been trying to implementa a 256-deep, 8-bit wide ROM as a BRAM
in Xilinx Virtex 4 and Spartan 3(ISE7.1sp2). Prefering to have it
inferred instead of instantiating a macro, i wrote it out as a case
statement in verilog. ISE correctly infers a block RAM for it.

My problem is i want to do two simultaneous reads from the same ROM
(the reads are done on independent clocks). If i implement this as two
seperate case statements, even with the exact same data, ISE infers two
blockRAMs for them, leaving the second port of each unused.

always @ (posedge clk0)
begin
   case(addr0)
       8'h00: data0 = 8'h12;
       ....................
       8'hff: data0 = 8'h34;
   endcase
end

always @ (posedge clk1)
begin
   case(addr1)
       8'h00: data1 = 8'h12;
       ....................
       8'hff: data1 = 8'h34;
       //(exact same data as above)
   endcase
end


Is there a way i can write my verilog so that ISE can infer that i am
reading the same ROM, and infer a single, dual-ported RAM block?

I know i can work around it by instantiating a dualport BRAM, i was
just wondering if there was a way to have ISE infer it.



Any suggestions appreciated.

Thanks in Advance, 

Abhishek


Article: 88746
Subject: 36x36 signed multiplier?
From: "Bubba" <blabla@bredband.net>
Date: Sat, 27 Aug 2005 11:51:28 +0200
Links: << >>  << T >>  << A >>
Multiplier



Is there a good algorithm (small) to multiply two 36 bit “signed” numbers to
get a 72 bit result.



Is it possible to divide the 36 bit numbers into 18 bit parts and multiply
them separately and after some shifting add the results?



I would like to instantiate the MULT18X18 in the Spartan3 for this.



When I write it strait like this without any specific instantiation:



library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;



entity test is

    Port ( a : in std_logic_vector(35 downto 0);

           b : in std_logic_vector(35 downto 0);

           q : out std_logic_vector(71 downto 0));

end test;



architecture Behavioral of test is



begin

  q <= signed(a)*signed(b);



end Behavioral;





It uses 9 MULT18X18!!!!!








Article: 88747
Subject: Re: 36x36 signed multiplier?
From: "Thomas Entner" <aon.912710880@aon.at>
Date: Sat, 27 Aug 2005 12:05:04 +0200
Links: << >>  << T >>  << A >>
As far as I know, this should be possible with 4 multipliers, if everything 
is unsigned. I could imagine that you also get away with 4 signed 
multipliers, if you cut a bit or two from your a and b.

Regards,

Thomas

www.entner-electronics.com

"Bubba" <blabla@bredband.net> schrieb im Newsbeitrag 
news:431037f6$0$18636$14726298@news.sunsite.dk...
> Multiplier
>
>
>
> Is there a good algorithm (small) to multiply two 36 bit "signed" numbers 
> to
> get a 72 bit result.
>
>
>
> Is it possible to divide the 36 bit numbers into 18 bit parts and multiply
> them separately and after some shifting add the results?
>
>
>
> I would like to instantiate the MULT18X18 in the Spartan3 for this.
>
>
>
> When I write it strait like this without any specific instantiation:
>
>
>
> library IEEE;
>
> use IEEE.STD_LOGIC_1164.ALL;
>
> use IEEE.STD_LOGIC_ARITH.ALL;
>
> use IEEE.STD_LOGIC_UNSIGNED.ALL;
>
>
>
> entity test is
>
>    Port ( a : in std_logic_vector(35 downto 0);
>
>           b : in std_logic_vector(35 downto 0);
>
>           q : out std_logic_vector(71 downto 0));
>
> end test;
>
>
>
> architecture Behavioral of test is
>
>
>
> begin
>
>  q <= signed(a)*signed(b);
>
>
>
> end Behavioral;
>
>
>
>
>
> It uses 9 MULT18X18!!!!!
>
>
>
>
>
>
> 



Article: 88748
Subject: Re: Phase Offset in Xilinx DDS Core
From: "AdamS" <sutongqi@gmail.com>
Date: 27 Aug 2005 04:06:58 -0700
Links: << >>  << T >>  << A >>
only one sentence got to the key point

Thanks a lot^_^


Article: 88749
Subject: Re: 36x36 signed multiplier?
From: Sylvain Munaut <com.246tNt@tnt>
Date: Sat, 27 Aug 2005 13:09:54 +0200
Links: << >>  << T >>  << A >>
Bubba wrote:
> Multiplier
> 
> 
> 
> Is there a good algorithm (small) to multiply two 36 bit “signed” numbers to
> get a 72 bit result.
> 
> 
> 
> Is it possible to divide the 36 bit numbers into 18 bit parts and multiply
> them separately and after some shifting add the results?

Sure, google for "Karatsuba multiplication"
You should achieve that with just 3 multiplier and some adders.


> library IEEE;
> use IEEE.STD_LOGIC_1164.ALL;
> use IEEE.STD_LOGIC_ARITH.ALL;
> use IEEE.STD_LOGIC_UNSIGNED.ALL;
> 
> entity test is
>     Port ( a : in std_logic_vector(35 downto 0);
>            b : in std_logic_vector(35 downto 0);
>            q : out std_logic_vector(71 downto 0));
> end test;
> 
> architecture Behavioral of test is
> begin
>   q <= signed(a)*signed(b);
> end Behavioral;
> 
> 
> It uses 9 MULT18X18!!!!!

Try with USE IEEE.STD_LOGIC_SIGNED.ALL



	Sylvain



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