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A stupid question but... If you are using a daughterboard and are only reading 0V, are you sure that: - The daughterboard is correctly connected - You use the proper IO pins on FPGAArticle: 87126
You are probably missing the declaration of the attribute. attribute syn_preserve : boolean; muthusnv@rediffmail.com wrote: > I used the syn_preserve synplify attribute in my VHDL code as below. > > attribute syn_preserve of sign1: signal is true; > > Modelsim gives compilation error for this? Any help to rid of this > would be appreciated. > > Thanks, > Muthu >Article: 87127
Sven wrote: > Hi, > > i try to build a dynamic reconfiguration application with use of icap > and the embedded powerpc. By reverse engineering i found a lot of the > bit-combinations in the configuration-frames, which handle the routing > in the switch-boxes. The reverse engineering process takes a lot of > time. I think anybody can give me the remaining bit-combinations in the > frames? > > Thanks, Sven > I've tried doing that as well. It's really hard to get the whole picture with reverse engineering. I gave up after a few months. Try to follow the approach in XAPP260 to do modular reconfiguration.Article: 87128
Alternately, you could include the Synplicity library, which defines the attributes. But I typically do it the way Ken suggested. JTW "Ken McElvain" <ken@synplicity.com> wrote in message news:6H%Be.18719$Tf5.8379@newsread1.mlpsca01.us.to.verio.net... > You are probably missing the declaration of the > attribute. > > attribute syn_preserve : boolean; > > muthusnv@rediffmail.com wrote: >> I used the syn_preserve synplify attribute in my VHDL code as below. >> >> attribute syn_preserve of sign1: signal is true; >> >> Modelsim gives compilation error for this? Any help to rid of this >> would be appreciated. >> >> Thanks, >> Muthu >> >Article: 87129
Chinix wrote:
> _reset is a global input signal,so it won't be influenced by the upper
> leven unit,i think.
> i simulated and synthesized the module independently,it all went
> well,so i don't think an underscore makes any differents.
Hi,
I think the way code is written might be the problem. In the following
line:
if(div_coef==14'b0) freq_out=0;
the status of the counter signal when the condition (div_coef==14'b0)
is met is not specified. This might be throwing the synthesizer off the
track.
Modify the line as
if(div_coef==14'b0)
begin
freq_out=0;
counter = 14'b0;
end
then try synthesizing.
Article: 87130Dear john... Please tell me the reset condition of internal counters. Is there any way to initialize the counter also with preset values.Article: 87131
Yes I did, those are the only IO pins that I can use and it is correctly connected.Article: 87132
Hello. I am trying to use the ML402 virtex4 (SX35) board and facing some problems getting the FPGA to configure. I dont have a PC4 programming cable, and am using the System ACE to do it for me. After i generate a Bitstream (no errors), i put it on the Compact flash and let the system ace program it to the linear (CPLD) flash using the flah programming bitstream provided in the board demo. The programming of the flash finishes fine, but then when i try to have the FPGA configured using the linear FLASH, i never get a "Done" led, and the two "err" leds on the board glow (but really faintly). The combinations i have seen are these: 1. system.bit confugures properly, but download.bit (which has its bram updated with the micrblaze software program) does not (giving the faintly glowing err LEDS. 2. sometimes both system.bit and download.bit fail to configure. 3. Sometimes, when both fail, if i generate the ACE file, that works. I am using ISE7.1sp3 with EDK7.1sp2 (latest). I am using the base system builder wizard and only adding peripherals included with the EDK. Can someone please tell me what i could be doing wrong? What is the meaning of those two "err" leds on the board glowing faintly? Any help/suggestion appreciated. Thanks, -AbArticle: 87133
has anyone been able to run SP3 on a Fedora Core 3 system? SP2 worked fine but SP3 is broken. Running XST gets, xst: error while loading shared libraries: /usr/local/tools/Xilinx/bin/lin/libSTL.so: cannot restore segment prot after reloc: Permission denied Anyone know how to deal with this?Article: 87134
I try to simulate the following code on ModelSim via ISE 6.3.
Behavioural, Post-Translate and Post-Mapping Simulation are work.
When i simulate post-place & route, the output pattern isn't correct.
I use dataflow in ModelSim to trace the problem source and found a
glicth before occur unknow signal. I try to decrease clock frequency.
No change from previous, it has glicth before occur unknow signal.
Both situation (before and after change clock frequency), occuring
glicth is very near before rising edge of clock.
My environment
==============
ISE 6.3 (I try on ISE 7.1 but it's incorrect)
ModelSim
VHDL code of test1.vhd.
--------------- test code (start) ---------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity test1 is
Port ( rst : in std_logic;
clk : in std_logic;
a : in std_logic_vector(7 downto 0);
b : in std_logic_vector(7 downto 0);
sum : out std_logic_vector(7 downto 0);
prod : out std_logic_vector(15 downto 0));
end test1;
architecture Behavioral of test1 is
begin
process (rst, clk)
begin
if rst='1' then
sum <= (sum'range=>'0');
prod <= (prod'range=>'0');
elsif clk'event and clk='1' then
sum <= a + b;
prod <= a * b;
end if;
end process;
end Behavioral;
--------------- test code (end) -----------------------
Testbench of test1.vhd that i use.
--------------- testbench for test code (start) -------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
ENTITY test1_tb_test1_vhd_tb IS
END test1_tb_test1_vhd_tb;
ARCHITECTURE behavior OF test1_tb_test1_vhd_tb IS
COMPONENT test1
PORT(
rst : IN std_logic;
clk : IN std_logic;
a : IN std_logic_vector(7 downto 0);
b : IN std_logic_vector(7 downto 0);
sum : OUT std_logic_vector(7 downto 0);
prod : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
SIGNAL rst : std_logic;
SIGNAL clk : std_logic;
SIGNAL a : std_logic_vector(7 downto 0);
SIGNAL b : std_logic_vector(7 downto 0);
SIGNAL sum : std_logic_vector(7 downto 0);
SIGNAL prod : std_logic_vector(15 downto 0);
BEGIN
uut: test1 PORT MAP(
rst => rst,
clk => clk,
a => a,
b => b,
sum => sum,
prod => prod
);
clk_gen : PROCESS
BEGIN
if clk='0' then
clk <= '1';
else
clk <= '0';
end if;
wait for 100 ns;
END PROCESS;
tb : PROCESS
BEGIN
wait for 100 ns;
rst <= '1';
a <= conv_std_logic_vector (0, 8);
b <= conv_std_logic_vector (0, 8);
for i in 1 to 10 loop
wait until clk'event and clk='1';
end loop;
wait for 1 ns;
rst <= '0';
for i in 1 to 10 loop
wait until clk'event and clk='1';
end loop;
wait for 1 ns;
a <= conv_std_logic_vector (11, 8);
b <= conv_std_logic_vector (13, 8);
wait until clk'event and clk='1';
wait for 1 ns;
a <= conv_std_logic_vector (77, 8);
b <= conv_std_logic_vector (19, 8);
wait until clk'event and clk='1';
wait for 1 ns;
wait; -- will wait forever
END PROCESS;
END;
--------------- testbench for test code (end) ---------
screenshot on ModelSim
http://putfile.com/pic.php?pic=7/19616551426.png&s=x2
http://putfile.com/pic.php?pic=7/19616563230.png&s=x2
http://putfile.com/pic.php?pic=7/19616564480.png&s=x2
Article: 87135Above question, i use virtex 4 as device. Now i change device as spantan-3 and virtex II and do post-place & route simulation again. I surprise the signal patterns're correct. I think something are incorrect. It may be post-place & route simulation vhdl file that ISE generate.Article: 87136
"Dear john" ...my oh my. Counters are registers. 1) You can always use the INIT=S and INIT=R attributes on the individual bits of the counter word in your ucf file. 2) If you're using XST, you might be able to use the initial definition reg [7:0] counter = 7'ha5; // to initialize to hex value a5 3) If you're using Synplify, see 1). 4) If you're using something else I can't help you any further. "vssumesh" <vssumesh_asic@yahoo.com> wrote in message news:1121499199.346589.76710@o13g2000cwo.googlegroups.com... > Dear john... > Please tell me the reset condition of internal counters. Is there any > way to initialize the counter also with preset values.Article: 87137
vssumesh wrote:
> Hello all,
> Is there any way i can initialise values into the Xilinx FPGA FF. I
> am working on the Virtex E FPGA. Please tell me how can i achive that
> through verilog.
Ummmm, how about this simplest, and most portable way?
always @(posedge clk or negedge rst_l) begin : FlopWithInit
if (~rst_l) begin
q <= '1'; -- if you want to preset the flop
end else begin
q <= d;
end
end // block FlopWithInit
or, if you want to initialize a register to some constant you've
defined:
parameter INITVAL = 16'hDEAD;
always @(posedge clk or negedge rst_l) begin : FlopsWithInit
if (~rst_l) begin
qq <= INITVAL;
end else begin
qq <= dd;
end
end // block FlopsWithInit
The trick is that you need a reset signal, but helpful the FPGA
families have power-on global resets that are asserted as part of the
configuration process.
-a
Article: 87138Try disabling selinux--Security Enhanced Linux. Paul "B. Joshua Rosen" wrote: > > has anyone been able to run SP3 on a Fedora Core 3 system? SP2 worked fine > but SP3 is broken. Running XST gets, > > xst: error while loading shared libraries: /usr/local/tools/Xilinx/bin/lin/libSTL.so: > cannot restore segment prot after reloc: Permission denied > > Anyone know how to deal with this?Article: 87139
On Sat, 16 Jul 2005 17:23:59 -0700, Paul Hartke wrote: > Try disabling selinux--Security Enhanced Linux. > > Paul > > "B. Joshua Rosen" wrote: >> >> has anyone been able to run SP3 on a Fedora Core 3 system? SP2 worked fine >> but SP3 is broken. Running XST gets, >> >> xst: error while loading shared libraries: /usr/local/tools/Xilinx/bin/lin/libSTL.so: >> cannot restore segment prot after reloc: Permission denied >> >> Anyone know how to deal with this? Thanks, that's it.Article: 87140
If you've purchased a board that doesn't already have on board RAM for you to work w/ then you'll need to make another baord with the RAM chips you want and connect the two via any off chips connectors that maybe available on your custom board. Then you'll need to develop the core to actually read and write to the RAM. Of course, the complexity of that core depends on what kind of RAM you'll be using, SDRAM, SRAM, etc.Article: 87141
Are you looking for bi directional I/O, or a one way?Article: 87142
dear I implemented some multiprocessors and some routers. 3 processors exchange data via routers and store into local memory. Functional VHDL simulation in MODELSIM seems okay. The VHDL code is synthesizable. BRAM was the only Xilinx resource that I used. Now I need to verify in real hardware using implementing and mapping into FPGA (vertex II pro and BRAM). My goal is only to see 'memory' value after 'data transfer' via routers. As far I found, it seems there are two ways to do that. First, host and FPGA serially communicate using UART module and hyperterminal. Second, chipscrop pro core can be synthesized with my logic. I am newbie on these things -: I am wondering what is more efficient, or if there is another way to see Block-RAM values. If I use 'serial' communication, I could use Xilinx 'UART' module but question is that - Can we see memory values on 'hyperterminal'? If I use 'Chipscope pro', there seems too many cores (ICON,ILA,ATC,IBA,VIO), and area overhead seems too big. Question is that - What kind of Chipscope core do I need to see memory values? - How much slices(CLB) those core consume? - Are there any examplary tutorial for chipscrop to follow up? Thankyou in advanceArticle: 87143
"pasacco" <pasacco@gmail.com> schrieb im Newsbeitrag news:1121590148.261935.211360@g43g2000cwa.googlegroups.com... > dear > > I implemented some multiprocessors and some routers. > 3 processors exchange data via routers and store into local memory. > Functional VHDL simulation in MODELSIM seems okay. The VHDL code is > synthesizable. BRAM was the only Xilinx resource that I used. > > Now I need to verify in real hardware using implementing and mapping > into FPGA (vertex II pro and BRAM). > > My goal is only to see 'memory' value after 'data transfer' via > routers. > > As far I found, it seems there are two ways to do that. > First, host and FPGA serially communicate using UART module and > hyperterminal. > Second, chipscrop pro core can be synthesized with my logic. > > I am newbie on these things -: I am wondering what is more efficient, > or if there is another way to see Block-RAM values. > > If I use 'serial' communication, I could use Xilinx 'UART' module but > question is that > > - Can we see memory values on 'hyperterminal'? > > If I use 'Chipscope pro', there seems too many cores > (ICON,ILA,ATC,IBA,VIO), and area overhead seems too big. > > Question is that > - What kind of Chipscope core do I need to see memory values? > - How much slices(CLB) those core consume? > - Are there any examplary tutorial for chipscrop to follow up? > > Thankyou in advance > Hi there is nothing directly useable for your 'see memory' if you use UART then its all up to you how you implement the protocol chipscope can be 'peek' the content of BRAM but you could just attach chiscope in parallel to the write port(s) of your BRAMs so chipscope could trigger and start recording in parallel during the RAM write, it would not give you the exact BRAM readback but maybe its even more useful for debugging as third option the BRAM readback is possible but you need to develop your own custom JTAG software for that, and that could be time consuming. I would just connect chipscope ILA, the resource useage depends on the parameters and can not be estimated before the ILA core is parametrized AnttiArticle: 87144
pasacco wrote: > I implemented some multiprocessors and some routers. > 3 processors exchange data via routers and store into local memory. > Functional VHDL simulation in MODELSIM seems okay. The VHDL code is > synthesizable. BRAM was the only Xilinx resource that I used. > Now I need to verify in real hardware using implementing and mapping > into FPGA (vertex II pro and BRAM). > My goal is only to see 'memory' value after 'data transfer' via > routers. You can "see" the block RAM array in action using Modelsim in a functional sim if you infer it from a code template. -- Mike TreselerArticle: 87145
Hi I used 'INIT_00' ,... statements...to initialize BRAM. After running simple application, I could able to 'see' block RAM contents as expected in Modelsim functional simulation. So 'simulation' seems okay. Now I would map into FPGA and then would like to see the memory behavior as the behavior in a simulation. I would try both ways 'UART + Terminal software' and 'Chipscrope pro' ... 'chipscope pro' first :) Thankyou very much for commentArticle: 87146
bjskill@rocketmail.com wrote: > Hi, > > We will soon be using the Nios II as embedded controller and we would > like to add a High Speed (HS) USB 2.0 hosting feature that is capable > or providing a sustained transfer rate of 20 MBytes/sec. to an external > HS USB 2.0 device. Brad, Our USB 2.0 HS host can sustain close to 56Mbytes/sec. Best Regards, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and Synthesis ****** Certified USB 2.0 HS OTG and HS Device IP Cores ****** > I realize that there are a limited number of HS USB 2.0 hosts > devices/IP cores currently available. The Phillips ISP1761 is the only > HS USB 2.0 component I was able to locate so far and it's not clear to > me if this part is readily available. Also, the FPGA-based HS USB 2.0 > host IP cores look like they are just now becoming available > (www.asics.ws) but they may be cost-prohibitive. > > Can anyone share their experiences in implementing either a HS USB 2.0 > or Full Speed (FS) USB 1.1 host? Is a sustained transfer speed of 20 > MBytes/sec. achievable with the assumptions that there are no major > transfer bottlenecks in the HS USB 2.0 host component or the associated > HS USB 2.0 device (e.g. USB Hard Disk). If not, what is a more > reasonable transfer speed goal that has a high probability of success? > > The choice of which OS with Nios II (or no OS at all) may also be > influenced by the max. sustained HS USB 2.0 transfer speed that can be > achieved. However, it's also possible that in order to meet the 20 > MBytes/sec. goal, the Nios II will have to be "removed" from the data > I/O path so that custom FPGA circuitry can handle the transfers > directly with the external HS USB 2.0 host transceiver or the IP core. > > Any information and/or opinions would be helpful. > > Sincerely, > Brad.Article: 87147
Rudi, Do you have any published benchmarks for your USB 2.0 HS host running on the Altera Stratix II EP2S90 FPGA? Also, to your knowledge to you know of any USB 2.0 devices that can sustain close to the 56 MByytes/sec rate (e.g. Hard Disk). Brad.Article: 87148
The maximum sample rate of SignalTap depends on, in order of importance: 1. device (faster device families run SignalTap faster) 2. speed grade 3. SignalTap options. The strongest effect is from the number of acquisition channels being used in the trigger condition -- larger numbers slow the maximum acquisition rate down some. For the fastest Stratix speed grade (-5), the maximum acquisition rate varies from about 200 MHz to about 270 MHz, depending on the SignalTap options you select. For the Stratix -7 speed grade, maximum acquisition rate varies from about 160 MHz to about 220 MHz, again depending on your SignalTap options. So 80 MHz definitely shouldn't be a problem. Since Stratix II is 50% faster than Stratix on average, a Stratix II-3 should run SignalTap approximately 50% faster than the Stratix-5 number above, but I don't have hard results on that in front of me. Regards, Vaughn Altera [v b e t z (at) altera.com] <jjlindula@hotmail.com> wrote in message news:1121029204.541149.52990@g14g2000cwa.googlegroups.com... > We are using the Stratix. > joe > > Thomas Entner wrote: >> <jjlindula@hotmail.com> schrieb im Newsbeitrag >> news:1120839025.730535.307150@g47g2000cwa.googlegroups.com... >> > Hello, >> > >> > My FPGA is running at 80Mhz and I've heard the max sample rate is >> > 50Mhz, so I just wanted to see if it can go higher. >> > >> > joe >> > >> >> If you have a "modern" FPGA, 80MHz should be no problem for SignalTap... >> >> Thomas >Article: 87149
Hi Junaid, I assume you're asking what this report means. > Wirelength results (all in units of 1 clb segments): > Total wirelength: 24 Average net length: 2.40000 > Maximum net length: 5 This gives the amount of wire used to route your design, where each unit of wire is a "wire segment" that spans 1 clb. You have 10 nets in your design, and the routing of said nets spans 24 wire segments, giving an average of 2.4 wire segments per net. The longest routed net was 5 net segments. > Wirelength results in terms of physical segments: > Total wiring segments used: 24 Av. wire segments per net: > 2.40000 > Maximum segments used by a net: 5 This gives the wiring in terms of the number of pre-fabricated wires used between logic blocks (clbs/LABs). In the example report you've posted, you must be using a routing architecture where every wire is only one logic block long, since this summary is the same as the summary above it. If you had longer wires (say wires that spanned 4 clbs before they went through a programmable switch), then the number of "physical segment wires" would be smaller (6) than the wires in terms of 1-logic-block-long segments (24). Hope this helps, Vaughn Altera (but with my academic hat on) [v b e t z (at) altera.com] "junaid" <k.najeeb@gmail.com> wrote in message news:1120580001.595173.137780@g49g2000cwa.googlegroups.com... >I need more information wirelength results given by VPR > for ex: > > Wirelength results (all in units of 1 clb segments): > Total wirelength: 24 Average net length: 2.40000 > Maximum net length: 5 > > Wirelength results in terms of physical segments: > Total wiring segments used: 24 Av. wire segments per net: > 2.40000 > Maximum segments used by a net: 5 > > Kindly help me > > Tanx in advance > > > junaid >
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